DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-7 in the reply filed on 02/02/2026 is acknowledged.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claims 1, 3 and 7 are objected to because of the following informalities:
(Original) A semiconductor memory device comprising:
at least one first insulating layer among the plurality of first insulating layers in a first region along the stacking direction of the first stacked body above a lowermost one of the first insulating layers of the first stacked body is thicker than the first insulating layers of the plurality of first insulating layers in a second region…
3. (Original) The semiconductor memory device according to claim 1, wherein multiple first insulating layers in the first region are each thicker than the first insulating layers in the second region.
7. (Original) The semiconductor memory device according to claim 1, further comprising:
wherein at least one second insulating layer among the plurality of second insulating layers in a third region along the stacking direction of the second stacked body above of the first stacked body is thicker than the second insulating layers of the plurality of second insulating layers in a fourth region…
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hwang et al. US 2021/0375905 in view of Jang et al. US 2022/0020766.
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Hwang et al. US 2021/0375905
Regarding claim 1, Hwang et al. in Fig. 28 and [0013]-[0153] discloses a semiconductor memory device comprising:
a lower layer film 520;
a first stacked body ST1 [0022] above the lower layer film 520 and having a plurality of first conductive layers WS [0073] and a plurality of first insulating layers 112 and 116 [0019], [0038] alternately stacked on each other along a stacking direction; and
a first pillar 150H and160H [0029], [0055] that penetrates through the first stacked body ST1 to reach the lower layer film Figs, 6-16 and has a memory cell formed at each intersection with the plurality of first conductive layers WS Fig. 16, [0073]-[0078].
Hwang et al. discloses at least one first insulating layer 114 among the plurality of first insulating layers 112 in a first region along the stacking direction of the first stacked body ST1 above a lowermost one of the first insulating layers 112 of the first stacked body ST1 and the first insulating layers 116 of the plurality of first insulating layer 116 in a second region above the first region in the stacking direction of the first stacked body ST1 (i.e. any region above ST1 including ST2), and
the first pillar has: (Fig. 28, annotated above)
a first bowing shape at a height position along the stacking direction of the at least one first insulating layer 114, and
a second bowing shape at a height position along the stacking direction in the second region.
Hwang et al. does not expressly disclose wherein at least one first insulating layer 114 among the plurality of first insulating layers 112 in a first region along the stacking direction of the first stacked body ST1 above a lowermost one of the first insulating layers 112 of the first stacked body ST1 is thicker than the first insulating layers 116 of the plurality of first insulating layer 116 in a second region above the first region in the stacking direction of the first stacked body ST1 (i.e. any region above ST1 including ST2).
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Jang et al. US 2022/0020766
However, in analogous art, Jang et al. in Fig. 3 and [0002], [0053] teaches a three-dimensional semiconductor memory device including a vertical channel film and an insulating film 125 thicker than an insulating film 120 of a sub-stacked structure ST1 and a sub-stacked structure ST2, having improved element performance and integration.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Jang et al. in the device of Hwang et al. for the purpose of enhancing the device performance and the degree of integration.
Regarding claim 5, Hwang et al. in view of Jang et al. teaches the semiconductor memory device according to claim 1. Hwang et al. teaches wherein the first pillar tapers inwardly in diameter from the maximum diameter of the first bowing shape toward the lower layer film in the stacking direction, Fig. 15.
Regarding claim 6, Hwang et al. in view of Jang et al. teaches the semiconductor memory device according to claim 1. Hwang et al. teaches wherein the second bowing shape has a maximum diameter at a top surface of the first stacked body ST1 (Fig. 28, annotated above).
Allowable Subject Matter
Claims 2-4 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 2 is allowed because the prior art neither anticipates nor renders obvious, in the context of the claims, wherein, when a height of a top surface of the first stacked body from a bottom surface of the first stacked body is set to a value of 100%, the at least one first insulating layer in the first region is at a height position in a range of 20% to 50% of the height of the top surface from the bottom surface.
Claim 3 is allowed because the prior art neither anticipates nor renders obvious, in the context of the claims, wherein multiple first insulating layers in the first region are each thicker than the first insulating layers in second region.
Claim 4 directly depends from claim 3.
Claim 7 is allowed because the prior art neither anticipates nor renders obvious, in the context of the claims, further comprising:
a second stacked body above the first stacked body and having a plurality of second conductive layers and a plurality of second insulating layers alternately stacked on each other along the stacking direction; and
a second pillar that penetrates through the second stacked body to reach a top surface of the first pillar in the first stacked body and has a memory cell formed at each intersection with the plurality of second conductive layers, wherein at least one second insulating layer among the plurality of second insulating layers in a third region along the stacking direction of the second stacked body above of the first stacked body is thicker than the second insulating layers of the plurality of second insulating layer in a fourth region above the third region in the stacking direction of the second stacked body, and the second pillar has:
a third bowing shape at a height position along the stacking direction of the at least one second insulating layer, and
a fourth bowing shape at a height position along the stacking direction in the second region.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SONYA D MCCALL-SHEPARD whose telephone number is (571)272-9801. The examiner can normally be reached M-F: 8:30 AM-5:00 PM.
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/Sonya McCall-Shepard/Primary Examiner, Art Unit 2898