DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 28, 2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Koltsidas et al. (Pub. No. US 2012/0131265) in view of Post et al. (Pub. No. US 2012/0221767).
Claim 1:
Koltsidas et al. disclose a data processing system comprising:
a plurality of memory devices including a first memory device and a second memory device [figs. 1-2; pars. 0050, 0054 – Second level cache and storage device. (“The second level cache is embodied as a solid state memory device.” … “The storage device 2 includes multiple hard disk drives 21, only a few of which are illustrated in FIG. 1. The hard disk drives 21 preferably are arranged in one or more Redundant Arrays of Independent Disks, abbreviated as RAID.”)]; and
a fabric instance including a buffer [figs. 1-2; par. 0055 – “The first level cache 361 in the present example is embodied in a dynamic random access memory DRAM device. The first level write cache 361 in the present example can physically be realized as a part of the random access memory 32 of the storage controller 3.”],
wherein the fabric instance is configured to:
receive write data including first data and second data, associated with the first data, from the at least one host [figs. 1-2; par. 0046 – Data is received from the host. The association between different data may be that it is from the same host. Examiner suggests clarifying the association between the data. (“As such, the two level cache design follows a concept that a data unit residing in the write cache structure can either reside in the first level cache or in the second level cache, such that when a data unit is received from a host it needs to travel the first level cache first and the second level cache second before leaving the second level cache for being written to the storage device.”)];
store the second data in the buffer [figs. 1-2; par. 0046 – Data is stored in the first level cache. Data is stored individually. In other words, first data may be stored and second data may be stored without including the first data. (“As such, the two level cache design follows a concept that a data unit residing in the write cache structure can either reside in the first level cache or in the second level cache, such that when a data unit is received from a host it needs to travel the first level cache first and the second level cache second before leaving the second level cache for being written to the storage device.”)];
transfer the first data to the first memory device [figs. 1-2; par. 0046 – Data is stored in the second level cache. (“As such, the two level cache design follows a concept that a data unit residing in the write cache structure can either reside in the first level cache or in the second level cache, such that when a data unit is received from a host it needs to travel the first level cache first and the second level cache second before leaving the second level cache for being written to the storage device.”)]; and
transfer the second data from the buffer to the second memory device at a preset timing after transferring the first data [par. 0064 – Data is transferred to the storage device at a certain timing. (“After a certain time all existing k groups, or, alternatively, when k groups of data units are stored in the second level cache, or, alternatively, at a certain point in time identifying the k oldest groups of data units, then a transfer of the data units of the k groups to the storage device is initiated.”)].
However, Koltsidas et al. do not specifically disclose,
the first data is transferred without storing the first data in the buffer;
In the same field of endeavor, Post et al. disclose,
the first data is transferred without storing the first data in the buffer [fig. 5; pars. 0080-0093 – “Once the control circuitry receives those additional write commands, the control circuitry can combine the additional write commands with the set of the most recently received commands into a write-multi command. The control circuitry can then direct a bus controller to dispatch the write-multi command from queue 502 to NVM 510. Consequently, the control circuitry can bypass buffer 522 for sequential write commands.”];
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Koltsidas et al. to include bypassing a buffer, as taught by Post et al., in order to improve performance by improving efficiency.
Claim 2 (as applied to claim 1 above):
Koltsidas et al. disclose,
wherein the first memory device is configured to operate at a faster data input/output speed than the second memory device [figs. 1-2; pars. 0050-0055 – “Although flash memory devices are more expensive than hard disk drives, they are faster to access and consume significantly less energy.”].
Claim 9 (as applied to claim 1 above):
Koltsidas et al. disclose, wherein the fabric instance is further configured to:
generate, when a read request for the write data is input from the host, a first read request regarding the first data and a second read request regarding the second data, and check whether the second data is stored in the buffer before transferring the first and second read requests to the plurality of memory devices [pars. 0048, 0054 – Host issues read requests. Storage system processes the read commands. The cache is searched for the data before reading from disk. (“However, whenever the data unit is used e.g. for being updated or for supporting reading requests, the flag is set to one.” … “Hence, the host 4 issues read and/or write commands to the storage system 1.”)].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over McGlone et al. (Pub. No. US 2015/0254202) in view of Olarig et al. (Pub. No. US 2018/0210785) and Post et al. (Pub. No. US 2012/0221767).
Claim 18:
McGlone et al. disclose a data processing system comprising:
a plurality of hosts each host comprising a root port [fig. 2; par. 0038 – Hosts (“As such, the IOMC 140 may receive an indication to verify a connection between a root port (i.e., host) and a plurality of endpoint devices that were specified in the configuration process as those devices to be connected for that particular root port.”)];
a plurality of logical devices comprising a plurality of first logical devices storing user data [fig. 2; par. 0030 – PCIe endpoint devices. (“In the embodiment shown, one or more PCIe endpoint devices 216, 218, 220 are connected to the downstream ports 209-1, 209-2, 209-3, respectively, and may provide I/O capabilities and/or additional storage or memory which each server 210, 212, 214 may access via the switch modules.”)];
However, McGlone et al. do not specifically disclose,
at least one second logical device storing secondary data associated with the user data; and
a fabric manager configured to:
receive a command for data input/output from the plurality of hosts,
generate plural sub commands for first user data and first secondary data, associated with the first user data, in response to the command,
store the first secondary data in a buffer according to a first sub command for the secondary data among the plural sub commands; and
transfer, to the plurality of first logical devices, the first user data with a second sub command for the user data among the plural sub commands.
In the same field of endeavor, Olarig et al. disclose,
at least one second logical device storing secondary data associated with the user data [par. 0039 – “In some embodiments, one or more of the storage devices 105 are dedicated to the storage of erasure codes only.”]; and
a fabric manager configured to:
receive a command for data input/output from the plurality of hosts [par. 0040 – “In operation, when a storage device 105 receives a write command through the Ethernet switch 110, it may store the data (i.e., the data of the data block included in the write command) in nonvolatile memory internal to the storage device 105, and send a copy of the data, as well as the logical block address, to the controller 115.”],
generate plural sub commands for first user data and first secondary data, associated with the first user data, in response to the command [par. 0046 – “As described in further detail below, in some embodiments, in normal operation, when a write command is executed, the data to be stored are written to one or more storage devices 105, and erasure codes are generated and also written to one or more storage devices 105, with the erasure codes stored, for example, on storage devices 105 different from the data that the erasure codes protect, so that the failure of any one storage device ordinarily will not result in irrecoverable data loss.”], and
store the first secondary data in a buffer or read the first secondary data from the buffer according to a sub command for the first secondary data among the plural sub commands [par. 0054 – “For example, for any writes, the write data may be stored temporarily in a posted write buffer in the target storage device.”].
transfer, to the plurality of first logical devices, the first user data with a sub command for the user data among the plural sub commands [par. 0046 – Data is sent to one or more storage devices for storage. (“As described in further detail below, in some embodiments, in normal operation, when a write command is executed, the data to be stored are written to one or more storage devices 105, and erasure codes are generated and also written to one or more storage devices 105, with the erasure codes stored, for example, on storage devices 105 different from the data that the erasure codes protect, so that the failure of any one storage device ordinarily will not result in irrecoverable data loss.”)].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of McGlone et al. to include erasure codes, as taught by Olarig et al., in order to improve data integrity by providing redundancy.
However, McGlone et al. and Olarig et al. do not specifically disclose,
the first user data is transferred without storing the first data in the buffer;
In the same field of endeavor, Post et al. disclose,
the first user data is transferred without storing the first data in the buffer [fig. 5; pars. 0080-0093 – “Once the control circuitry receives those additional write commands, the control circuitry can combine the additional write commands with the set of the most recently received commands into a write-multi command. The control circuitry can then direct a bus controller to dispatch the write-multi command from queue 502 to NVM 510. Consequently, the control circuitry can bypass buffer 522 for sequential write commands.”];
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined teachings of McGlone et al. and Olarig et al. to include bypassing a buffer, as taught by Post et al., in order to improve performance by improving efficiency.
Allowable Subject Matter
Claims 11-17 allowed.
Claims 3-8, 10, and 19-20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 2, 9, and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LARRY T MACKALL whose telephone number is (571)270-1172. The examiner can normally be reached Monday - Friday, 9am-5pm.
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LARRY T. MACKALL
Primary Examiner
Art Unit 2131
20 March 2026
/LARRY T MACKALL/Primary Examiner, Art Unit 2139