Prosecution Insights
Last updated: October 22, 2026
Application No. 18/458,331

POWER CONVERTER SYSTEM WITH CASCADED POWER STAGES AND SHARING OF INFORMATION BETWEEN POWER STAGES FOR CONTROL

Non-Final OA §102§103
Filed
Aug 30, 2023
Priority
Jan 11, 2023 — provisional 63/438,401
Examiner
RIVERA-PEREZ, CARLOS O
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Cirrus Logic International Semiconductor Ltd.
OA Round
2 (Non-Final)
72%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
91%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
379 granted / 525 resolved
+4.2% vs TC avg
Strong +19% interview lift
Without
With
+18.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
28 currently pending
Career history
559
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
64.3%
+24.3% vs TC avg
§102
21.4%
-18.6% vs TC avg
§112
7.6%
-32.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 525 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This office action is in response to the filling of the Amendment on 10 June 2026 Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-9, 21, 23-31 and 43 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Low et al. (US 2019/0296630), hereinafter Low. Regarding claim 1, Low discloses (see figures 1-10) a power converter system (figure 5, part 10) comprising a plurality of power converter stages in a cascaded arrangement (figure 5, parts 18 and 20), the power converter stages (figure 5, parts 18 and 20) comprising at least: a first power converter stage (figure 5, part 18); and a second power converter stage (figure 5, part 20) configured to modify an operational state and/or an operational mode (figure 5, part through CTRLratio) (paragraph [0047]; The charge pump 20 is one that can be reconfigured such that the voltage-transformation ratio of the charge pump 20 changes. The charge pump 20 transitions between different voltage-transformation ratios in response to the second control-signal CTRLRATIO. Each such voltage-transformation ratio defines a charge pump mode) of the second power converter stage (figure 5, part 20) responsive to feedforward information (figure 5, part feedforward information at P1 [Vin, Vx]) associated with the first power converter stage (figure 5, part 18) (paragraphs [0068]-[0078]; It does so by permitting the first and second control-signals CTRLMODE, CTRLRATIO to choose an appropriate voltage-transformation ratio for the charge pump 20 and also an appropriate mode for the regulator 18 in such a way as to favor such transient response performance over efficiency or vice versa… In addition, the controller 16 receives a first set of operation signals along a first path P1. The operation signals in the first set can be analog signals indicative of the power converter's operation. In the illustrated embodiment, the first set of operation signals includes the input voltage VIN, the intermediate voltage VX, and the output voltage VOUT… the logic block 22 receives signals from the sensor block 25 and/or the duty-cycle control-block 17 and passes along updated first and second control-signals CTRLMODE, CTRLRRATIO. The sensor block 25 receives the first set of operation signals along the first path P1, a second set of operation signals along a second path P2, and passes a third set of operation signals along a third path P3 to the logic block 22. Whether or not the sensor block 25 uses both first and second sets of operational signals or all the signals within each set depends on the circuits implemented within the sensor block 25). Regarding claim 2, Low discloses everything claimed as applied above (see claim 1). Further, Low discloses (see figures 1-10) the feedforward information (figure 5, part feedforward information at P1 [Vin, Vx]) comprises a change in one or more of an operational state, an operational mode, and a control variable (figure 5, part through CTRLmode) of the first power converter stage (figure 5, part 18) (paragraph [0068]-[0074]; It does so by permitting the first and second control-signals CTRLMODE, CTRLRATIO to choose an appropriate voltage-transformation ratio for the charge pump 20 and also an appropriate mode for the regulator 18 in such a way as to favor such transient response performance over efficiency or vice versa… At each clock pulse, the logic block 22 receives signals from the sensor block 25 and/or the duty-cycle control-block 17 and passes along updated first and second control-signals CTRLMODE, CTRLRRATIO). Regarding claim 3, Low discloses everything claimed as applied above (see claim 2). Further, Low discloses (see figures 1-10) the second power converter stage (figure 5, part 20) is configured to modify its own operational state and/or operational mode (figure 5, part through CTRLratio) substantially contemporaneously with the change in one or more of the operational state, the operational mode, and the control variable (figure 5, part through CTRLmode) of the first power converter stage (figure 5, part 18) (paragraph [0078]; At every occurrence of a clock pulse, the logic block 22 generates the first and second control-signals CTRLMODE, CTRLRATIO. The first and second control-signals CTRLMODE, CTRLRATIO can change at the same time). Regarding claim 4, Low discloses everything claimed as applied above (see claim 1). Further, Low discloses (see figures 1-10) the first power converter stage (figure 5, part 18) is configured to communicate feedforward information (figure 5, part feedforward information at P1 [Vin, Vx]; through 25) regarding the first power converter stage (figure 5, part 18); and the second power converter stage (figure 5, part 20) is configured to modify its own operational state and/or operational mode (figure 5, part through CTRLratio) responsive to receipt of the feedforward information (figure 5, part feedforward information at P1 [Vin, Vx]) (paragraphs [0068]-[0078]; It does so by permitting the first and second control-signals CTRLMODE, CTRLRATIO to choose an appropriate voltage-transformation ratio for the charge pump 20 and also an appropriate mode for the regulator 18 in such a way as to favor such transient response performance over efficiency or vice versa… In addition, the controller 16 receives a first set of operation signals along a first path P1. The operation signals in the first set can be analog signals indicative of the power converter's operation. In the illustrated embodiment, the first set of operation signals includes the input voltage VIN, the intermediate voltage VX, and the output voltage VOUT… the logic block 22 receives signals from the sensor block 25 and/or the duty-cycle control-block 17 and passes along updated first and second control-signals CTRLMODE, CTRLRRATIO. The sensor block 25 receives the first set of operation signals along the first path P1, a second set of operation signals along a second path P2, and passes a third set of operation signals along a third path P3 to the logic block 22. Whether or not the sensor block 25 uses both first and second sets of operational signals or all the signals within each set depends on the circuits implemented within the sensor block 25). Regarding claim 5, Low discloses everything claimed as applied above (see claim 4). Further, Low discloses (see figures 1-10) an information controller (figure 5, part information controller generated by 22 and 25) communicatively coupled to the first power converter stage (figure 5, part 18) and the second power converter stage (figure 5, part 20) and configured to: receive the feedforward information (figure 5, part feedforward information at P1 [Vin, Vx]) from the first power converter stage (figure 5, part 18; through 25); and responsive to the feedforward information (figure 5, part feedforward information at P1 [Vin, Vx]), communicate one or more control signals (figure 5, part CTRLratio) to the second power converter stage (figure 5, part 20) to force the second power converter stage (figure 5, part 20) to modify its operational state and/or operational mode responsive to receipt of the one or more control signals (figure 5, part CTRLratio) (paragraphs [0068]-[0078]; It does so by permitting the first and second control-signals CTRLMODE, CTRLRATIO to choose an appropriate voltage-transformation ratio for the charge pump 20 and also an appropriate mode for the regulator 18 in such a way as to favor such transient response performance over efficiency or vice versa… In addition, the controller 16 receives a first set of operation signals along a first path P1. The operation signals in the first set can be analog signals indicative of the power converter's operation. In the illustrated embodiment, the first set of operation signals includes the input voltage VIN, the intermediate voltage VX, and the output voltage VOUT… the logic block 22 receives signals from the sensor block 25 and/or the duty-cycle control-block 17 and passes along updated first and second control-signals CTRLMODE, CTRLRRATIO. The sensor block 25 receives the first set of operation signals along the first path P1, a second set of operation signals along a second path P2, and passes a third set of operation signals along a third path P3 to the logic block 22. Whether or not the sensor block 25 uses both first and second sets of operational signals or all the signals within each set depends on the circuits implemented within the sensor block 25). Regarding claim 6, Low discloses everything claimed as applied above (see claim 1). Further, Low discloses (see figures 1-10) the first power converter stage (figure 5, part 18) is upstream of the second power converter stage in the cascaded arrangement (figure 5, part 20). Regarding claim 7, Low discloses everything claimed as applied above (see claim 1). Further, Low discloses (see figures 1-10) the second power converter stage (figure 2, part 20) is upstream of the first power converter stage in the cascaded arrangement (figure 2, part 18). Regarding claim 8, Low discloses everything claimed as applied above (see claim 1). Further, Low discloses (see figures 1-10) the first power converter stage (figure 5, part 18) comprises either a capacitive power converter or an inductive power converter (figures 3 and 5, part 18) (paragraphs [0036]-[0039]). Regarding claim 9, Low discloses everything claimed as applied above (see claim 1). Further, Low discloses (see figures 1-10) the second power converter stage (figure 5, part 20) comprises either a capacitive power converter or an inductive power converter (figures 4 and 5, part 20) (paragraphs [0040]-[0047]). Regarding claim 21, Low discloses everything claimed as applied above (see claim 1). Further, Low discloses (see figures 1-10) the first power converter stage (figure 5, part 18) is an inductive converter (figures 3 and 5, part 18) (paragraphs [0036]-[0039]); the second power converter stage (figure 5, part 20) is a charge pump (figures 4 and 5, part 20); and the modification (figures 4 and 5, part through CTRLratio) comprises a modification of a charge pump ratio (figure 5, part CTRLratio) of the charge pump (figures 4 and 5, part 20) (paragraphs [0040]-[0047]; The charge pump 20 is one that can be reconfigured such that the voltage-transformation ratio of the charge pump 20 changes. The charge pump 20 transitions between different voltage-transformation ratios in response to the second control-signal CTRLRATIO. Each such voltage-transformation ratio defines a charge pump mode). Regarding claim 23, claim 1 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons. Regarding claim 24, claim 2 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons. Regarding claim 25, claim 3 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons. Regarding claim 26, claim 4 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons. Regarding claim 27, claim 5 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons. Regarding claim 28, claim 6 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons. Regarding claim 29, claim 7 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons. Regarding claim 30, claim 8 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons. Regarding claim 31, claim 9 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons. Regarding claim 43, claim 21 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 11, 12, 33 and 34 are rejected under 35 U.S.C. 103 as being unpatentable over Low et al. (US 2019/0296630), hereinafter Low, in view of Chen et al. (US 2020/0105185), hereinafter Chen. Regarding claim 11, Low discloses everything claimed as applied above (see claim 1). Further, Low discloses (see figures 1-10) the first power converter stage (figure 5, part 18) is an inductive converter (figures 3 and 5, part 18) in combination with a gain element (figure 3, part gain element at 40) (paragraphs [0036]-[0039]); the second power converter stage (figure 5, part 20) is a charge pump (figures 4 and 5, part 20) (paragraphs [0040]-[0047]); the feedforward information is indicative of a change (figure 5, part feedforward information at P1 [Vin, Vx]); and the second power converter stage (figure 5, part 20) modifies its charge pump ratio (figure 5, part CTRLratio) in response to a change (figure 5, part feedforward information at P1 [Vin, Vx]). However, Low does not expressly disclose the feedforward information is indicative of a change of available headroom of the gain element. Chen teaches (see figures 1-11) the feedforward information (figure 5, part feedforward information 124) is indicative of a change of available headroom of the gain element (figure 5, part gain element generated by 122) (paragraph [0111]; provided with feedforward control logic such as headroom feedforward control circuit 122 (see, e.g., FIG. 6C), which is configured to adjust Vout… The value Vout_adj computed by equation (2) refers to the predictive amount by which converter 70 should increase or decrease Vout. If desired, a different gain value G may be applied from step up versus step down cases (e.g., a first gain value may be used for brightness increases, whereas a second gain value that is different than the first gain value may be used for brightness reductions)). It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the controller of Low with the headroom features as taught by Chen and obtain the first power converter stage is an inductive converter in combination with a gain element; the second power converter stage is a charge pump; the feedforward information is indicative of a change of available headroom of the gain element; and the second power converter stage modifies its charge pump ratio in response to a change in the available headroom, because it provides more efficient and accurate control while minimizing DC/DC voltage variation and thus suppressing acoustic noise (paragraph [0115]). Regarding claim 12, Low and Chen teach everything claimed as applied above (see claim 11). Further, Low discloses (see figures 1-10) a gain of the gain element is changed (figure 3, part gain element at 40) to compensate for modification of the charge pump ratio (figure 5, part CTRLratio) (paragraph [0068]-[0074]; It does so by permitting the first and second control-signals CTRLMODE, CTRLRATIO to choose an appropriate voltage-transformation ratio for the charge pump 20 and also an appropriate mode for the regulator 18 in such a way as to favor such transient response performance over efficiency or vice versa… At each clock pulse, the logic block 22 receives signals from the sensor block 25 and/or the duty-cycle control-block 17 and passes along updated first and second control-signals CTRLMODE, CTRLRRATIO). Regarding claim 33, claim 11 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons. Regarding claim 34, claim 12 has the same limitations, except that is not a method claim, based on this is rejected for the same reasons. Response to Arguments Applicant's arguments filed 06/10/2026 have been fully considered but they are not persuasive. Applicant’s argues on pages 12-13 of the Applicant's Response (“Applicant respectfully maintains that the restriction requirement is improper and continues to traverse the restriction for at least the following reasons”). The Examiner respectfully disagrees with Applicant’s arguments, because (as previously discussed) it would be a serious burden for searching the non-elected species as their variable feedforward parameters (headroom voltage, error, input/output power, power limit, bandwidth etc.) that result in different control schemes (charge pump ratio control, frequency control, number of phases, FET segmentation, bandwidth control etc.) require different search queries/strategies. In order to support this statement, distinction between these species will be presented: Species 1 (figure 2) requires a gain normalization block 201 and an inductive converter 202 (as first power converter stage) and a charge pump 204 (as second power converter stage) in combination with a ratio controller 206. These elements are only presented in species 1, and not found in the species 2 through 5, thus these elements evidence that the species do not overlap in scope, and that the species are mutually exclusive. A serious search burden was provided by the description of the species. Species 1 would require search queries for a normalization block and a ratio controller for a charge pump, which would not be required of species 2 through 5; Species 2 (figure 3) requires an inductive converter which detects an error with a closed loop summing circuit and a charge pump with control switching frequency based on the error. These elements are only presented in species 2, and not found in the species 1 and 3 through 5, thus these elements evidence that the species do not overlap in scope, and that the species are mutually exclusive. Species 2 would require search queries for an error being detected in a closed loop and providing frequency switching control in response to the error, which would not be required in species 1, and 3 through 5. Species 3 (figure 4) requires an efficiency controller that receives input or out power from an inductive controller and controls parameters including the number of active phases, frequency of operation, FET segmentation of the switches, and charge pump ratio. These elements are only presented in species 3, and not found in the species 1, 2, 4, and 5, thus these elements evidence that the species do not overlap in scope, and that the species are mutually exclusive. Species 3 requires search queries for an efficiency controller receiving input or output power levels, and controlling an inductive converter and charge pump with parameters of the number of active phases, frequency of operation, FET segmentation of the switches, and charge pump ratio, in the species 1, 2, 4, and 5. Species 4 (figure 7) requires an inductive converter 702 (as first power converter stage) and an inductive converter [audio amplifier] 704 (as second power converter stage) with power limits to prevent over-current or under-current and maintain a power balance between the converters, as well as headroom control. These elements are only presented in species 4, and not found in the species 1 through 3, and 5, thus these elements evidence that the species do not overlap in scope, and that the species are mutually exclusive. Species 4 requires search queries for power limit setting, headroom control, over-current, and over temperature, which are not required in the species 1 through 3 and 5. Species 5 (figure 9) requires an inductive converter 902 (as first power converter stage) and an inductive converter 904 (as second power converter stage) each with variable band width control based on error magnitude based on error magnitude. These elements are only presented in species 5, and not found in the species 1 through 4, thus these elements evidence that the species do not overlap in scope, and that the species are mutually exclusive. Species 5 requires search queries for inductive converters with variable bandwidth control based on error magnitude, which is not required for species 1 through 4. Additional, examples about the different classification are: H02M3/07 (for charge pump); H02M5/451 (control of frequency); H02M1/084 (multiphase systems); H03F2200/03 (audio amplifier); H02H3/08 (power limit as over-current); and H03G1/02 (bandwidth control). Therefore, the requirement is still deemed proper. Applicant’s argues on pages 13-17 of the Applicant's Response (“Applicant submits that Low fails to teach, either expressly or inherently, "a second power converter stage configured to modify an operational state and/or an operational mode of the second power converter stage responsive to feedforward information associated with the first power converter stage," as recited in Claim 1 and as similarly recited in Claim 23”). The Examiner respectfully disagrees with Applicant’s arguments, because Low discloses a second power converter stage (figure 5, part 20) configured to modify an operational state and/or an operational mode (figure 5, part through CTRLratio) (paragraph [0047]; The charge pump 20 is one that can be reconfigured such that the voltage-transformation ratio of the charge pump 20 changes. The charge pump 20 transitions between different voltage-transformation ratios in response to the second control-signal CTRLRATIO. Each such voltage-transformation ratio defines a charge pump mode) of the second power converter stage (figure 5, part 20) responsive to feedforward information (figure 5, part feedforward information at P1 [Vin, Vx]) associated with the first power converter stage (figure 5, part 18) (paragraphs [0068]-[0078]; It does so by permitting the first and second control-signals CTRLMODE, CTRLRATIO to choose an appropriate voltage-transformation ratio for the charge pump 20 and also an appropriate mode for the regulator 18 in such a way as to favor such transient response performance over efficiency or vice versa… In addition, the controller 16 receives a first set of operation signals along a first path P1. The operation signals in the first set can be analog signals indicative of the power converter's operation. In the illustrated embodiment, the first set of operation signals includes the input voltage VIN, the intermediate voltage VX, and the output voltage VOUT… the logic block 22 receives signals from the sensor block 25 and/or the duty-cycle control-block 17 and passes along updated first and second control-signals CTRLMODE, CTRLRRATIO. The sensor block 25 receives the first set of operation signals along the first path P1, a second set of operation signals along a second path P2, and passes a third set of operation signals along a third path P3 to the logic block 22. Whether or not the sensor block 25 uses both first and second sets of operational signals or all the signals within each set depends on the circuits implemented within the sensor block 25). As discusses above, Low’s reference disclose the second power converter stage (figure 5, part 20) configured to modify an operational state and/or an operational mode through CTRLratio that transitions between different voltage-transformation ratios (figure 5, part through CTRLratio) responsive to the feedforward information (figure 5, part feedforward information at P1 [Vin, Vx]) associated with the first power converter stage (figure 5, part 18). The feed information (figure 5, part feedforward information at P1 [Vin, Vx]) is associated with the first power converter stage (figure 5, part 18) because are the input and output voltages of this stage. Furthermore, in response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., the specification states: "As used herein, 'feedforward information' communicated from a converter stage may include any information associated with the converter stage other than the intermediate variable(s) (e.g., current or voltage) and output variable(s) (e.g., current or voltage) generated by such converter stage (e.g., information external to a signal path from control variable(s) to intermediate variable(s) of the cascaded converter stages) and other than any other information readily available to the other converter in the absence of feedforward information") are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Therefore, based on the broadest reasonable interpretation, Low meets with the claimed limitation. Additional, it should be noted that broad claim language as recited does not defines specific feedforward information used in the control. The examiner suggests the applicant to positively recite in the claim language the specific feedforward information used in the control. Applicant’s argues on page 17 of the Applicant's Response (“Claim 2 recites that "the feedforward information comprises a change in one or more of an operational state, an operational mode, and a control variable of the first power converter stage," and Claim 24 similarly recites this limitation. This further underscores the distinction from Low, because the signals VIN, Vx, Vout on P1 in Low are not "a change in one or more of an operational state, an operational mode, and a control variable of the first power converter stage."… Thus, Claims 2, 3, 24, and 25 are allowable on their own merits in addition to being allowable by virtue of their dependence from allowable independent claims”). The Examiner respectfully disagrees with Applicant’s arguments, because Low discloses the feedforward information (figure 5, part feedforward information at P1 [Vin, Vx]) comprises a change in one or more of an operational state, an operational mode, and a control variable (figure 5, part through CTRLmode) of the first power converter stage (figure 5, part 18) (paragraph [0068]-[0074]; It does so by permitting the first and second control-signals CTRLMODE, CTRLRATIO to choose an appropriate voltage-transformation ratio for the charge pump 20 and also an appropriate mode for the regulator 18 in such a way as to favor such transient response performance over efficiency or vice versa… At each clock pulse, the logic block 22 receives signals from the sensor block 25 and/or the duty-cycle control-block 17 and passes along updated first and second control-signals CTRLMODE, CTRLRRATIO). Therefore, Low meets with the claimed limitation. Applicant’s argues on pages 17-18 of the Applicant's Response (“Claim 4 recites that "the first power converter stage is configured to communicate feedforward information regarding the first power converter stage" and that "the second power converter stage is configured to modify its own operational state and/or operational mode responsive to receipt of the feedforward information," and Claim 26 similarly recites these limitations. Low does not teach the regulator 18 communicating feedforward information regarding itself to the charge pump 20. Thus, Claims 4, 5, 26, and 27 are allowable on their own merits in addition to being allowable by virtue of their dependence from allowable independent claims”). The Examiner respectfully disagrees with Applicant’s arguments, because Low discloses the first power converter stage (figure 5, part 18) is configured to communicate feedforward information (figure 5, part feedforward information at P1 [Vin, Vx]; through 25) regarding the first power converter stage (figure 5, part 18); and the second power converter stage (figure 5, part 20) is configured to modify its own operational state and/or operational mode (figure 5, part through CTRLratio) responsive to receipt of the feedforward information (figure 5, part feedforward information at P1 [Vin, Vx]) (paragraphs [0068]-[0078]; It does so by permitting the first and second control-signals CTRLMODE, CTRLRATIO to choose an appropriate voltage-transformation ratio for the charge pump 20 and also an appropriate mode for the regulator 18 in such a way as to favor such transient response performance over efficiency or vice versa… In addition, the controller 16 receives a first set of operation signals along a first path P1. The operation signals in the first set can be analog signals indicative of the power converter's operation. In the illustrated embodiment, the first set of operation signals includes the input voltage VIN, the intermediate voltage VX, and the output voltage VOUT… the logic block 22 receives signals from the sensor block 25 and/or the duty-cycle control-block 17 and passes along updated first and second control-signals CTRLMODE, CTRLRRATIO. The sensor block 25 receives the first set of operation signals along the first path P1, a second set of operation signals along a second path P2, and passes a third set of operation signals along a third path P3 to the logic block 22. Whether or not the sensor block 25 uses both first and second sets of operational signals or all the signals within each set depends on the circuits implemented within the sensor block 25). Therefore, Low meets with the claimed limitation. Applicant’s argues on pages 18-19 of the Applicant's Response (“Moreover, even apart from the deficiencies of Low identified above, Chen does not cure Low's failure to teach "feedforward information associated with the first power converter stage”). The Examiner respectfully disagrees with Applicant’s arguments, because the rejection is a 103 combination between Low and Chen. The primary reference Low discloses (as discussed above) the first power converter stage (figure 5, part 18) is an inductive converter (figures 3 and 5, part 18) in combination with a gain element (figure 3, part gain element at 40) (paragraphs [0036]-[0039]); the second power converter stage (figure 5, part 20) is a charge pump (figures 4 and 5, part 20) (paragraphs [0040]-[0047]); the feedforward information is indicative of a change (figure 5, part feedforward information at P1 [Vin, Vx]); and the second power converter stage (figure 5, part 20) modifies its charge pump ratio (figure 5, part CTRLratio) in response to a change (figure 5, part feedforward information at P1 [Vin, Vx]). Chen teaches the feedforward information (figure 5, part feedforward information 124) is indicative of a change of available headroom of the gain element (figure 5, part gain element generated by 122) (paragraph [0111]; provided with feedforward control logic such as headroom feedforward control circuit 122 (see, e.g., FIG. 6C), which is configured to adjust Vout… The value Vout_adj computed by equation (2) refers to the predictive amount by which converter 70 should increase or decrease Vout. If desired, a different gain value G may be applied from step up versus step down cases (e.g., a first gain value may be used for brightness increases, whereas a second gain value that is different than the first gain value may be used for brightness reductions)). It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the controller of Low with the headroom features as taught by Chen and obtain the first power converter stage is an inductive converter in combination with a gain element; the second power converter stage is a charge pump; the feedforward information is indicative of a change of available headroom of the gain element; and the second power converter stage modifies its charge pump ratio in response to a change in the available headroom, because it provides more efficient and accurate control while minimizing DC/DC voltage variation and thus suppressing acoustic noise (paragraph [0115]). Therefore, the combination of power converter stages (figure 5, parts 18 and 20) of Low with the headroom features as taught by Chen result in the claimed limitation. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.O.R. / Examiner, Art Unit 2838 /THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
Read full office action

Prosecution Timeline

Aug 30, 2023
Application Filed
Apr 01, 2026
Non-Final Rejection mailed — §102, §103
Jun 10, 2026
Response Filed
Aug 28, 2026
Final Rejection mailed — §102, §103
Sep 28, 2026
Response after Non-Final Action

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12754575
VOLTAGE CONTROL DEVICE AND METHOD CONSIDERING LINE POWER LOSS IN VOLTAGE DROP USING CVR FACTOR
3y 1m to grant Granted Oct 06, 2026
Patent 12749964
SYSTEMS AND METHODS FOR DRIVING BIPOLAR TRANSISTORS RELATED TO POWER CONVERTERS
3y 4m to grant Granted Sep 29, 2026
Patent 12738854
SEMICONDUCTOR OSCILLATION SUPPRESSION CIRCUIT
4y 10m to grant Granted Sep 15, 2026
Patent 12738836
LOW LOSS SNUBBER CIRCUIT
3y 3m to grant Granted Sep 15, 2026
Patent 12719378
DUAL ACTIVE BRIDGE OPTIMIZATION WITH TRIPLE PHASE SHIFT AND VARIABLE INDUCTOR
3y 0m to grant Granted Aug 25, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

2-3
Expected OA Rounds
72%
Grant Probability
91%
With Interview (+18.8%)
2y 8m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 525 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month