Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the claim listing filed on May 20th, 2026. Claims 1-20 are currently pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected 35 U.S.C. 103 as being unpatentable over RENNIG et al. (US Pat No. 11853252 B2, hereinafter referred to as Rennig) in view of Bender et al. (USPGPUB No. 2005/0091383 A1, hereinafter referred to as Bender) and further in view of Huynh (USPGPUB No. 2008/0082409 A1) and further in view of Hornung (USPGPUB No. 2023/0058355 A1, hereinafter referred to as Hornung).
Referring to claim 1, Rennig discloses a processing device {processing device “processing system 10a, see Fig. 4, Col 8, lines 62-67}, comprising: an event manager {event manager(s) “one or more DMA controller 110”, see Fig. 1, Col 8, lines 62-67} coupled between a first circuit {first circuit “communication interface 50 comprises…”, see Fig. 4, Col 9, lines 10-13} and a second circuit {“send read or write requests, respectively, either to [other circuits] the communication system 114 or directly the memory controller 110”, see Figs. 4 and 5, Col 9, lines 23-25}, the event manager comprising: an event channel {event channel “slave interface 1104 for … configuring the channels of the DMA controller 110”, see Fig. 4, Col 10, lines 34-36; the first circuit configured to:
assert a request signal {“DM interface circuit 506 may assert the request signal REQ”, see Fig. 5, Col 9, lines 39-40} via the event channel based on detecting an event {“[detecting an event] set a flag enabling the data transmission and/or a flag enabling DMA transfer”, see Fig. 5, Col 9, lines 35-37}, and in response to detecting an assertion of an acknowledge signal {“in response to the acknowledge signal ACK11”, see Fig. 5, Col 9, lines 57-58}, de-assert the request signal {“may de-assert the request signal REQ1”, see Fig. 5, Col 9, lines 57-58};
Rennig does not appear to explicitly disclose wherein the second circuit configured to:
in response to detecting the assertion of the request signal, assert the control signal via the event channel, and in response to detecting the de-assertion of the request signal, de-assert the control signal.
However, Bender discloses wherein the second circuit configured to:
in response to detecting the assertion of the request signal (“identifies all the channels with active requests” [0144], 2nd sentence), assert the control signal via the event channel {“condition code field or the channel's channel status field and whether an indication is sent to the service processor”, see Table 29. [0376] last two lines of page 36}, and in response to detecting the de-assertion of the request signal {“source of pull descriptor with an active remote start [request signal] flag encountered after the initial source of pull descriptor is considered to be the same as an end of list condition [de-asserts as claimed]”, [0295] last sentence}, de-assert the control signal {“retry entry is cleared [and respective done signal de-asserts so that] the next oldest, entry appears”, [0578]}.
Rennig and Bender are analogous because they are from the same field of endeavor, managing DMA transfer(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Rennig and Bender before him or her, to modify Rennig’s respective circuit(s) incorporating Bender’s “Transport Macro logic 205” ([0540], see Fig. 38).
The suggestion/motivation for doing so would have been to implement communication adapters with mechanisms for time of day synchronization and with related mechanisms that establish backup and master/slave relationships amongst a plurality of adapters that permit designated backup adapter units to take over the communications operations of a failed adapter unit (Bender [0001] last sentence).
Therefore, it would have been obvious to combine Bender with Rennig to obtain the invention as specified in the instant claim(s).
However, neither Rennig or Bender appears to explicitly disclose wherein the control signal is asserting an acknowledge signal in response to detecting the assertion of the request signal.
Furthermore, Huynh discloses wherein the control signal is asserting an acknowledge signal (“port agent transmits an ACK until…”, see Fig. 1 [0023]} in response to detecting the assertion of the request signal (“receives an indication that the request corresponding to the job to be completed is committed, and completed or failed.”, see Fig. 1, [0023]}.
Rennig/Bender and Huynh are analogous because they are from the same field of endeavor, managing DMA transfer(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Rennig/Bender and Huynh before him or her, to modify Rennig/Bender’s system incorporating Huynh’s “web client engine 22” (see Fig. 1, [0029]) for the corresponding request signal/ACK signal as appropriate.
The suggestion/motivation for doing so would have been to implement storing mechanisms utilizing the request is for job recovery in case the server shuts operation. It can recover the pending requests from the jobstore for better security or reliability (Huynh [0007]).
Therefore, it would have been obvious to combine Huynh with Rennig/Bender to obtain the invention as specified in the instant claim(s).
However, neither one of the group consisting of Bender, Renning and Huynh appears to explicitly disclose wherein the event manager comprising an event channel configured to provide a point-to-point connection between the first circuit and the second circuit.
Furthermore, Hornung discloses wherein the event manager comprising an event channel {“example tile 504 can include a passthrough channel”, see Fig. 5, [0108], 1st sentence} configured to provide a point-to-point connection {“supports virtual channels to enable a flexible and high-speed interaction between chiplets”, see Fig. 1, [0126], 1st sentence} between the first circuit and the second circuit {“By enabling a physical channel to virtual channel mapping and encapsulating time-based signaling with a packetized protocol, CPI bridges intra-chiplet networks across the chiplet network 622 [between first and second circuits].”, see Fig. 6a, [0126], last sentence}.
Rennig/Bender/Huynh and Hornung are analogous because they are from the same field of endeavor, managing DMA transfer(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Rennig/Bender/Huynh and Hornung before him or her, to modify Rennig/Bender/Huynh’s system incorporating Hornung’s “example tile 504”, respective “passthrough channel” and “CPI interface” (see Fig. 1, [0126], 1st sentence).
The suggestion/motivation for doing so would have been to implement new computing architectures and devices to advance computing performance beyond the practice of transistor scaling while considering moving data between processors (Hornung [0001], last sentence).
Therefore, it would have been obvious to combine Hornung with Rennig/Bende/Huynh to obtain the invention as specified in the instant claim(s).
As per claim 2, the rejection of claim 1 is incorporated and Bender discloses wherein: the event channel comprises a plurality of conductors {“using some [conductors] sideband capability or may use previously established message passing parameters”, [0427]}, and each conductor of the plurality of conductors {“consists of a single data interface with a sideband control interface to indicate [among plurality of logical conductors] the virtual lane[s] over which the data is transmitted”, see Fig. 40 [0535] last two sentences} is used to transmit a specific type of signal {“the type of [signals] transfer”, [0427] 1st sentence} between the first circuit and the second circuit {“sending and receiving software” ([0427]) of respective first and second circuits “communication adaptors 100a and 100b”, see Fig. 3 [0074]};
Hornung discloses the event channel comprises a plurality of conductors {“a host interface (e.g., corresponding to the host interface 724 from the example of FIG. 7) that is responsible for workload balancing across the tiled chiplet”, see Figs. 7 and 8 [0150]}, wherein a first conductor of the plurality of conductors is configured {plurality of conductors “new computing architectures and devices are desired to advance computing performance beyond the practice of transistor scaling”, see Fig. 11 [0181]} to transmit the request signal {“host-based command request queues [and request signals]”, see Figs. 7 and 8, [0150, 2nd sentence} and a second conductor {“be communicatively coupled to the second CNM cluster 804 via an inter-chiplet CPI interface 818,”, see Fig. 8 [0149]} of the plurality of conductors is configured to transmit the acknowledge signal {“and response queues” and respective acknowledge signal (see Fig. 8 [0150]) such as “an initialize a mask field for data used a synchronous flow” ([0155], 2nd sentence)}.
As per claim 3, the rejection of claim 1 is incorporated and Bender discloses wherein the second circuit is further configured to begin processing the event {“Each descriptor identifies the channel and adapter intended to receive the data [when said descriptor is processed].”, see Fig. 17 [0428], 2nd sentence}.
As per claim 4, the rejection of claim 3 is incorporated and Bender discloses wherein: the second circuit is further configured to: in response to completion of the processing of the event {“completion code table field bits”, see Table after [0267]}, assert a completion signal via the event channel {“The local descriptor completion code field, CC, is updated with the final status of the operation. See Table 16 above”, [0268] last sentence}, and in response to detecting an assertion of a done acknowledge signal {“expected, then an acknowledgment packet is sent back to the sender”, see Fig. 38 [0539] last two sentences}, de-assert the completion signal {“The local descriptor completion code field, CC, is updated with the final status of the operation. See Table 16 above.”, see Fig. 17 [0268], last sentence};
and the first circuit is further configured to:
in response to detecting the assertion of the completion signal {“condition code field or the channel's channel status field and whether an indication is sent to the service processor”, see Table 29. [0376] last two lines of page 36}, assert the done acknowledge signal via the event channel {“When the associated response returns, the entry within the Request buffer contains the [claimed DONE ACK signal] bus tag for the response when it is put on to the processor bus”, see Fig. 17 [0539]}, and in response to detecting the de-assertion of the completion signal {“In the case where the resend is eventually successful [and respective completion signal de-asserted”, [0578] 1st sentence}, de-assert the done acknowledge signal {“retry entry is cleared [and respective done signal de-asserts so that] the next oldest, entry appears”, [0578]}.
As per claim 5, the rejection claim 1 is incorporated and Bender discloses wherein: the first circuit is further configured to:
transmit a count of a number of DMA transactions associated {“Descriptor Sequence Number is a monotonically increasing counter that increments whenever a new descriptor is used”, see Fig. 17 [0598], 6th sentence} with the request signal via the event channel {“Packet to the other side in order to initiate the transfer.”, see Fig. 17 [0597]; said first packet associated with a request via event channel “identifies all the channels with active requests” ([0144], 2nd sentence)};
and the second circuit is further configured to: in response to detecting the assertion of the request signal and the count {“back on the [other circuit] target side… a Pull Sequence Number that matches the [claimed request signal and count] one expected,”, see Fig. 17 [0599], 1st sentence}, begin processing the number of DMA transactions indicated by the count {“Once a packet is received for this channel that meets these conditions, the Descriptor Sequence Number of that packet is saved and the data transfer is assumed to have begun [processing the DMA as claimed]”, see Fig. 17 [0599] 3rd sentence}.
As per claim 6, the rejection claim 5 is incorporated and Bender discloses wherein: the second circuit is further configured to:
in response to completion of the processing of the number of the DMA transactions {“Descriptor Sequence Number is a monotonically increasing counter that increments whenever a new descriptor is used”, see Fig. 17 [0598], 6th sentence}, assert a completion signal via the event channel {“push response packet back to the send side indicating that the operation was (or perhaps was not) successful [completion]”, [0461]}, and in response to detecting an assertion of a done acknowledge signal {“when the receive side detects the [bus tag] echo packet”, [0463]}, de-assert the completion signal {“it removes [de-asserts the completion signal] the push response packet”, [0463]};
and the first circuit is further configured to: in response to detecting the assertion of the completion signal {“condition code field or the channel's channel status field and whether an indication is sent to the service processor”, see Table 29. [0376] last two lines of page 36}, assert the done acknowledge signal via the event channel {“When the associated response returns, the entry within the Request buffer contains the [claimed DONE ACK signal] bus tag for the response when it is put on to the processor bus”, see Fig. 17 [0539]}, and in response to detecting the de-assertion of the completion signal {“In the case where the resend is eventually successful [and respective completion signal de-asserted”, [0578] 1st sentence}, de-assert the done acknowledge signal {“retry entry is cleared [and respective done signal de-asserts so that] the next oldest, entry appears”, [0578]}.
As per claim 7, the rejection of claim 6 is incorporated and Bender discloses wherein: the second circuit is further configured to:
in response to completion of the processing of the number of the DMA transactions {“Descriptor Sequence Number is a monotonically increasing counter that increments whenever a new descriptor is used”, see Fig. 17 [0598], 6th sentence}, assert a done status signal via the event channel {“When the associated response returns, the entry within the Request buffer contains the [claimed DONE ACK signal] bus tag for the response when it is put on to the processor bus”, see Fig. 17 [0539]}, and in response to de-asserting the completion signal {“In the case where the resend is eventually successful [and respective completion signal de-asserted”, [0578] 1st sentence}, de-assert the done status signal {“retry entry is cleared [and respective done signal de-asserts so that] the next oldest, entry appears”, [0578]}.
As per claim 8, the rejection of claim 1 is incorporated and Bender discloses the first circuit further configured to:
detect an event prior to detecting {“using some [conductors] sideband capability or may use previously established message passing parameters”, [0427]} the assertion of the acknowledge signal via the event channel {“When the associated response returns, the entry within the Request buffer contains the [claimed DONE ACK signal] bus tag for the response when it is put on to the processor bus”, see Fig. 17 [0539]}, wherein the first circuit is configured to generate a second request signal based on detecting the event {“Packet to the other side in order to initiate the transfer.”, see Fig. 17 [0597]; said first packet associated with a request via event channel “identifies all the channels with active requests” ([0144], 2nd sentence)};
store information for generating the second request signal {first circuit “sending side… [it gather all of the information it needs into working registers” for the respective request signal, [0455]} in a queue {“working registers”, [0455] but also queue “maintenance of the work queue linked list and the interrupt queue linked list;” ([0235])};
and in response to detecting the assertion of the acknowledge signal via the event channel {“When the associated response returns, the entry within the Request buffer contains the [claimed DONE ACK signal] bus tag for the response when it is put on to the processor bus”, see Fig. 17 [0539]} and de-asserting the request signal via the event channel {“back on the [other circuit] target side… a Pull Sequence Number that matches the [claimed request signal and count] one expected,”, see Fig. 17 [0599], 1st sentence}, assert the second request signal via the event channel {“Packet to the other side in order to initiate the transfer.”, see Fig. 17 [0597]; said first packet associated with a request via event channel “identifies all the channels with active requests” ([0144], 2nd sentence).
As per claim 9, the rejection claim 1 is incorporated and Bender discloses further comprising a wakeup circuit coupled to the second circuit and configured to {wakeup circuit “finite state machine” that “describes the various states defined for a channel [to an associated circuit]”, see Fig. 16, Table 6 after [0204]}:
in response to detecting the assertion of the request signal via the event channel {detecting request signal “a request via event channel “identifies all the channels with active requests” ([0144], 2nd sentence” on event channel “using some [event channel conductors] sideband capability or may use previously established message passing parameters” ([0427])}, enable the second circuit from a sleep state to an enabled state {“resetting” state, see Table 6, transitions from a sleep state “stopped” to enabled state “invalid”, see Table 6 and Fig. 16} that allows the second circuit to detect the assertion of the request signal {“It also [detects and] discards any incoming [request] packet” in the “invalid state”, see Table 6}.
As per claim 10, the rejection of claim 1 is incorporated and Bender discloses wherein: the event manager selectably couples the first circuit to the second circuit and a third circuit {“adapter chip 200” in a network fabric to a third circuit “two message passing adapters 200D and 200Z” but as seen in Figure 6 includes a plurality of adapters, [0082], 7th sentence}; the third circuit is configured to:
in response to detecting the assertion of the request signal (“identifies all the channels with active requests” [0144], 2nd sentence} via the event channel {“using some [event channel conductors] sideband capability or may use previously established message passing parameters” ([0427]), assert, via the event channel, a second acknowledge signal to the first circuit {“condition code field or the channel's channel status field and whether an indication is sent to the service processor”, see Table 29. [0376] last two lines of page 36;
and the first circuit de-asserting the request signal {“source of pull descriptor with an active remote start [request signal] flag encountered after the initial source of pull descriptor is considered to be the same as an end of list condition [de-asserts as claimed]”, [0295] last sentence} is further in response to detecting both the acknowledge signal {“When the associated response returns, the entry within the Request buffer contains the [claimed DONE ACK signal] bus tag for the response when it is put on to the processor bus”, see Fig. 17 [0539]} and the second acknowledge signal {“when the [first circuit] receive side detects the [bus tag] echo packet”, [0463]}.
As per claim 11, the rejection claim 1 is incorporated and Bender discloses wherein the event manager is configured to:
dynamically assign each of a plurality of event channels {“target of pull descriptor [dynamically assigns] identifies the remote adapter and channel number that provides the data” per respective event channel, [0298]} between one of a plurality of publishing circuits {publishing circuits within each adapter executing “Sending and receiving software identify each other's [assigned] channel and logical ID values”, [0427]} and an associated subscribing circuit of a plurality of subscribing circuits {establishing circuitry executing “Receiving side software defines one or more target of push descriptors”, [0429]}, wherein the event channel is a first event channel of the plurality of event channels {“using some sideband capability or may use previously established message passing parameters” the sideband consisting a plurality of channels, [0427]}, the first circuit is a first publishing circuit of the plurality of publishing circuits {first publishing circuit executing “Sending side software defines one or more source of push descriptors”, [0428]}, and the second circuit is a first subscribing circuit of the plurality of subscribing circuits {“[subscribing circuit to] verify that the software task is authorized to issue the command and directs the command”, [0431], 1st sentence}.
Referring to claim 12, Rennig discloses a method comprising {a method performed by “processing system 10a, see Fig. 4, Col 8, lines 62-67}:
asserting, by a first circuit over an event channel between the first circuit and a second circuit, a request signal {“DM interface circuit 506 may assert the request signal REQ”, see Fig. 5, Col 9, lines 39-40};
in response to detecting the assertion of the request signal {in response as claimed “whereby the DMA channel DMA.sub.1 transfers a given number k of data packets TD1 . . . TDk”, see Fig. 5, Col 9, lines 40-42}, asserting, by the second circuit over the event channel, an acknowledge signal {“may also assert an acknowledge signal ACK.sub.1 indicating that the requested number k of packets TD1 . . . TDk has been transferred” associated with the first request signal, see Fig. 5, Col 9, lines 53-55};
in response to detecting the assertion of the acknowledge signal {“in response to the acknowledge signal ACK1”, see Fig. 5, Col 9, lines 56-58}, de-asserting, by the first circuit, the request signal {“may de-assert the request signal REQ1”, see Fig. 5, Col 9, lines 56-58}};
Rennig does not appear to explicitly disclose wherein the second circuit configured to:
in response to detecting the assertion of the request signal, assert the control signal via the event channel, and in response to detecting the de-assertion of the request signal, de-assert the control signal.
However, Bender discloses wherein the second circuit configured to:
in response to detecting the assertion of the request signal (“identifies all the channels with active requests” [0144], 2nd sentence), assert the control signal via the event channel {“condition code field or the channel's channel status field and whether an indication is sent to the service processor”, see Table 29. [0376] last two lines of page 36}, and in response to detecting the de-assertion of the request signal {“source of pull descriptor with an active remote start [request signal] flag encountered after the initial source of pull descriptor is considered to be the same as an end of list condition [de-asserts as claimed]”, [0295] last sentence}, de-assert the control signal {“retry entry is cleared [and respective done signal de-asserts so that] the next oldest, entry appears”, [0578]}.
Rennig and Bender are analogous because they are from the same field of endeavor, managing DMA transfer(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Rennig and Bender before him or her, to modify Rennig’s respective circuit(s) incorporating Bender’s “Transport Macro logic 205” ([0540], see Fig. 38).
The suggestion/motivation for doing so would have been to implement communication adapters with mechanisms for time of day synchronization and with related mechanisms that establish backup and master/slave relationships amongst a plurality of adapters that permit designated backup adapter units to take over the communications operations of a failed adapter unit (Bender [0001] last sentence).
Therefore, it would have been obvious to combine Bender with Rennig to obtain the invention as specified in the instant claim(s).
However, neither Rennig or Bender appears to explicitly disclose wherein the control signal is asserting an acknowledge signal in response to detecting the assertion of the request signal.
Furthermore, Huynh discloses wherein the control signal is asserting an acknowledge signal (“port agent transmits an ACK until…”, see Fig. 1 [0023]} in response to detecting the assertion of the request signal (“receives an indication that the request corresponding to the job to be completed is committed, and completed or failed.”, see Fig. 1, [0023]}.
Rennig/Bender and Huynh are analogous because they are from the same field of endeavor, managing DMA transfer(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Rennig/Bender and Huynh before him or her, to modify Rennig/Bender’s system incorporating Huynh’s “web client engine 22” (see Fig. 1, [0029]) for the corresponding request signal/ACK signal as appropriate.
The suggestion/motivation for doing so would have been to implement storing mechanisms utilizing the request is for job recovery in case the server shuts operation. It can recover the pending requests from the jobstore for better security or reliability (Huynh [0007]).
Therefore, it would have been obvious to combine Huynh with Rennig/Bender to obtain the invention as specified in the instant claim(s).
However, neither one of the group consisting of Bender, Renning and Huynh appears to explicitly disclose wherein the event manager comprising an event channel that is configured to provide a point-to-point connection between the first circuit and the second circuit, a request signal.
Furthermore, Hornung discloses wherein the event manager comprising an event channel {“example tile 504 can include a passthrough channel”, see Fig. 5, [0108], 1st sentence} that is configured to provide a point-to-point connection {“supports virtual channels to enable a flexible and high-speed interaction between chiplets”, see Fig. 1, [0126], 1st sentence} between the first circuit and the second circuit {“By enabling a physical channel to virtual channel mapping and encapsulating time-based signaling with a packetized protocol, CPI bridges intra-chiplet networks across the chiplet network 622 [between first and second circuits].”, see Fig. 6a, [0126], last sentence}, a request signal {“host-based command request queues [and request signals]”, see Figs. 7 and 8, [0150, 2nd sentence}.
Rennig/Bender/Huynh and Hornung are analogous because they are from the same field of endeavor, managing DMA transfer(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Rennig/Bender/Huynh and Hornung before him or her, to modify Rennig/Bender/Huynh’s system incorporating Hornung’s “example tile 504”, respective “passthrough channel” and “CPI interface” (see Fig. 1, [0126], 1st sentence).
The suggestion/motivation for doing so would have been to implement new computing architectures and devices to advance computing performance beyond the practice of transistor scaling while considering moving data between processors (Hornung [0001], last sentence).
Therefore, it would have been obvious to combine Hornung with Rennig/Bende/Huynh to obtain the invention as specified in the instant claim(s).
As per claims 13-20 are method claims reciting claim functional language corresponding to the apparatus claims of claims 2-10, respectively, thereby rejected under the same rationale as claims 2-10 recited above.
Response to Arguments
Applicant’s arguments filed on 05/20/2026 have been considered but deemed moot in view of the new ground of rejection(s).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references indicative the current state of the art regarding claim 1’s “processing device”, “first circuit”, or “request signal”: US 20250390229 A1, US 12381751 B2, US 20220358063 A1, US 10459854 B2, US 9934173 B1, US 9032112 B1, US 6493803 B1, US 6341318 B1, and US 6003122 A.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A. BARTELS whose telephone number is (571)270-3182. The examiner can normally be reached on Monday-Friday 9:00a-5:30pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C. B./
Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
Prosecution Insights