Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection mailed on 08/20/2025. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/20/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected 35 U.S.C. 103 as being unpatentable over RENNIG et al. (US Pat No. 11853252 B2, hereinafter referred to as Rennig) in view of Bender et al. (USPGPUB No. 2005/0091383 A1, hereinafter referred to as Bender) and further in view of Barry et al. (USPGPUB No. 2022/0179657 A1, hereinafter referred to as Barry).
Referring to claim 1, Rennig discloses a processing device {processing device “processing system 10a, see Fig. 4, Col 8, lines 62-67}, comprising:
a first circuit {first circuit “communication interface 50 comprises…”, see Fig. 4, Col 9, lines 10-13};
a second circuit {“[other circuits] the communication system 114 or directly the memory controller 110”, see Figs. 4 and 5, Col 9, lines 23-25}; and
an event manager {event manager(s) “one or more DMA controller 110”, see Fig. 1, Col 8, lines 62-67} coupled between a first circuit {first circuit “communication interface 50 comprises…”, see Fig. 4, Col 9, lines 10-13} and a second circuit {“send read or write requests, respectively, either to [other circuits] the communication system 114 or directly the memory controller 110”, see Figs. 4 and 5, Col 9, lines 23-25}, the event manager comprising: an event channel {event channel “slave interface 1104 for … configuring the channels of the DMA controller 110”, see Fig. 4, Col 10, lines 34-36; the first circuit configured to:
assert a request signal {“DM interface circuit 506 may assert the request signal REQ”, see Fig. 5, Col 9, lines 39-40} via the event channel based on detecting an event {“[detecting an event] set a flag enabling the data transmission and/or a flag enabling DMA transfer”, see Fig. 5, Col 9, lines 35-37}, the first circuit is configured to, in response to detecting an assertion of an acknowledge signal {“in response to the acknowledge signal ACK11”, see Fig. 5, Col 9, lines 57-58}, de-assert the request signal {“may de-assert the request signal REQ1”, see Fig. 5, Col 9, lines 57-58};
Rennig does not appear to explicitly disclose wherein the second circuit is configured to, in response to detecting the assertion of the request signal, assert an control signal via the event channel, and the second circuit is configured to in response to detecting the de-assertion of the request signal, de-assert the control signal.
However, Bender discloses wherein the second circuit is configured to, in response to detecting the assertion of the request signal (“identifies all the channels with active requests” [0144], 2nd sentence), assert an the control signal via the event channel {“condition code field or the channel's channel status field and whether an indication is sent to the service processor”, see Table 29. [0376] last two lines of page 36}, and the second circuit is configured to, in response to detecting the de-assertion of the request signal {“source of pull descriptor with an active remote start [request signal] flag encountered after the initial source of pull descriptor is considered to be the same as an end of list condition [de-asserts as claimed]”, [0295] last sentence}, de-assert the control signal {“retry entry is cleared [and respective done signal de-asserts so that] the next oldest, entry appears”, [0578]}.
Rennig and Bender are analogous because they are from the same field of endeavor, managing DMA transfer(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Rennig and Bender before him or her, to modify Rennig’s respective circuit(s) incorporating Bender’s “Transport Macro logic 205” ([0540], see Fig. 38).
The suggestion/motivation for doing so would have been to implement communication adapters with mechanisms for time of day synchronization and with related mechanisms that establish backup and master/slave relationships amongst a plurality of adapters that permit designated backup adapter units to take over the communications operations of a failed adapter unit (Bender [0001] last sentence).
Therefore, it would have been obvious to combine Bender with Rennig to obtain the invention as specified in the instant claim(s).
However, neither Rennig or Bender appears to explicitly disclose wherein the control signal is asserting an acknowledge signal in response to detecting the assertion of the request signal.
Furthermore, Barry discloses wherein the control signal is asserting an acknowledge signal {“a particular event or a sequence of events has happened, the event filter 1302 can output control signals for controlling”, see Fig. 14, [0214], last sentence} in response to detecting the assertion of the request signal {“[event] filter module can be interrupted when it receives an interrupt request”, [0170], see Fig. 3}.
Rennig/Bender and Barry are analogous because they are from the same field of endeavor, managing DMA transfer(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Rennig/Bender and Barry before him or her, to modify Rennig/Bender’s system incorporating Barry’s “software defined interface 1102 can also include an event processor 1210” (see Fig. 14, [0209]).
The suggestion/motivation for doing so would have been to implement a flexible hardware/software architecture and a flexible hardware infrastructure (Barry [0005], last sentence) facilitating a general need for a flexible computational imaging infrastructure that can operate even under a constrained power budget (Barry [0005] and [0006]).
Therefore, it would have been obvious to combine Barry with Rennig/Bender to obtain the invention as specified in the instant claim(s).
As per claim 2, the rejection of claim 1 is incorporated and Bender discloses wherein: the event channel comprises a plurality of conductors {“using some [conductors] sideband capability or may use previously established message passing parameters”, [0427]}, and each conductor of the plurality of conductors {“consists of a single data interface with a sideband control interface to indicate [among plurality of logical conductors] the virtual lane[s] over which the data is transmitted”, see Fig. 40 [0535] last two sentences} is used to transmit a specific type of signal {“the type of [signals] transfer”, [0427] 1st sentence} between the first circuit and the second circuit {“sending and receiving software” ([0427]) of respective first and second circuits “communication adaptors 100a and 100b”, see Fig. 3 [0074]}.
As per claim 3, the rejection of claim 1 is incorporated and Bender discloses wherein the second circuit is further configured to begin processing the event {“Each descriptor identifies the channel and adapter intended to receive the data [when said descriptor is processed].”, see Fig. 17 [0428], 2nd sentence}.
As per claim 4, the rejection of claim 3 is incorporated and Bender discloses wherein: the second circuit is further configured to: in response to completion of the processing of the event {“completion code table field bits”, see Table after [0267]}, assert a completion signal via the event channel {“The local descriptor completion code field, CC, is updated with the final status of the operation. See Table 16 above”, [0268] last sentence}, and in response to detecting an assertion of a done acknowledge signal {“expected, then an acknowledgment packet is sent back to the sender”, see Fig. 38 [0539] last two sentences}, de-assert the completion signal {“The local descriptor completion code field, CC, is updated with the final status of the operation. See Table 16 above.”, see Fig. 17 [0268], last sentence};
and the first circuit is further configured to:
in response to detecting the assertion of the completion signal {“condition code field or the channel's channel status field and whether an indication is sent to the service processor”, see Table 29. [0376] last two lines of page 36}, assert the done acknowledge signal via the event channel {“When the associated response returns, the entry within the Request buffer contains the [claimed DONE ACK signal] bus tag for the response when it is put on to the processor bus”, see Fig. 17 [0539]}, and in response to detecting the de-assertion of the completion signal {“In the case where the resend is eventually successful [and respective completion signal de-asserted”, [0578] 1st sentence}, de-assert the done acknowledge signal {“retry entry is cleared [and respective done signal de-asserts so that] the next oldest, entry appears”, [0578]}.
As per claim 5, the rejection claim 1 is incorporated and Bender discloses wherein: the first circuit is further configured to:
transmit a count of a number of DMA transactions associated {“Descriptor Sequence Number is a monotonically increasing counter that increments whenever a new descriptor is used”, see Fig. 17 [0598], 6th sentence} with the request signal via the event channel {“Packet to the other side in order to initiate the transfer.”, see Fig. 17 [0597]; said first packet associated with a request via event channel “identifies all the channels with active requests” ([0144], 2nd sentence)};
and the second circuit is further configured to: in response to detecting the assertion of the request signal and the count {“back on the [other circuit] target side… a Pull Sequence Number that matches the [claimed request signal and count] one expected,”, see Fig. 17 [0599], 1st sentence}, begin processing the number of DMA transactions indicated by the count {“Once a packet is received for this channel that meets these conditions, the Descriptor Sequence Number of that packet is saved and the data transfer is assumed to have begun [processing the DMA as claimed]”, see Fig. 17 [0599] 3rd sentence}.
As per claim 6, the rejection claim 5 is incorporated and Bender discloses wherein: the second circuit is further configured to:
in response to completion of the processing of the number of the DMA transactions {“Descriptor Sequence Number is a monotonically increasing counter that increments whenever a new descriptor is used”, see Fig. 17 [0598], 6th sentence}, assert a completion signal via the event channel {“push response packet back to the send side indicating that the operation was (or perhaps was not) successful [completion]”, [0461]}, and in response to detecting an assertion of a done acknowledge signal {“when the receive side detects the [bus tag] echo packet”, [0463]}, de-assert the completion signal {“it removes [de-asserts the completion signal] the push response packet”, [0463]};
and the first circuit is further configured to: in response to detecting the assertion of the completion signal {“condition code field or the channel's channel status field and whether an indication is sent to the service processor”, see Table 29. [0376] last two lines of page 36}, assert the done acknowledge signal via the event channel {“When the associated response returns, the entry within the Request buffer contains the [claimed DONE ACK signal] bus tag for the response when it is put on to the processor bus”, see Fig. 17 [0539]}, and in response to detecting the de-assertion of the completion signal {“In the case where the resend is eventually successful [and respective completion signal de-asserted”, [0578] 1st sentence}, de-assert the done acknowledge signal {“retry entry is cleared [and respective done signal de-asserts so that] the next oldest, entry appears”, [0578]}.
As per claim 7, the rejection of claim 6 is incorporated and Bender discloses wherein: the second circuit is further configured to:
in response to completion of the processing of the number of the DMA transactions {“Descriptor Sequence Number is a monotonically increasing counter that increments whenever a new descriptor is used”, see Fig. 17 [0598], 6th sentence}, assert a done status signal via the event channel {“When the associated response returns, the entry within the Request buffer contains the [claimed DONE ACK signal] bus tag for the response when it is put on to the processor bus”, see Fig. 17 [0539]}, and in response to de-asserting the completion signal {“In the case where the resend is eventually successful [and respective completion signal de-asserted”, [0578] 1st sentence}, de-assert the done status signal {“retry entry is cleared [and respective done signal de-asserts so that] the next oldest, entry appears”, [0578]}.
As per claim 8, the rejection of claim 1 is incorporated and Bender discloses the first circuit further configured to:
detect an event prior to detecting {“using some [conductors] sideband capability or may use previously established message passing parameters”, [0427]} the assertion of the acknowledge signal via the event channel {“When the associated response returns, the entry within the Request buffer contains the [claimed DONE ACK signal] bus tag for the response when it is put on to the processor bus”, see Fig. 17 [0539]}, wherein the first circuit is configured to generate a second request signal based on detecting the event {“Packet to the other side in order to initiate the transfer.”, see Fig. 17 [0597]; said first packet associated with a request via event channel “identifies all the channels with active requests” ([0144], 2nd sentence)};
store information for generating the second request signal {first circuit “sending side… [it gather all of the information it needs into working registers” for the respective request signal, [0455]} in a queue {“working registers”, [0455] but also queue “maintenance of the work queue linked list and the interrupt queue linked list;” ([0235])};
and in response to detecting the assertion of the acknowledge signal via the event channel {“When the associated response returns, the entry within the Request buffer contains the [claimed DONE ACK signal] bus tag for the response when it is put on to the processor bus”, see Fig. 17 [0539]} and de-asserting the request signal via the event channel {“back on the [other circuit] target side… a Pull Sequence Number that matches the [claimed request signal and count] one expected,”, see Fig. 17 [0599], 1st sentence}, assert the second request signal via the event channel {“Packet to the other side in order to initiate the transfer.”, see Fig. 17 [0597]; said first packet associated with a request via event channel “identifies all the channels with active requests” ([0144], 2nd sentence).
As per claim 9, the rejection claim 1 is incorporated and Bender discloses further comprising a wakeup circuit coupled to the second circuit and configured to {wakeup circuit “finite state machine” that “describes the various states defined for a channel [to an associated circuit]”, see Fig. 16, Table 6 after [0204]}:
in response to detecting the assertion of the request signal via the event channel {detecting request signal “a request via event channel “identifies all the channels with active requests” ([0144], 2nd sentence” on event channel “using some [event channel conductors] sideband capability or may use previously established message passing parameters” ([0427])}, enable the second circuit from a sleep state to an enabled state {“resetting” state, see Table 6, transitions from a sleep state “stopped” to enabled state “invalid”, see Table 6 and Fig. 16} that allows the second circuit to detect the assertion of the request signal {“It also [detects and] discards any incoming [request] packet” in the “invalid state”, see Table 6}.
As per claim 10, the rejection of claim 1 is incorporated and Bender discloses wherein: the event manager selectably couples the first circuit to the second circuit and a third circuit {“adapter chip 200” in a network fabric to a third circuit “two message passing adapters 200D and 200Z” but as seen in Figure 6 includes a plurality of adapters, [0082], 7th sentence}; the third circuit is configured to:
in response to detecting the assertion of the request signal (“identifies all the channels with active requests” [0144], 2nd sentence} via the event channel {“using some [event channel conductors] sideband capability or may use previously established message passing parameters” ([0427]), assert, via the event channel, a second acknowledge signal to the first circuit {“condition code field or the channel's channel status field and whether an indication is sent to the service processor”, see Table 29. [0376] last two lines of page 36;
and the first circuit de-asserting the request signal {“source of pull descriptor with an active remote start [request signal] flag encountered after the initial source of pull descriptor is considered to be the same as an end of list condition [de-asserts as claimed]”, [0295] last sentence} is further in response to detecting both the acknowledge signal {“When the associated response returns, the entry within the Request buffer contains the [claimed DONE ACK signal] bus tag for the response when it is put on to the processor bus”, see Fig. 17 [0539]} and the second acknowledge signal {“when the [first circuit] receive side detects the [bus tag] echo packet”, [0463]}.
As per claim 11, the rejection claim 1 is incorporated and Bender discloses wherein the event manager is configured to:
dynamically assign each of a plurality of event channels {“target of pull descriptor [dynamically assigns] identifies the remote adapter and channel number that provides the data” per respective event channel, [0298]} between one of a plurality of publishing circuits {publishing circuits within each adapter executing “Sending and receiving software identify each other's [assigned] channel and logical ID values”, [0427]} and an associated subscribing circuit of a plurality of subscribing circuits {establishing circuitry executing “Receiving side software defines one or more target of push descriptors”, [0429]}, wherein the event channel is a first event channel of the plurality of event channels {“using some sideband capability or may use previously established message passing parameters” the sideband consisting a plurality of channels, [0427]}, the first circuit is a first publishing circuit of the plurality of publishing circuits {first publishing circuit executing “Sending side software defines one or more source of push descriptors”, [0428]}, and the second circuit is a first subscribing circuit of the plurality of subscribing circuits {“[subscribing circuit to] verify that the software task is authorized to issue the command and directs the command”, [0431], 1st sentence}.
Referring to claim 12, Rennig discloses a method comprising {a method performed by “processing system 10a, see Fig. 4, Col 8, lines 62-67}:
asserting, by a first circuit over an event channel between the first circuit and a second circuit, a request signal {“DM interface circuit 506 may assert the request signal REQ”, see Fig. 5, Col 9, lines 39-40};
in response to detecting the assertion of the request signal {in response as claimed “whereby the DMA channel DMA.sub.1 transfers a given number k of data packets TD1 . . . TDk”, see Fig. 5, Col 9, lines 40-42}, asserting, by the second circuit over the event channel, an acknowledge signal {“may also assert an acknowledge signal ACK.sub.1 indicating that the requested number k of packets TD1 . . . TDk has been transferred” associated with the first request signal, see Fig. 5, Col 9, lines 53-55};
in response to detecting the assertion of the acknowledge signal {“in response to the acknowledge signal ACK1”, see Fig. 5, Col 9, lines 56-58}, de-asserting, by the first circuit, the request signal {“may de-assert the request signal REQ1”, see Fig. 5, Col 9, lines 56-58}};
Rennig does not appear to explicitly disclose wherein the second circuit configured to:
in response to detecting the assertion of the request signal, assert the control signal via the event channel, and in response to detecting the de-assertion of the request signal, de-assert the control signal.
However, Bender discloses wherein the second circuit configured to:
in response to detecting the assertion of the request signal (“identifies all the channels with active requests” [0144], 2nd sentence), assert the control signal via the event channel {“condition code field or the channel's channel status field and whether an indication is sent to the service processor”, see Table 29. [0376] last two lines of page 36}, and in response to detecting the de-assertion of the request signal {“source of pull descriptor with an active remote start [request signal] flag encountered after the initial source of pull descriptor is considered to be the same as an end of list condition [de-asserts as claimed]”, [0295] last sentence}, de-assert the control signal {“retry entry is cleared [and respective done signal de-asserts so that] the next oldest, entry appears”, [0578]}.
Rennig and Bender are analogous because they are from the same field of endeavor, managing DMA transfer(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Rennig and Bender before him or her, to modify Rennig’s respective circuit(s) incorporating Bender’s “Transport Macro logic 205” ([0540], see Fig. 38).
The suggestion/motivation for doing so would have been to implement communication adapters with mechanisms for time of day synchronization and with related mechanisms that establish backup and master/slave relationships amongst a plurality of adapters that permit designated backup adapter units to take over the communications operations of a failed adapter unit (Bender [0001] last sentence).
Therefore, it would have been obvious to combine Bender with Rennig to obtain the invention as specified in the instant claim(s).
However, neither Rennig or Bender appears to explicitly disclose wherein the control signal is asserting an acknowledge signal in response to detecting the assertion of the request signal.
Furthermore, Barry discloses wherein the control signal is asserting an acknowledge signal {“a particular event or a sequence of events has happened, the event filter 1302 can output control signals for controlling”, see Fig. 14, [0214], last sentence} in response to detecting the assertion of the request signal {“[event] filter module can be interrupted when it receives an interrupt request”, [0170], see Fig. 3}.
Rennig/Bender and Barry are analogous because they are from the same field of endeavor, managing DMA transfer(s).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Rennig/Bender and Barry before him or her, to modify Rennig/Bender’s system incorporating Barry’s “software defined interface 1102 can also include an event processor 1210” (see Fig. 14, [0209]).
The suggestion/motivation for doing so would have been to implement a flexible hardware/software architecture and a flexible hardware infrastructure (Barry [0005], last sentence) facilitating a general need for a flexible computational imaging infrastructure that can operate even under a constrained power budget (Barry [0005] and [0006]).
Therefore, it would have been obvious to combine Barry with Rennig/Bender to obtain the invention as specified in the instant claim(s).
Referring to claims 13-20 are method claims reciting claim functional language corresponding to the apparatus claims of claims 1-10, respectively, thereby rejected under the same rationale as claims 1-10 recited above.
Response to Arguments
Applicant’s arguments, filed on 01/20/2026, have been considered however rendered moot in view of the new ground of rejection(s).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. These references reminiscent of claim 1’s first or second circuits, or “event manager”: US 20230231811 A1, US 20230195519 A1, US 20210058367 A1, US 20200134208 A1, US 20240104226 A1, US 20200125501 A1, US 20140201417 A1, and US 20120166690 A1.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A. BARTELS whose telephone number is (571)270-3182. The examiner can normally be reached on Monday-Friday 9:00a-5:30pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.A.B./
Examiner (Art Unit 2184)
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184