DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1 – 20 are pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 - 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sharma et al (US20230333998) hereinafter Sharma.
The applied reference has a common Assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
As to claim 1, Sharma discloses a computing system comprising: a memory device; (Fig. 1B, and element 30); a lock buffer coupled to the memory device (Fig. 1B, and element 38a); and an atomic unit (Fig. 1B, and element 34a) coupled to the lock buffer, wherein the atomic unit includes logic coupled to one or more substrates (Fig. 12, element 352), the logic (Fig. 12, element 354) to: detect a condition in which a plurality of atomic instructions target a common address and different bit positions in a mask, generate a combined read-lock request for the plurality of atomic instructions in response to the condition, and send the combined read-lock request to the lock buffer, wherein the memory device is associated with the common address (Fig. 2, and steps 42, and 44, where bitmapping processes and DMA (read operations occur, para. 0038, 0039).
As to claims 2, 7, and 14, Sharma discloses the computing system, wherein the logic is further to: detect a response to the combined read-lock request, combine an execution of the plurality of atomic instructions based on data in the response, detect a completion of the combined execution of the plurality of atomic instructions (Fig. 1B where engines such as 32a sends the requests for atomic operations, para. 0032), generate a combined write-unlock request for the plurality of atomic instructions in response to the completion of the combined execution, and send the combined write-unlock request to the lock buffer (Fig. 1B, and para. 0033 delivering the resultant data).
As to claims 3, 8, and 15, Sharma discloses the computing system, wherein the logic is further to: generate a combined store-with-acknowledgement request for the plurality of atomic instructions if a result update requirement is associated with the plurality of atomic instructions and send the combined store-with-acknowledgement request to the lock buffer (Store and waiting for responses, para. 0030).
As to claims 4, 10, and 17, Sharma discloses the computing system, wherein the logic is further to: detect a negative acknowledgement associated with the combined read-lock request, and prioritize a retry of the combined read-lock request through a first in first out buffer (Fig. 1B, where lock buffer is a Multi-entry buffer (Fifo), and Fig. 4 where re-try occurs, para. 0034).
As to claims 5, 11, 12, 18, and 19, Sharma discloses the computing system, wherein the memory device is a local memory device, the plurality of atomic instructions are to originate from a remote source in a distributed memory system, and the distributed memory system is to be a non-cached distributed memory system (Fig. 1A, and para. 0030, where plurality of MENG, 24 are the contributors).
As to claim 6, Sharma discloses At least one computer readable storage medium comprising a set of executable program instructions, which when executed, cause a computing system to: detect a condition in which a plurality of atomic instructions target a common address and different bit positions in a mask (Fig. 1a, and para. 0028 describes shared address, and plurality of pipelines); generate a combined read-lock request for the plurality of atomic instructions in response to the condition (Fig. 2, and steps 42, and 44, where bitmapping processes and DMA (read operations occur, para. 0038, 0039); and send the combined read-lock request to a lock buffer coupled to a memory device associated with the common address (Fig. 3, and para. 0042, where delivery to lock buffers occur).
As to claims 9, and 16, Sharma discloses the at least one computer readable storage medium, wherein the executable program instructions, when executed, further cause the computing system to: generate a combined store-with-acknowledgement request for the plurality of atomic instructions if a result update requirement is associated with the plurality of atomic instructions (Fig. 6, and paras. 0054- 0057); and send the combined store-with-acknowledgement request to the lock buffer (Fig. 7, and para. 0058).
As to claim 13, Sharma discloses a semiconductor apparatus comprising: one or more substrates (Fig. 12); and logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic to (Fig. 12 with logic 354): detect a condition in which a plurality of atomic instructions target a common address and different bit positions in a mask mask (Fig. 1a, and para. 0028 describes shared address, and plurality of pipelines); generate a combined read-lock request for the plurality of atomic instructions in response to the condition (Fig. 2, and steps 42, and 44, where bitmapping processes and DMA (read operations occur, para. 0038, 0039); and send the combined read-lock request to a lock buffer coupled to a memory device associated with the common address (Fig. 3, and para. 0042, where delivery to lock buffers occur).
As to claim 20, Sharma discloses the semiconductor apparatus, wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates (Fig. 12, and para. 0026 teaching the channels).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US20230315451, US10860388, and US20220121474, among others teach the operations of atomic transactions in a memory system, looking to due operation latency.
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/C.A.D/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
