Prosecution Insights
Last updated: April 19, 2026
Application No. 18/458,571

Mapping-Aware and Memory Topology-Aware Message Passing Interface Collectives

Non-Final OA §102§103
Filed
Aug 30, 2023
Examiner
KIM, SISLEY NAHYUN
Art Unit
2196
Tech Center
2100 — Computer Architecture & Software
Assignee
Advanced Micro Devices, Inc.
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
2y 9m
To Grant
99%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allow Rate
590 granted / 665 resolved
+33.7% vs TC avg
Strong +17% interview lift
Without
With
+16.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
42 currently pending
Career history
707
Total Applications
across all art units

Statute-Specific Performance

§101
9.1%
-30.9% vs TC avg
§103
49.6%
+9.6% vs TC avg
§102
26.1%
-13.9% vs TC avg
§112
7.2%
-32.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 665 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless - (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-3, 11-13, and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Archer et al. (US 2014/0047451, hereinafter Archer). Regarding claim 1, Archer discloses A node comprising: one or more processors; and one or more computer-readable storage media storing instructions that are executable by the one or more processors to cause the node to (paragraph [0004]: Computer systems typically include a combination of hardware and software components, application programs, operating systems, processors, buses, memory, input/output devices): select an affinity domain (paragraph [0112]: generating (1204), based on the affinities (1220) of the software threads (197), one or more affinity domains (1222)) for communication of data associated with a message passing interface (paragraph [0032]: the compute nodes (102) of parallel computer (100) are organized into at least one operational group (132) of compute nodes for collective parallel operations on parallel computer (100) … An operational group may be implemented as, for example, an MPI `communicator); select a first rank of a first process of the message passing interface assigned to a first partition of the affinity domain as a first partition leader rank and an affinity domain leader rank (paragraph [0032]: An operational group may be implemented as, for example, an MPI `communicator; paragraph [0062]: A rank uniquely identifies an application's location in the tree network for use in both point-to-point and collective operations in the tree network. The ranks in this example are assigned as integers beginning with `0` assigned to the root instance or root node (202), `1` assigned to the first node in the second layer of the tree; paragraph [0109]: Generating (1404), for each affinity domain, an n-ary tree (1422) representing a communication organization among the software threads associated with the affinity domain may be carried out by creating a data structure indicating which software threads communicate with each other in a particular affinity domain; paragraph [0113]: Designating (1502) an affinity domain leader (1522) may be carried out by selecting one of the software threads associated with a particular affinity domain to be the `leader` of that affinity domain); select a second rank of a second process of the message passing interface assigned to a second partition of the affinity domain as second partition leader rank (paragraph [0032]: An operational group may be implemented as, for example, an MPI `communicator; paragraph [0062]: A rank uniquely identifies an application's location in the tree network for use in both point-to-point and collective operations in the tree network. The ranks in this example are assigned as integers beginning with `0` assigned to the root instance or root node (202), `1` assigned to the first node in the second layer of the tree; paragraph [0113]: Designating (1502) an affinity domain leader (1522) may be carried out by selecting one of the software threads associated with a particular affinity domain to be the `leader` of that affinity domain); receive the data at the first partition leader rank; and communicate the data from the first partition leader rank to the second partition leader rank (paragraph [0113]: The affinity domain leader may be used to communicate with other affinity domain leaders such that software threads in different affinity domains may use only the domain leaders to communicate with each other). Regarding claim 11 referring to claim 1, Archer discloses A method comprising: … (See the rejection for claim 1). Regarding claims 2 and 12, Archer discloses wherein reception of the data at the first partition leader rank (paragraph [0113]: The affinity domain leader may be used to communicate with other affinity domain leaders such that software threads in different affinity domains may use only the domain leaders to communicate with each other) is based on: the selection of the first partition leader rank as the affinity domain leader rank (paragraph [0113]: Designating (1502) an affinity domain leader (1522) may be carried out by selecting one of the software threads associated with a particular affinity domain to be the `leader` of that affinity domain); and the affinity domain leader rank (paragraph [0113]: Designating (1502) an affinity domain leader (1522) may be carried out by selecting one of the software threads associated with a particular affinity domain to be the `leader` of that affinity domain) being mapped, by the node, to a virtual affinity domain leader rank (paragraph [0075]: each has assigned or mapped particular threads (253, 254, 262, 264) to advance (268, 270, 276, 278) work on the contexts (290, 292, 310, 312)). Regarding claims 3 and 13, Archer discloses wherein the communication of the data from the first partition leader rank to the second partition leader rank is based on at least one of: the selection of the first partition leader rank as the affinity domain leader rank (paragraph [0062]: A rank uniquely identifies an application's location in the tree network for use in both point-to-point and collective operations in the tree network. The ranks in this example are assigned as integers beginning with `0` assigned to the root instance or root node (202), `1` assigned to the first node in the second layer of the tree; paragraph [0113]: Designating (1502) an affinity domain leader (1522) may be carried out by selecting one of the software threads associated with a particular affinity domain to be the `leader` of that affinity domain); and the second partition leader rank being subordinate to the affinity domain leader rank within the affinity domain. Regarding claim 17, Archer discloses A node comprising: one or more processors; and one or more computer-readable storage media storing instructions that are executable by the one or more processors to cause the node to (paragraph [0004]: Computer systems typically include a combination of hardware and software components, application programs, operating systems, processors, buses, memory, input/output devices): select an affinity domain partition of an affinity domain and a second affinity domain partition of affinity domain (paragraph [0032]: An operational group may be implemented as, for example, an MPI `communicator; paragraph [0112]: generating (1204), based on the affinities (1220) of the software threads (197), one or more affinity domains (1222)) for communication of data associated with a message passing interface (paragraph [0032]: the compute nodes (102) of parallel computer (100) are organized into at least one operational group (132) of compute nodes for collective parallel operations on parallel computer (100) … An operational group may be implemented as, for example, an MPI `communicator); select a first rank of the message passing interface assigned to the first affinity domain partition as a first affinity domain rank (paragraph [0032]: An operational group may be implemented as, for example, an MPI `communicator; paragraph [0062]: A rank uniquely identifies an application's location in the tree network for use in both point-to-point and collective operations in the tree network. The ranks in this example are assigned as integers beginning with `0` assigned to the root instance or root node (202), `1` assigned to the first node in the second layer of the tree; paragraph [0113]: Designating (1502) an affinity domain leader (1522) may be carried out by selecting one of the software threads associated with a particular affinity domain to be the `leader` of that affinity domain); select a second rank of the message passing interface assigned to the second affinity domain partition as a second affinity domain leader rank (paragraph [0032]: An operational group may be implemented as, for example, an MPI `communicator; paragraph [0062]: A rank uniquely identifies an application's location in the tree network for use in both point-to-point and collective operations in the tree network. The ranks in this example are assigned as integers beginning with `0` assigned to the root instance or root node (202), `1` assigned to the first node in the second layer of the tree; paragraph [0113]: Designating (1502) an affinity domain leader (1522) may be carried out by selecting one of the software threads associated with a particular affinity domain to be the `leader` of that affinity domain); and communicate the data from the first affinity domain leader rank to the second affinity domain leader rank (paragraph [0113]: The affinity domain leader may be used to communicate with other affinity domain leaders such that software threads in different affinity domains may use only the domain leaders to communicate with each other). Regarding claim 18, Archer discloses wherein further instructions are executable by the one or more processors to cause the node to: assign a first tree topology to the first affinity domain partition; and assign, to the second affinity domain partition, a second tree topology (paragraph [0109]: An n-ary tree is a rooted tree in which each node has no more than n children. Generating (1404), for each affinity domain, an n-ary tree (1422) representing a communication organization among the software threads associated with the affinity domain may be carried out by creating a data structure indicating which software threads communicate with each other in a particular affinity domain). Regarding claim 19, Archer discloses wherein the communication of the data from the first affinity domain leader rank to the second affinity domain leader rank (paragraph [0113]: The affinity domain leader may be used to communicate with other affinity domain leaders such that software threads in different affinity domains may use only the domain leaders to communicate with each other) is based on further instructions executable by the one or more processors to cause the node to map: the first affinity domain leader rank (paragraph [0113]: Designating (1502) an affinity domain leader (1522) may be carried out by selecting one of the software threads associated with a particular affinity domain to be the `leader` of that affinity domain) to a first virtual affinity leader rank (paragraph [0075]: each has assigned or mapped particular threads (253, 254, 262, 264) to advance (268, 270, 276, 278) work on the contexts (290, 292, 310, 312); and the second affinity domain leader rank (paragraph [0113]: Designating (1502) an affinity domain leader (1522) may be carried out by selecting one of the software threads associated with a particular affinity domain to be the `leader` of that affinity domain) to a second virtual affinity leader rank (paragraph [0075]: each has assigned or mapped particular threads (253, 254, 262, 264) to advance (268, 270, 276, 278) work on the contexts (290, 292, 310, 312)). Regarding claim 20, Archer discloses wherein the communication of the data from the first affinity domain leader rank to the second affinity domain leader rank (paragraph [0113]: The affinity domain leader may be used to communicate with other affinity domain leaders such that software threads in different affinity domains may use only the domain leaders to communicate with each other) is based on further instructions executable by the one or more processors to cause the node to: group the first affinity domain leader rank paragraph [0032]: An operational group may be implemented as, for example, an MPI `communicator; paragraph [0062]: A rank uniquely identifies an application's location in the tree network for use in both point-to-point and collective operations in the tree network. The ranks in this example are assigned as integers beginning with `0` assigned to the root instance or root node (202), `1` assigned to the first node in the second layer of the tree; paragraph [0109]: Generating (1404), for each affinity domain, an n-ary tree (1422) representing a communication organization among the software threads associated with the affinity domain may be carried out by creating a data structure indicating which software threads communicate with each other in a particular affinity domain; paragraph [0113]: Designating (1502) an affinity domain leader (1522) may be carried out by selecting one of the software threads associated with a particular affinity domain to be the `leader` of that affinity domain) and the second affinity domain leader rank with a group of leader ranks of the affinity domain paragraph [0032]: An operational group may be implemented as, for example, an MPI `communicator; paragraph [0062]: A rank uniquely identifies an application's location in the tree network for use in both point-to-point and collective operations in the tree network. The ranks in this example are assigned as integers beginning with `0` assigned to the root instance or root node (202), `1` assigned to the first node in the second layer of the tree; paragraph [0109]: Generating (1404), for each affinity domain, an n-ary tree (1422) representing a communication organization among the software threads associated with the affinity domain may be carried out by creating a data structure indicating which software threads communicate with each other in a particular affinity domain; paragraph [0113]: Designating (1502) an affinity domain leader (1522) may be carried out by selecting one of the software threads associated with a particular affinity domain to be the `leader` of that affinity domain); map the first affinity domain leader rank as a virtual first affinity domain leader rank over the group of leader ranks (paragraph [0075]: each has assigned or mapped particular threads (253, 254, 262, 264) to advance (268, 270, 276, 278) work on the contexts (290, 292, 310, 312); paragraph [0113]: Designating (1502) an affinity domain leader (1522) may be carried out by selecting one of the software threads associated with a particular affinity domain to be the `leader` of that affinity domain); and map the second affinity domain leader rank as a second virtual affinity group (paragraph [0075]: each has assigned or mapped particular threads (253, 254, 262, 264) to advance (268, 270, 276, 278) work on the contexts (290, 292, 310, 312); paragraph [0113]: Designating (1502) an affinity domain leader (1522) may be carried out by selecting one of the software threads associated with a particular affinity domain to be the `leader` of that affinity domain). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Archer et al. (US 2014/0047451, hereinafter Archer) in view of Lu et al. (US 2023/0026837, hereinafter Lu). Regarding claim 8, Archer discloses wherein the selection of the affinity domain is based on further instructions executable by the one or more processors to cause the node to select one or more affinity domains for the communication of the data from a list of affinity domains (paragraph [0112]: generating (1204), based on the affinities (1220) of the software threads (197), one or more affinity domains (1222)) that includes a node level, … and a processor core level within the memory level (paragraph [0042]: Examples of a hardware domain include a core domain, a multi-chip module (MCM) domain, and a processor domain; paragraph [0048]: processor may access local memory quickly and remote memory more slowly, a configuration referred to as a Non-Uniform Memory Access or `NUMA.`). Archer does not disclose a node level, a socket level within the node level, a non-uniform memory access level within the socket level, a memory level within the non-uniform memory access level, and a processor core level within the memory level. Lu discloses a node level (paragraph [0016]: FIG. 1B depicts an example configuration for processor topology 106 of system 100 that comprises two NUMA nodes 0 and 1 (reference numerals 108(1) and 108(2))), a socket level within the node level (paragraph [0016]: FIG. 1B depicts an example configuration for processor topology 106 of system 100 that comprises two NUMA nodes 0 and 1 (reference numerals 108(1) and 108(2)), each including a processor socket 112(1)/112(2)), a non-uniform memory access level within the socket level (paragraph [0017]: Processor socket 112(1) includes two LLC domains 0 and 1 (reference numerals 110(1) and 110(2))), a memory level within the non-uniform memory access level (paragraph [0017]: Processor socket 112(1) includes two LLC domains 0 and 1 (reference numerals 110(1) and 110(2)), each of which consists of two processor cores 118(1) and 118(2)/118(3) and 118(4) that are directly attached to an LLC 120(1)/120(2)), and a processor core level within the memory level (paragraph [0017]: two processor cores 118(1) and 118(2)/118(3) and 118(4) that are directly attached to an LLC 120(1)/120(2))). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Archer by incorporating Lu’s processor topology including NUMA nodes, processor sockets, LLC domains, cores, LLCs, and DRAMs. The motivation would have been to schedule the virtual CPUs of a VM on a NUCA system (i.e., a computer system that includes one or more NUCA processors, each comprising multiple LLC domains) in an optimal manner (Lu paragraph [0012]). Regarding claim 9, Archer discloses wherein the selection of the affinity domain is based on at least one of a processor architecture (paragraph [0098]: An affinity domain indicates which software threads are assigned to hardware threads of the same hardware domain. A hardware domain may refer to an organizational level within a processor. Examples of hardware domains include a core domain, a multi-chip module (MCM) domain, and a processor domain), a mapping of processes of the message passing interface to hardware resources of the node, or a size of the data. Allowable Subject Matter Claims 4-7, 10, 14-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISLEY N. KIM whose telephone number is (571)270-7832. The examiner can normally be reached M-F 11:30AM -7:30PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Y. Blair can be reached on (571)270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SISLEY N KIM/Primary Examiner, Art Unit 2196 1/3/2026
Read full office action

Prosecution Timeline

Aug 30, 2023
Application Filed
Jan 05, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
99%
With Interview (+16.9%)
2y 9m
Median Time to Grant
Low
PTA Risk
Based on 665 resolved cases by this examiner. Grant probability derived from career allow rate.

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