Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-7, 10-16, 18, and 19 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
In the remarks, Applicant argued in substance that
(a) Although Mazumdar claims priority to Prov. Pat. App. Ser. No. 63/308,904 (the '904 application), the '904 application does not disclose the entire subject matter as published in Mazumdar. Therefore, only a portion of the disclosure of Mazumdar is supported by the priority claim and entitles to the priority date of the '904 application
(b) Although Mazumdar (e.g., FIG. 10) shows a reconfigurable processor (RP) memory 1062 and a network interface controller 1032, Mazumdar does not suggest that the RP memory 1062 is "accessible" via the network interface controller 1032. The title of Mazumdar states "Direct Access to External Storage from a Reconfigurable Processor" [Emphasis Added]. Thus, a person of ordinary skill in relevant fields would recognize that the reconfigurable processor (RP) of Mazumdar may access the "external storage" 960/1060/1160/1260 of Mazumdar (in FIG. 9 to FIG. 12). However, there is no indication that access can be performed in the other direction such that the "external storage" 960/1060/1160/1260 of Mazumdar (in FIG. 9 to FIG. 12) can access the memory 1062/1162/1262 of Mazumdar over the network 1036/1136/1236. In contrast, claim 1 recites "a memory configured to be accessible via the first interface". Therefore, the memory 1062/1162/1262 of Mazumdar does not correspond to the "memory" recited in the claim.
Examiner respectfully traversed Applicant’s remarks:
As to point (a), Applicant’s argument that the relied-upon portions of Mazumdar lack support in the '904 provisional application is unpersuasive. While Mazumdar contains additional material added during the non-provisional filing, the specific subject matter relied upon in the rejection of Claim 1 is fully supported by the '904 provisional application, entitling those portions to the February 10, 2022 effective prior art date under 35 U.S.C. § 102(a)(2).
In particular, the relied-upon disclosures in Mazumdar map directly to the '904 provisional as follows:
The First Interface (NIC/Network): Mazumdar paragraphs [0174], [0192], and [0204] are supported by the '904 Provisional at Fig. 1 & 2, paragraphs [0012] and [0017]-[0019].
The Memory (DRAM): Mazumdar paragraph [0015] is supported by the '904 Provisional at Fig. 2 and paragraph [0015].
The Second Interface (Bus Switch/Local Buses): Mazumdar [0187] is supported by the '904 Provisional at Fig. 2 and paragraph [0017].
Logic Circuit separating first and second messages (Direct vs. Buffered I/O): Mazumdar paragraphs [0223] and [0224] are supported by the '904 Provisional at Fig. 4 and paragraph [0040].
Generating third messages (IOMMU Translation): Mazumdar paragraph [0203] is supported by the '904 Provisional at Fig. 4 and paragraph [0046].
Therefore, the cited portions of Mazumdar are proper prior art under 35 U.S.C. § 102(a)(2).
As to point (b), Applicant’s argument that Mazumdar does not teach the RP memory 1062 being “accessible” via the network interface controller (the first interface) because access is only one-way is unpersuasive. The text of Mazumdar, as well as the '904 provisional, explicitly discloses two-way data transfer where the NIC accesses the RP memory to write data received from the external network. Specifically, the '904 provisional explicitly states at paragraph [0031]: “direct access from the DMA engine in the network interface card 332a to the external memory 160 transfers data from the external memory 160 via the network 136 to the network interface controller 332a and over the PCIe bus to the reconfigurable processors 142a and the reconfigurable processor memory 162a.” Furthermore, the '904 provisional at paragraph [0041] discloses that the system “directly moves data between the external memory 160 via the network interface card 332a to the reconfigurable processor memory 162a.” Because the DMA engine in the NIC (the first interface) directly accesses the RP memory to write data retrieved from the external storage, the RP memory is clearly “configured to be accessible via the first interface” as claimed. Therefore, the rejection is maintained.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless -
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, 10-16, 18, and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Mazumdar et al. (US 2023/0251989, hereinafter Mazumdar; Provisional Application No. 63/308,904 filed on 2/10/2022).
Regarding claim 1, Mazumdar discloses
A device, comprising:
a first interface (paragraph [0174]: Examples of the network 936 include a Storage Area Network (SAN), a Local Area Network (LAN), and a Wide Area Network (WAN) … Data communication protocols for use with the SAN can include Advanced Technology Attachment (‘ATA’), Fibre Channel Protocol, Small Computer System Interface (‘SCSI’), Internet Small Computer System Interface (‘iSCSI’), HyperSCSI, Non-Volatile Memory Express (‘NVMe’) over Fabrics, or the like; paragraph [0192]: the NIC 932 may include a direct memory access controller that generates memory addresses for the direct data access operation on the external storage 960 and initiates memory read and/or write operations; paragraph [0204]: network interface controller (NIC) 1132 that includes an application programming interface (API) 113);
a memory (paragraph [0015]: The attached reconfigurable processor memories 1062 may include main memory such as dynamic random-access memory (DRAM)) configured to be accessible via the first interface (paragraph [0174]: Examples of the network 936 include a Storage Area Network (SAN), a Local Area Network (LAN), and a Wide Area Network (WAN) … Data communication protocols for use with the SAN can include Advanced Technology Attachment (‘ATA’), Fibre Channel Protocol, Small Computer System Interface (‘SCSI’), Internet Small Computer System Interface (‘iSCSI’), HyperSCSI, Non-Volatile Memory Express (‘NVMe’) over Fabrics, or the like; paragraph [0194]: The data processing system 1000 includes an API (e.g., in the NIC 1032) that is configured to enable sending of data from the one or more reconfigurable processors 1042 via the NIC 1032 to the external storage 1060 and/or retrieving of data from the external storage 1060 via the NIC 1032 for the one or more reconfigurable processors 1042);
a second interface connectable to a processor that is external to the device (paragraph [0187]: bus switch 1024 couples multiple local busses 1025, 1026, 1027, thereby operatively coupling the one or more reconfigurable processors 1042, the host processor 1002, and the NIC 1032);
a logic circuit configured to separate incoming messages received in the first interface (paragraph [0174]: Examples of the network 936 include a Storage Area Network (SAN), a Local Area Network (LAN), and a Wide Area Network (WAN) … Data communication protocols for use with the SAN can include Advanced Technology Attachment (‘ATA’), Fibre Channel Protocol, Small Computer System Interface (‘SCSI’), Internet Small Computer System Interface (‘iSCSI’), HyperSCSI, Non-Volatile Memory Express (‘NVMe’) over Fabrics, or the like; paragraph [0194]: The data processing system 1000 includes an API (e.g., in the NIC 1032) that is configured to enable sending of data from the one or more reconfigurable processors 1042 via the NIC 1032 to the external storage 1060 and/or retrieving of data from the external storage 1060 via the NIC 1032 for the one or more reconfigurable processors 1042; paragraph [0196]: the API is configured to enable the retrieving of the data in integer multiples of a block size (i.e., page size) of the external storage 1060) into first messages (paragraph [0223]: In this scenario, a portion of the data to be transferred that includes a multiple of the block size of the external storage 1260 is transferred in directly between the external storage 1260 and the reconfigurable processor memory 1262 and/or the one or more reconfigurable processors 1242) and second messages, communicate the second messages via the second interface for processing by the processor (paragraph [0187]: bus switch 1024 couples multiple local busses 1025, 1026, 1027, thereby operatively coupling the one or more reconfigurable processors 1042, the host processor 1002, and the NIC 1032; paragraph [0203]: performing a remote read/write operation can represent a security risk; paragraph [0224]: The remainder of the data to be transferred is doing a buffered I/O transfer. As an example, when doing a buffered I/O transfer for retrieving data from the external storage 1260, the remainder of the data to be transferred is first copied from the external storage 1260 to the host memory 1234 and from the host memory 1234 to the target memory (i.e., to the reconfigurable processor memory 1262)) to generate third messages (paragraph [0203]: The IOMMU tables on the host processor 1002 will translate IOVA to PA before issuing a read or a write request to the reconfigurable processor memory 1062 locally or remotely), and process the first messages (paragraph [0223]: In this scenario, a portion of the data to be transferred that includes a multiple of the block size of the external storage 1260 is transferred in directly between the external storage 1260 and the reconfigurable processor memory 1262 and/or the one or more reconfigurable processors 1242) and the third messages (paragraph [0203]: The IOMMU tables on the host processor 1002 will translate IOVA to PA before issuing a read or a write request to the reconfigurable processor memory 1062 locally or remotely).
Regarding claim 2, Mazumdar discloses
wherein the first interface is a network interface (paragraph [0174]: Examples of the network 936 include a Storage Area Network (SAN), a Local Area Network (LAN), and a Wide Area Network (WAN) … Data communication protocols for use with the SAN can include Advanced Technology Attachment (‘ATA’), Fibre Channel Protocol, Small Computer System Interface (‘SCSI’), Internet Small Computer System Interface (‘iSCSI’), HyperSCSI, Non-Volatile Memory Express (‘NVMe’) over Fabrics, or the like; paragraph [0194]: The data processing system 1000 includes an API (e.g., in the NIC 1032) that is configured to enable sending of data from the one or more reconfigurable processors 1042 via the NIC 1032 to the external storage 1060 and/or retrieving of data from the external storage 1060 via the NIC 1032 for the one or more reconfigurable processors 1042).
Regarding claim 3, Mazumdar discloses
wherein the second interface is a host interface operatable on a bus connected to the processor (paragraph [0187]: bus switch 1024 couples multiple local busses 1025, 1026, 1027, thereby operatively coupling the one or more reconfigurable processors 1042, the host processor 1002, and the NIC 1032).
Regarding claim 4, Mazumdar discloses
wherein the device is configured to receive via the host interface (paragraph [0187]: bus switch 1024 couples multiple local busses 1025, 1026, 1027, thereby operatively coupling the one or more reconfigurable processors 1042, the host processor 1002, and the NIC 1032) a message selection configuration identifying first criteria, and identify the second messages based on the first criteria (paragraph [0203]: in a non-trusted environment, exposing the reconfigurable processor memory 1062 via its PCIe BAR2 memory-mapped region directly to any third-party RDMA devices for performing a remote read/write operation can represent a security risk… The IOMMU tables on the host processor 1002 will translate IOVA to PA before issuing a read or a write request to the reconfigurable processor memory 1062 locally or remotely).
Regarding claim 5, Mazumdar discloses
wherein the device is configured to receive the third messages (paragraph [0203]: in a non-trusted environment, exposing the reconfigurable processor memory 1062 via its PCIe BAR2 memory-mapped region directly to any third-party RDMA devices for performing a remote read/write operation can represent a security risk… The IOMMU tables on the host processor 1002 will translate IOVA to PA before issuing a read or a write request to the reconfigurable processor memory 1062 locally or remotely) via the host interface from the processor (paragraph [0187]: bus switch 1024 couples multiple local busses 1025, 1026, 1027, thereby operatively coupling the one or more reconfigurable processors 1042, the host processor 1002, and the NIC 1032).
Regarding claim 6, Mazumdar discloses
wherein the device is configured to process the first messages and the third messages without assistance from the processor in provision of network storage services responsive to the incoming messages received in the first interface (paragraph [0177]: remote direct memory access (RDMA); paragraph [0222]: Data is transferred from external storage 1260 to PCIe device memory such as reconfigurable processor memory 1262 while bypassing the file buffer cache and thereby the host memory 1234).
Regarding claim 7, Mazumdar discloses
wherein the message selection configuration further is configured to identify second criteria; and the device is configured to identify the first messages based on the second criteria (paragraph [0223]: In this scenario, a portion of the data to be transferred that includes a multiple of the block size of the external storage 1260 is transferred in directly between the external storage 1260 and the reconfigurable processor memory 1262 and/or the one or more reconfigurable processors 1242).
Regarding claim 10, Mazumdar discloses
A method, comprising:
receiving, via a first interface of a device, incoming messages to access a memory of the device (paragraph [0174]: Examples of the network 936 include a Storage Area Network (SAN), a Local Area Network (LAN), and a Wide Area Network (WAN) … Data communication protocols for use with the SAN can include Advanced Technology Attachment (‘ATA’), Fibre Channel Protocol, Small Computer System Interface (‘SCSI’), Internet Small Computer System Interface (‘iSCSI’), HyperSCSI, Non-Volatile Memory Express (‘NVMe’) over Fabrics, or the like; paragraph [0192]: the NIC 932 may include a direct memory access controller that generates memory addresses for the direct data access operation on the external storage 960 and initiates memory read and/or write operations; paragraph [0204]: network interface controller (NIC) 1132 that includes an application programming interface (API) 113);
separating, by the device, the incoming messages received via the first interface (paragraph [0174]: Examples of the network 936 include a Storage Area Network (SAN), a Local Area Network (LAN), and a Wide Area Network (WAN) … Data communication protocols for use with the SAN can include Advanced Technology Attachment (‘ATA’), Fibre Channel Protocol, Small Computer System Interface (‘SCSI’), Internet Small Computer System Interface (‘iSCSI’), HyperSCSI, Non-Volatile Memory Express (‘NVMe’) over Fabrics, or the like; paragraph [0194]: The data processing system 1000 includes an API (e.g., in the NIC 1032) that is configured to enable sending of data from the one or more reconfigurable processors 1042 via the NIC 1032 to the external storage 1060 and/or retrieving of data from the external storage 1060 via the NIC 1032 for the one or more reconfigurable processors 1042; paragraph [0196]: the API is configured to enable the retrieving of the data in integer multiples of a block size (i.e., page size) of the external storage 1060) and second messages (paragraph [0203]: performing a remote read/write operation can represent a security risk; paragraph [0224]: The remainder of the data to be transferred is doing a buffered I/O transfer. As an example, when doing a buffered I/O transfer for retrieving data from the external storage 1260, the remainder of the data to be transferred is first copied from the external storage 1260 to the host memory 1234 and from the host memory 1234 to the target memory (i.e., to the reconfigurable processor memory 1262));
communicating, via a second interface of the device, the second messages (paragraph [0203]: performing a remote read/write operation can represent a security risk; paragraph [0224]: The remainder of the data to be transferred is doing a buffered I/O transfer. As an example, when doing a buffered I/O transfer for retrieving data from the external storage 1260, the remainder of the data to be transferred is first copied from the external storage 1260 to the host memory 1234 and from the host memory 1234 to the target memory (i.e., to the reconfigurable processor memory 1262)) to a processor that is external to the device (paragraph [0187]: bus switch 1024 couples multiple local busses 1025, 1026, 1027, thereby operatively coupling the one or more reconfigurable processors 1042, the host processor 1002, and the NIC 1032) to generate third messages (paragraph [0203]: The IOMMU tables on the host processor 1002 will translate IOVA to PA before issuing a read or a write request to the reconfigurable processor memory 1062 locally or remotely); and
processing, by the device, the first messages (paragraph [0223]: In this scenario, a portion of the data to be transferred that includes a multiple of the block size of the external storage 1260 is transferred in directly between the external storage 1260 and the reconfigurable processor memory 1262 and/or the one or more reconfigurable processors 1242) and the third messages (paragraph [0203]: The IOMMU tables on the host processor 1002 will translate IOVA to PA before issuing a read or a write request to the reconfigurable processor memory 1062 locally or remotely) responsive to the incoming messages to access the memory of the device (paragraph [0196]: the API is configured to enable the retrieving of the data in integer multiples of a block size (i.e., page size) of the external storage 1060; paragraph [0223]: In this scenario, a portion of the data to be transferred that includes a multiple of the block size of the external storage 1260 is transferred in directly between the external storage 1260 and the reconfigurable processor memory 1262 and/or the one or more reconfigurable processors 1242).
Regarding claim 18 referring to claim 10, Mazumdar discloses A non-transitory computer storage medium storing instructions which, when executed in a device, cause the device to perform a method, comprising: … (paragraph [0076]: CPU, memory).
Regarding claim 11, Mazumdar discloses
wherein the incoming messages are configured to access the memory of the device (paragraph [0196]: the API is configured to enable the retrieving of the data in integer multiples of a block size (i.e., page size) of the external storage 1060; paragraph [0223]: In this scenario, a portion of the data to be transferred that includes a multiple of the block size of the external storage 1260 is transferred in directly between the external storage 1260 and the reconfigurable processor memory 1262 and/or the one or more reconfigurable processors 1242) using a storage protocol (paragraph [0174]: Data communication protocols for use with the SAN can include Advanced Technology Attachment (‘ATA’), Fibre Channel Protocol, Small Computer System Interface (‘SCSI’), Internet Small Computer System Interface (‘iSCSI’), HyperSCSI, Non-Volatile Memory Express (‘NVMe’) over Fabrics, or the like).
Regarding claim 12, Mazumdar discloses
wherein the storage protocol is according to: internet small computer systems interface; fibre channel; fibre channel over ethernet; network file system; or server message block (paragraph [0174]: Examples of the network 936 include a Storage Area Network (SAN), a Local Area Network (LAN), and a Wide Area Network (WAN). The SAN can be implemented with a variety of data communications fabrics, devices, and protocols. For example, the fabrics for the SAN can include Fibre Channel, Ethernet, InfiniBand™, Serial Attached Small Computer System Interface (‘SAS’), or the like. Data communication protocols for use with the SAN can include Advanced Technology Attachment (‘ATA’), Fibre Channel Protocol, Small Computer System Interface (‘SCSI’), Internet Small Computer System Interface (‘iSCSI’), HyperSCSI, Non-Volatile Memory Express (‘NVMe’) over Fabrics, or the like).
Regarding claim 13, Mazumdar discloses
wherein the first interface is a network interface (paragraph [0174]: Examples of the network 936 include a Storage Area Network (SAN), a Local Area Network (LAN), and a Wide Area Network (WAN) … Data communication protocols for use with the SAN can include Advanced Technology Attachment (‘ATA’), Fibre Channel Protocol, Small Computer System Interface (‘SCSI’), Internet Small Computer System Interface (‘iSCSI’), HyperSCSI, Non-Volatile Memory Express (‘NVMe’) over Fabrics, or the like; paragraph [0194]: The data processing system 1000 includes an API (e.g., in the NIC 1032) that is configured to enable sending of data from the one or more reconfigurable processors 1042 via the NIC 1032 to the external storage 1060 and/or retrieving of data from the external storage 1060 via the NIC 1032 for the one or more reconfigurable processors 1042); and
the second interface is a host interface operatable on a bus connected to the processor (paragraph [0187]: bus switch 1024 couples multiple local busses 1025, 1026, 1027, thereby operatively coupling the one or more reconfigurable processors 1042, the host processor 1002, and the NIC 1032).
Regarding claims 14 and 19, Mazumdar discloses
further comprising: receiving, via the host interface (paragraph [0187]: bus switch 1024 couples multiple local busses 1025, 1026, 1027, thereby operatively coupling the one or more reconfigurable processors 1042, the host processor 1002, and the NIC 1032), a message selection configuration identifying first criteria; and identifying the second messages based on the first criteria (paragraph [0203]: in a non-trusted environment, exposing the reconfigurable processor memory 1062 via its PCIe BAR2 memory-mapped region directly to any third-party RDMA devices for performing a remote read/write operation can represent a security risk… The IOMMU tables on the host processor 1002 will translate IOVA to PA before issuing a read or a write request to the reconfigurable processor memory 1062 locally or remotely).
Regarding claim 15, Mazumdar discloses
wherein the device is configured to receive the third messages (paragraph [0203]: in a non-trusted environment, exposing the reconfigurable processor memory 1062 via its PCIe BAR2 memory-mapped region directly to any third-party RDMA devices for performing a remote read/write operation can represent a security risk… The IOMMU tables on the host processor 1002 will translate IOVA to PA before issuing a read or a write request to the reconfigurable processor memory 1062 locally or remotely) via the host interface from the processor (paragraph [0187]: bus switch 1024 couples multiple local busses 1025, 1026, 1027, thereby operatively coupling the one or more reconfigurable processors 1042, the host processor 1002, and the NIC 1032).
Regarding claim 16, Mazumdar discloses
wherein the message selection configuration further is configured to identify second criteria; and the device is configured to identify the first messages based on the second criteria (paragraph [0223]: In this scenario, a portion of the data to be transferred that includes a multiple of the block size of the external storage 1260 is transferred in directly between the external storage 1260 and the reconfigurable processor memory 1262 and/or the one or more reconfigurable processors 1242).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made
Claims 8, 9, 17, and 20are rejected under 35 U.S.C. 103 as being unpatentable over Mazumdar et al. (US 2023/0251989, hereinafter Mazumdar) in view of Zou et al. (US 2021/0326270, hereinafter Zou).
Regarding claims 8 and 17, Mazumdar does not disclose wherein the device is further configured to identify, among the incoming messages received in the first interface, fourth messages that do not meet the first criteria and do not meet the second criteria, and reject or block the fourth messages. Zou discloses wherein the device is further configured to identify, among the incoming messages received in the first interface, fourth messages that do not meet the first criteria and do not meet the second criteria, and reject or block the fourth messages (paragraph [0029]: redirector device can receive, from an initiator device, a request that identifies a data set to be accessed … The request may be a request to read from a data set, as indicated in block 326, or to write to a data set, as indicated in block 328; paragraph [0032]: As indicated in block 342, redirector device may identify resilvering write requests (e.g., requests to write data to a replica that in the process of being created). In doing so, and as indicated in block 344, redirector device discards any redundant resilvering write requests (e.g., requests to write to the same logical block address)). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Mazumdar by incorporating Zou’s identifying resilvering write requests and discarding any redundant resilvering write requests. The motivation would have been to enable requests to be sent more directly to the precise locations (e.g., the storage server 130, 132, 134 that actually stores a particular data set) (Zou paragraph [0016]).
Regarding claim 9, Mazumdar discloses
wherein the network storage services are based on a storage protocol according to: internet small computer systems interface; fibre channel; fibre channel over ethernet; network file system; or server message block (paragraph [0174]: Examples of the network 936 include a Storage Area Network (SAN), a Local Area Network (LAN), and a Wide Area Network (WAN). The SAN can be implemented with a variety of data communications fabrics, devices, and protocols. For example, the fabrics for the SAN can include Fibre Channel, Ethernet, InfiniBand™, Serial Attached Small Computer System Interface (‘SAS’), or the like. Data communication protocols for use with the SAN can include Advanced Technology Attachment (‘ATA’), Fibre Channel Protocol, Small Computer System Interface (‘SCSI’), Internet Small Computer System Interface (‘iSCSI’), HyperSCSI, Non-Volatile Memory Express (‘NVMe’) over Fabrics, or the like).
Regarding claim 20, Mazumdar discloses
wherein the message selection configuration further is configured to identify second criteria; and the method further comprises: identifying, based on the second criteria, the first messages among the incoming messages (paragraph [0223]: In this scenario, a portion of the data to be transferred that includes a multiple of the block size of the external storage 1260 is transferred in directly between the external storage 1260 and the reconfigurable processor memory 1262 and/or the one or more reconfigurable processors 1242).
Mazumdar does not disclose identifying, among the incoming messages received via the first interface, fourth messages that do not meet the first criteria and do not meet the second criteria; and rejecting or blocking the fourth messages. Zou discloses identifying, among the incoming messages received via the first interface, fourth messages that do not meet the first criteria and do not meet the second criteria; and rejecting or blocking the fourth messages (paragraph [0029]: redirector device can receive, from an initiator device, a request that identifies a data set to be accessed … The request may be a request to read from a data set, as indicated in block 326, or to write to a data set, as indicated in block 328; paragraph [0032]: As indicated in block 342, redirector device may identify resilvering write requests (e.g., requests to write data to a replica that in the process of being created). In doing so, and as indicated in block 344, redirector device discards any redundant resilvering write requests (e.g., requests to write to the same logical block address)). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Mazumdar by incorporating Zou’s identifying resilvering write requests and discarding any redundant resilvering write requests. The motivation would have been to enable requests to be sent more directly to the precise locations (e.g., the storage server 130, 132, 134 that actually stores a particular data set) (Zou paragraph [0016]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Muthiah (US 2023/0401005) discloses “RDMA” (paragraph [0053]) and “host interface 530 may include a host request handler 534 configured to handle a plurality of host requests and translate them into storage and/or compute commands to be executed by a data storage device” (paragraph [0054]).
Turlik et al. (US 2023/0297527) discloses “in a non-trusted environment, exposing the reconfigurable processor memory (e.g., reconfigurable processor memory 1162a) via its PCIe BAR2 memory-mapped region directly to any third-party remote direct memory access (RDMA) devices for performing a remote read/write operation can represent a security risk … The IOMMU tables 1280 on the host processor (e.g., host processor 1102a of FIG. 11) will translate IOVA to PA before issuing a read or a write request to the reconfigurable processor memory locally or remotely” (paragraph [0231]).
Navon et al. (US 2022/0221999) discloses “a host write operation may trigger a deduplication operation to determine whether the target data unit is already stored (and/or is stored in a number of copies at or above a duplicate target) before writing the new copy (and may discard the write operation if the duplicate is not within the duplicate policy” (paragraph [0063]).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in [0037] CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to [0037] CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISLEY N. KIM whose telephone number is (571)270-7832. The examiner can normally be reached M-F 11:30AM -7:30PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Y. Blair can be reached on (571)270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SISLEY N KIM/Primary Examiner, Art Unit 2196 06/12/2026
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