DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-15 in the reply filed on 6/26/2026 is acknowledged.
Claim Rejections - 35 USC § 112
Claims 1-7 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 is indefinite because "the determination" lacks positive antecedent basis. Claim 9 is indefinite because the claim should recite "central server" instead of "central sever".
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-6, 26-28, and 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoneda (5896875) in view of Haifeng et al. (CN101359578, IDS of 8/21/2024).
Re claims 1 and 26, Yoneda teaches cleaning, etching and drying a semiconductor wafer provided within a process chamber (Fig. 1) , wherein the wafer is placed in a bath filled with a process solution (i.e. cleaning or etching solution for a preset period of time(col. 5-6 bridging, col. 10, lines 1-20 for example), and draining the process solution from the bath while the wafer is in the bath (col. 10, lines 20-25), following by rinsing and drying of the wafer surface (col. 5-6 bridging of Yoneda).
Yoneda does not teach determining whether the wafer is in the process bath and draining the process solution after the preset process time while the wafer is in the bath. Haifeng et al., as cited by applicant's own IDS, teach washing a wafer, a detecting device to detect the wafer in the bath during the washing step, a control system which is used to control the rinse bath, and a monitoring device which is used to monitor the time during which the wafer is disposed in the rinse bath according to the wafer detection signal and a draining device to drain the liquid when the time exceeds the alert time in order to avoid damages to the wafer caused by the wafer disposed in the washing liquid after a cleaning time. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method of Yoneda to include determining the wafer in the bath after the preset cleaning time and draining the processing liquid while the wafer is in the bath, as taught by Haifeng et al., for purposes of avoiding damages to the wafer surface. Furthermore, in the absence of a showing of criticality and/or unexpected results, it would have been well within the level of the skilled artisan to drain the chemical solution after the preset period of time in order to rinse and dry the wafer surface. Re claim 2, refer to col. 4, lines 50-65 of Yoneda. Re claims 3-4, refer to rinsing the wafer with ultrapure water (for example, Fig. 4, step S25 of Yoneda). Re claim 5, refer to steps S26-S28 of Yoneda. Re claims 6 and 27, refer to Fig. 1 of Yoneda and col. 9, lines 5-7 directed to the drain port. Re claim 28, refer to S44 of Fig. 6 of Yoneda et al. for example. Re claim 30, refer to col. 4, lines 50-60 of Yoneda et al.
Claim(s) 7 and 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoneda (5896875) in view of Haifeng et al. (CN101359578, IDS of 8/21/2024) and further in view of Jung et al. (US2009/00953253).
Yoneda in view of Haifeng et al. teach the invention substantially as claimed with the exception of the bath having an inner and outer bath, the inner bath disposed in the outer bath and draining the solution from the inner and outer baths. Jung et al. teach a substrate treating apparatus (Fig. 1) having an inner bath 111 disposed in an outer bath 112 (paragraph 41), wherein process solution from the inner bath overflows to the outer bath, and both inner and outer baths are discharged of the process solution (paragraphs 48-49). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have modified the modified method of Yoneda to include a bath having an inner and outer bath, as taught by Jung et al. to allow for overflow of the processing solution from the inner bath during processing of the wafer.
Claim(s) 8-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoneda (5896875) in view of Muraoka et al. (JP4245200B; machine translation).
Yoneda teaches cleaning, etching and drying a semiconductor wafer provided within a process chamber (Fig. 1) , wherein the wafer is placed in a bath filled with a process solution (i.e. cleaning or etching solution for a preset period of time(col. 5-6 bridging, col. 10, lines 1-20 for example), and draining the process solution from the bath while the wafer is in the bath (col. 10, lines 20-25), following by rinsing and drying of the wafer surface (col. 5-6 bridging of Yoneda). Yoneda does not teach a control module wherein the control module recites a signal to perform a process of draining the process solution from the bath, wherein a central server receives an alarm signal, wherein the signal is provided by a monitor device coupled to the wet processing apparatus. Re claims 8-10, in view of the indefiniteness, the claims are broadly interpreted as controlling the drainage of the processing solution from a bath using signals which are received by a controller. Muraoka et al. teach immersing a substrate in a treatment tank 1 and a controller 8 (paragraph 34), comprising discharge detection sensors 44 (i.e. monitor devices), which are coupled to the tank via elements 41,45, 43, wherein based on the detection signals output from each drainage detector sensor 44, the controller 8 monitors and discharges the liquid from the treatment tank 1 (Fig.1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to have modified the method of Yoneda, to include a controller comprising sensors (i.e. monitoring devices), as taught by Muraoka et al. for purposes of monitoring and discharging the processing liquids from the treatment tank. Re claim 11, the claim is broadly interpreted as opening the valve to drain the liquid from the bath. Applicant is directed to paragraph 6 of Muraoka et al. which teaches the controller opening and closing valve 133 to allow for various liquids to be discharged from the treatment tank. Re claim 12, Yoneda further teaches rinsing with ultrapure water after the cleaning/etching step. Re claim 13, in view of the teachings of Muraoka et al., and in the absence of a showing of criticality and/or unexpected results, it would have been well within the level of the skilled artisan to use a controller to supply fluid to the bath since Muraoka et al. teach using a controller to open/close valves to allow the supply and discharge of fluids from the treatment tank. Re claim 14, refer to the teachings of Yoneda which teaches purging by adding a nitrogen gas, as previously discussed. Re claim 15, refer to steps S49-S50 of Yoneda.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim et al. teach an etching process of immersion, rinsing and drying. Taniguchi et al. teach detecting an etching endpoint. Jung et al. teach wet etch. Weber teach cleaning a wafer after cmp. Masuda teach photosensors. Liu teaches wafer failure. Lee et al. teach various process solutions for etching. Chen et al. teach detecting wafer damage. Chen et al. teach sensors to monitor the wafer presence.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Sharidan Carrillo whose telephone number is (571)272-1297. The examiner can normally be reached M-F, 7:00am-4:00pm.
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Sharidan Carrillo
Primary Examiner
Art Unit 1711
/Sharidan Carrillo/Primary Examiner, Art Unit 1711 bsc
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