DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment dated 03/23/2026, in which claims 1, 4-6, 12, 19 were amended, claims 2-3, 17-18 were cancelled, has been entered.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d) to foreign application JP2023-049092 filed on 03/24/2023. The foreign application is not in English. The certified copy of the foreign priority application JP2023-049092 has been received.
Filing Dates for the Claims — All Claims Not Entitled to Priority Date
To be entitled to the filing date of the foreign priority application JP2023-049092 that is not in English, an English translation of the non-English language foreign application JP2023-049092 and a statement that the translation is accurate in accordance with 37 CFR 1.55 is required to perfect the claim for priority under 35 U.S.C. 119 (a)-(d). The foreign application must adequately support the claimed subject matter, meaning satisfy the written description and enablement requirements of 35 U.S.C. 112(a). See MPEP §§ 215 and 216. 37 C.F.R. 1.55(g)(3)(ii)-(iii). To demonstrate compliance with 35 U.S.C. 112(a), applicant should point to support for their claimed subject matter in their translations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 6-7, 9-16, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Asaba et al. (US Pub. 20230092735) in view of Okumura (US Pub. 20200266294), Kono et al. (US Pub. 20150263158) and Oota et al. (US Pat. 9887285).
Regarding claims 1, 4, 6 and 11, Asaba et al. discloses in Fig. 3-Fig. 5, Fig. 12-Fig. 14 a semiconductor device comprising:
a silicon carbide layer [10] including a first surface and a second surface on opposite sides of the silicon carbide layer,
the silicon carbide layer [10] including
a first silicon carbide region [24] of a first conductivity type [n type][paragraph [0046]],
a second silicon carbide region [26a] of a second conductivity type [p type] provided between the first silicon carbide region [24] and the first surface [paragraph [0046]],
a third silicon carbide region [28a] of the second conductivity type [p type] provided between the second silicon carbide region [26] and the first surface and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the second silicon carbide region [26][paragraph [0046]], and
a fourth silicon carbide region [30a] of the first conductivity type [ n type] provided between the second silicon carbide region [26] and the first surface [paragraph [0046]],
a first gate electrode [18a] extending in a first direction parallel to the first surface and facing the second silicon carbide region [26a];
a second gate electrode [18b] extending in the first direction, spaced from the first gate electrode [18a] in a second direction parallel to the first surface and perpendicular to the first direction, and facing the second silicon carbide region [26a];
a first gate insulating layer [16a] provided between the second silicon carbide region [26a] and the first gate electrode [18a];
a second gate insulating layer [16b] provided between the second silicon carbide region [26a] and the second gate electrode [18b];
a first electrode [12] provided on the first surface side of the silicon carbide layer [10],
the first electrode [12] including
a first portion [12x1] provided between the first gate electrode [18a] and the second gate electrode [18b] and in contact with the third silicon carbide region [28a] and the fourth silicon carbide region [30a]; and
a second portion [12y1] provided between the first gate electrode [18a] and the second gate electrode [18b], spaced from the first portion in the first direction, and in contact with the first silicon carbide region [24], and
a second electrode [14] provided on the second surface side of the silicon carbide layer [10],
wherein the first silicon carbide region [10] includes a first region [lower region of 10], and second, third, and fourth regions [upper regions of 10 directly contact region 26] provided between the first region [lower region of 10] and the second silicon carbide region [26a],
the second silicon carbide region [26a] includes a fifth region facing the first gate electrode [18a], a sixth region facing the second gate electrode [18b], and a seventh region provided between the fifth region and the sixth region [Fig. 4, Fig. 13],
the second region is provided between the first region and the fifth region,
the third region is provided between the first region and the sixth region, and
the fourth region is provided between the first region and the seventh region;
wherein the seventh region is provided between the third silicon carbide region [28a] and the fourth region.
PNG
media_image1.png
589
808
media_image1.png
Greyscale
Asaba et al. fails to disclose
a first conductivity type impurity concentration of the second region is higher than a first conductivity type impurity concentration of the first region,
a first conductivity type impurity concentration of the third region is higher than the first conductivity type impurity concentration of the first region.
Oota et al. discloses in Fig. 1, Fig. 6, column 4, lines 49-60, column 7, lines 59-67, column 8, lines 1-11
a first conductivity type impurity concentration of the second region [n-type region 26 underlying first gate] is higher than a first conductivity type impurity concentration of the first region [24][“An impurity concentration of the n-type impurities in the low resistance region 26 is higher than the impurity concentration of the n-type impurities in the drift region 24”],
a first conductivity type impurity concentration of the third region [n type region 26 between first and second gate] is higher than the first conductivity type impurity concentration of the first region [24][“An impurity concentration of the n-type impurities in the low resistance region 26 is higher than the impurity concentration of the n-type impurities in the drift region 24”].
PNG
media_image2.png
602
703
media_image2.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Oota et al. into the method of Asaba et al. to include wherein a first conductivity type impurity concentration of the second region is higher than a first conductivity type impurity concentration of the first region, a first conductivity type impurity concentration of the third region is higher than the first conductivity type impurity concentration of the first region. The ordinary artisan would have been motivated to modify Asaba et al. in the above manner for the purpose of preventing the growth of the stacking fault in the silicon carbide layer and reliability can be improved [column 8, lines 1-11 of Oota et al.].
Asaba et al. and Oota et al. fails to disclose
wherein the first conductivity type impurity concentration of the fourth region is higher than the first conductivity type impurity concentration of the second region and the third region;
wherein the first conductivity type impurity concentration of the fourth region is 1.5 to 10 times the first conductivity type impurity concentration of the second region; and
the first conductivity type impurity concentration of the fourth region is 1.5 to 10 times the first conductivity type impurity concentration of the third region.
Okumura discloses in Fig. 1, Fig. 7A, paragraph [0066], [0069], [0072], [0078]
wherein the first conductivity type impurity concentration of the fourth region [17] is higher than the first conductivity type impurity concentration of the second region [5 right] and the third region [5];
wherein the first conductivity type impurity concentration of the fourth region [17] is 1.5 to 10 times the first conductivity type impurity concentration of the second region [5/5a]; and
the first conductivity type impurity concentration of the fourth region [17] is 1.5 to 10 times the first conductivity type impurity concentration of the third region [5/5a].
[paragraph [0066], “an n+-type region (first semiconductor region of the first conductivity type) 17 having a peak impurity concentration higher than the n-type high-concentration region 5”; paragraph [0069] “the impurity concentration of the n+-type region 17 may be in a range from 1×1017/cm3 to 1×1020/cm3”; paragraph [0078], “dose amount during ion implantation for forming the first n-type region 5a, for example, may be set so that the impurity concentration becomes about 1×1017/cm3”].
PNG
media_image3.png
439
444
media_image3.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Okumura into the method of Asaba et al. and Oota et al. to include wherein the first conductivity type impurity concentration of the fourth region is higher than the first conductivity type impurity concentration of the second region and the third region; wherein the first conductivity type impurity concentration of the fourth region is 1.5 to 10 times the first conductivity type impurity concentration of the second region; and the first conductivity type impurity concentration of the fourth region is 1.5 to 10 times the first conductivity type impurity concentration of the third region. The ordinary artisan would have been motivated to modify Asaba et al. and Oota et al. in the above manner for the purpose of enabling the position where electric field concentrates to be controlled [paragraph [0072] of Okumura].
In addition, Applicant has not provided any criticality of the claimed range. The ordinary artisan would have been motivated to modify Asaba et al., Oota et al. and Okumura to include the claimed range for at least the purpose of optimization and routine experimentation. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Asaba et al. fails to disclose
the seventh region having a shallower depth than a depth of the fifth region and a depth of the sixth region;
wherein the depth of the seventh region is one-half or less the depth of the fifth region; and
the depth of the seventh region is one-half or less the depth of the sixth region.
Kono et al. discloses in Fig. 5A, paragraph [0037], [0047]-[0052]
the seventh region [31a] having a shallower depth than a depth of the fifth region [31b left] and a depth of the sixth region [31b right];
wherein the depth of the seventh region [31a] is one-half or less the depth of the fifth region [31 left]; and
the depth of the seventh region [31a] is one-half or less the depth of the sixth region [31 right].
PNG
media_image4.png
431
448
media_image4.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Kono et al. into the method of Asaba et al. to include the seventh region having a shallower depth than a depth of the fifth region and a depth of the sixth region; wherein the depth of the seventh region is one-half or less the depth of the fifth region; and the depth of the seventh region is one-half or less the depth of the sixth region. The ordinary artisan would have been motivated to modify Asaba et al. in the above manner for the purpose of reducing the chip surface area, reducing conduction loss, reducing/ minimizing the forming of stacking faults and reliably suppressing leakage current in the semiconductor device [paragraph [0047]-[0052] of Kono et al.].
Regarding claim 7, Asaba et al. discloses in Fig. 3-Fig. 5, Fig. 12-Fig. 14
a third gate electrode [18c] extending in the first direction, spaced from the second gate electrode [18b] in the second direction, so that the second gate electrode [18b] is between the first gate electrode [18a] and the third gate electrode [18c]; and
a third gate insulating layer [16c],
wherein the silicon carbide layer [10] further includes
a fifth silicon carbide region [26b] of the second conductivity type provided between the first silicon carbide region [24] and the first surface and separated from the second silicon carbide region [26a] in the second direction,
a sixth silicon carbide region [28b] of the second conductivity type provided between the fifth silicon carbide region [26b] and the first surface and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the fifth silicon carbide region [26b], and
a seventh silicon carbide region [30] of the first conductivity type provided between the fifth silicon carbide region [28b] and the first surface,
the second gate electrode [18b] faces the fifth silicon carbide region [26b],
the second gate insulating layer [16b] is provided between the fifth silicon carbide region [26b] and the second gate electrode [18b],
the third gate electrode [18c] faces the fifth silicon carbide region [26b],
the third gate insulating layer [16c] is provided between the fifth silicon carbide region [26b] and the third gate electrode [18c], and
the first electrode [12] further includes a third portion [12x2] provided between the second gate electrode [18b] and the third gate electrode [18c] and in contact with the sixth silicon carbide region [28b] and the seventh silicon carbide region [30b].
Regarding claim 9, Asaba et al. discloses in Fig. 12, Fig. 14
wherein the third portion [12x2] is aligned with the second portion [12y1] in the second direction.
Regarding claim 10, Asaba et al. discloses in Fig. 4-Fig. 5, Fig. 13-Fig. 14
wherein the first surface is between the first gate electrode [18a] and the second silicon carbide region [26a], and between the second gate electrode [18b] and the second silicon carbide region [26a].
Regarding claims 12, 19 and 20, Asaba et al. discloses in Fig. 3-Fig. 5, Fig. 12-Fig. 14 a semiconductor device comprising:
a silicon carbide layer [10] including a first surface and a second surface on opposite sides of the silicon carbide layer, the silicon carbide layer [10] including
a first silicon carbide region [24] of a first conductivity type [n type],
a second silicon carbide region [26a] of a second conductivity type [p type] provided between the first silicon carbide region [24] and the first surface,
a third silicon carbide region [28a] of the second conductivity type [p type] provided between the second silicon carbide region [26a] and the first surface and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the second silicon carbide region [26a], and
a fourth silicon carbide region [30a] of the first conductivity type [ n type] provided between the second silicon carbide region [28a] and the first surface,
a first gate electrode [18a] extending in a first direction parallel to the first surface and facing the second silicon carbide region [26a];
a second gate electrode [18b] extending in the first direction, spaced from the first gate electrode [18a] in a second direction parallel to the first surface and perpendicular to the first direction, and facing the second silicon carbide region [26a];
a first gate insulating layer [16a] provided between the second silicon carbide region [26a] and the first gate electrode [18a];
a second gate insulating layer [16b] provided between the second silicon carbide region [26a] and the second gate electrode [18b];
a first electrode [12] provided on the first surface side of the silicon carbide layer [10], and having a plurality of first portions [12x] provided between the first gate electrode [18a] and the second gate electrode [18b] and in contact with the third silicon carbide region [28a] and the fourth silicon carbide region [30a] and a plurality of second portions [12y] in contact with the first silicon carbide region [24]; and
a second electrode [14] provided on the second surface side of the silicon carbide layer [10], wherein
the first silicon carbide region [24] includes a first region [lower region of 10], and second, third, and fourth regions [upper regions of 10 directly contact region 26] provided between the first region [lower region of 10] and the second silicon carbide region [26a],
the second silicon carbide region [26a] includes a fifth region facing the first gate electrode [18a], a sixth region facing the second gate electrode [18b], and a seventh region provided between the fifth region and the sixth region,
the second region is provided between the first region and the fifth region,
the third region is provided between the first region and the sixth region, and
the fourth region is provided between the first region and the seventh region;
wherein the seventh region is provided between the third silicon carbide region [28a] and the fourth region.
PNG
media_image1.png
589
808
media_image1.png
Greyscale
Asaba et al. fails to disclose
a first conductivity type impurity concentration of the second region is higher than a first conductivity type impurity concentration of the first region,
a first conductivity type impurity concentration of the third region is higher than the first conductivity type impurity concentration of the first region.
Oota et al. discloses in Fig. 1, Fig. 6, column 4, lines 49-60, column 7, lines 59-67, column 8, lines 1-11
a first conductivity type impurity concentration of the second region [n-type region 26 underlying first gate] is higher than a first conductivity type impurity concentration of the first region [24][“An impurity concentration of the n-type impurities in the low resistance region 26 is higher than the impurity concentration of the n-type impurities in the drift region 24”],
a first conductivity type impurity concentration of the third region [n type region 26 between first and second gate] is higher than the first conductivity type impurity concentration of the first region [24][“An impurity concentration of the n-type impurities in the low resistance region 26 is higher than the impurity concentration of the n-type impurities in the drift region 24”]
PNG
media_image2.png
602
703
media_image2.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Oota et al. into the method of Asaba et al. to include wherein the first silicon carbide region includes a first conductivity type impurity concentration of the second region is higher than a first conductivity type impurity concentration of the first region, a first conductivity type impurity concentration of the third region is higher than the first conductivity type impurity concentration of the first region. The ordinary artisan would have been motivated to modify Asaba et al. in the above manner for the purpose of preventing the growth of the stacking fault in the silicon carbide layer and reliability can be improved [column 8, lines 1-11 of Oota et al.].
Asaba et al. and Oota et al. fails to disclose
wherein the first conductivity type impurity concentration of the fourth region is higher than the first conductivity type impurity concentration of the second region and the third region;
wherein the first conductivity type impurity concentration of the fourth region is 1.5 to 10 times the first conductivity type impurity concentration of the second region; and
the first conductivity type impurity concentration of the fourth region is 1.5 to 10 times the first conductivity type impurity concentration of the third region.
Okumura discloses in Fig. 1, Fig. 7A, paragraph [0066], [0069], [0072], [0078]
wherein the first conductivity type impurity concentration of the fourth region [17] is higher than the first conductivity type impurity concentration of the second region [5 right] and the third region [5];
wherein the first conductivity type impurity concentration of the fourth region [17] is 1.5 to 10 times the first conductivity type impurity concentration of the second region [5/5a]; and
the first conductivity type impurity concentration of the fourth region [17] is 1.5 to 10 times the first conductivity type impurity concentration of the third region [5/5a].
[paragraph [0066], “an n+-type region (first semiconductor region of the first conductivity type) 17 having a peak impurity concentration higher than the n-type high-concentration region 5”; paragraph [0069] “the impurity concentration of the n+-type region 17 may be in a range from 1×1017/cm3 to 1×1020/cm3”; paragraph [0078], “dose amount during ion implantation for forming the first n-type region 5a, for example, may be set so that the impurity concentration becomes about 1×1017/cm3”].
PNG
media_image3.png
439
444
media_image3.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Okumura into the method of Asaba et al. and Oota et al. to include wherein the first conductivity type impurity concentration of the fourth region is higher than the first conductivity type impurity concentration of the second region and the third region; wherein the first conductivity type impurity concentration of the fourth region is 1.5 to 10 times the first conductivity type impurity concentration of the second region; and the first conductivity type impurity concentration of the fourth region is 1.5 to 10 times the first conductivity type impurity concentration of the third region. The ordinary artisan would have been motivated to modify Asaba et al. and Oota et al. in the above manner for the purpose of enabling the position where electric field concentrates to be controlled [paragraph [0072] of Okumura].
In addition, Applicant has not provided any criticality of the claimed range. The ordinary artisan would have been motivated to modify Asaba et al., Oota et al. and Okumura to include the claimed range for at least the purpose of optimization and routine experimentation. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Asaba et al. fails to disclose
the seventh region having a shallower depth than a depth of the fifth region and a depth of the sixth region;
wherein the depth of the seventh region is one-half or less the depth of the fifth region; and
the depth of the seventh region is one-half or less the depth of the sixth region.
Kono et al. discloses in Fig. 5A, paragraph [0037], [0047]-[0052]
the seventh region [31a] having a shallower depth than a depth of the fifth region [31b left] and a depth of the sixth region [31b right];
wherein the depth of the seventh region [31a] is one-half or less the depth of the fifth region [31 left]; and
the depth of the seventh region [31a] is one-half or less the depth of the sixth region [31 right].
PNG
media_image4.png
431
448
media_image4.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Kono et al. into the method of Asaba et al. to include the seventh region having a shallower depth than a depth of the fifth region and a depth of the sixth region; wherein the depth of the seventh region is one-half or less the depth of the fifth region; and the depth of the seventh region is one-half or less the depth of the sixth region. The ordinary artisan would have been motivated to modify Asaba et al. in the above manner for the purpose of reducing the chip surface area, reducing conduction loss, reducing/ minimizing the forming of stacking faults and reliably suppressing leakage current in the semiconductor device [paragraph [0047]-[0052] of Kono et al.].
Regarding claims 13, 14 and 15, Asaba et al. discloses in Fig. 3-Fig. 5, Fig. 12-Fig. 14
a third gate electrode [18c] extending in the first direction and facing the second silicon carbide region [26a], wherein the third gate electrode [18c] is spaced from the second gate electrode [18b] in the second direction, so that the second gate electrode [18b] is between the first gate electrode [18a] and the third gate electrode [18c]; and
a third gate insulating layer [16c] provided between the second silicon carbide region [26a] and the third gate electrode [18c],
wherein the plurality of the first portions [12x] of the first electrode [12] and the plurality of the second portions [12y] of the first electrode [12] are arranged alternately in at least one of the first and second directions [Fig. 3, Fig. 12];
wherein the plurality of the first portions [12x] of the first electrode [12] and the plurality of the second portions [12y] of the first electrode [12] are arranged alternately in both the first and second directions [Fig. 12];
wherein the plurality of the first portions [12x] of the first electrode [12] and the plurality of the second portions [12y] of the first electrode [12] are arranged alternately in the first direction but not in the second direction [Fig. 3].
Regarding claim 16, Asaba et al. discloses in Fig. 4-Fig. 5, Fig. 13-Fig. 14
wherein the plurality of the first portions [12x] of the first electrode [12] extend into the first surface of the silicon carbide layer [10].
Claims 1, 4, 6-7, 9-15, 17, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yen et al. (US Pub. 20170250275) in view of Okumura (US Pub. 20200266294), Oota et al. (US Pat. 9887285) and Kono et al. (US Pub. 20150263158).
Regarding claims 1, 4, 6 and 11, Yen et al. discloses in Fig. 2A-2D, Fig. 4 a semiconductor device comprising:
a silicon carbide layer [20 and 30] including a first surface and a second surface on opposite sides of the silicon carbide layer,
the silicon carbide layer [20 and 30] including
a first silicon carbide region [20] of a first conductivity type [n type][paragraph [0024]],
a second silicon carbide region [32] of a second conductivity type [p type] provided between the first silicon carbide region [20] and the first surface [paragraph [0025]],
a third silicon carbide region [34] of the second conductivity type [p type] provided between the second silicon carbide region and the first surface and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the second silicon carbide region [paragraph [0025]], and
a fourth silicon carbide region [33] of the first conductivity type [ n type] provided between the second silicon carbide region [32] and the first surface [paragraph [0025]],
a first gate electrode [50] extending in a first direction [Y direction] parallel to the first surface and facing the second silicon carbide region [32];
a second gate electrode [50] extending in the first direction, spaced from the first gate electrode [50] in a second direction [X direction] parallel to the first surface and perpendicular to the first direction, and facing the second silicon carbide region [32];
a first gate insulating layer [40] provided between the second silicon carbide region [32] and the first gate electrode [50];
a second gate insulating layer [40] provided between the second silicon carbide region [32] and the second gate electrode [50];
a first electrode [1101] provided on the first surface side of the silicon carbide layer [20 and 30],
the first electrode including
a first portion provided between the first gate electrode [50] and the second gate electrode [50] and in contact with the third silicon carbide region [34] [Fig. 2C]; and
a second portion provided between the first gate electrode [50] and the second gate electrode [50], spaced from the first portion in the first direction [Y direction], and in contact with the first silicon carbide region [20][Fig. 2D], and
a second electrode [120] provided on the second surface side of the silicon carbide layer [20 and 30],
wherein the first silicon carbide region [20] includes a first region [lower region of 20], and second, third, and fourth regions [upper regions of 20 that directly contact region [32]] provided between the first region [lower region of 20] and the second silicon carbide region [32],
the second silicon carbide region [32] includes a fifth region facing the first gate electrode [50], a sixth region facing the second gate electrode [50], and a seventh region provided between the fifth region and the sixth region [Fig. 2C],
the second region is provided between the first region and the fifth region,
the third region is provided between the first region and the sixth region, and
the fourth region is provided between the first region and the seventh region;
wherein the seventh region is provided between the third silicon carbide region and the fourth region.
PNG
media_image5.png
473
682
media_image5.png
Greyscale
PNG
media_image6.png
545
733
media_image6.png
Greyscale
PNG
media_image7.png
474
658
media_image7.png
Greyscale
Yen et al. fails to disclose
a first conductivity type impurity concentration of the second region is higher than a first conductivity type impurity concentration of the first region,
a first conductivity type impurity concentration of the third region is higher than the first conductivity type impurity concentration of the first region,
the first portion in contact with the third silicon carbide region and the fourth silicon carbide region.
Oota et al. discloses in Fig. 1, Fig. 6, column 4, lines 49-60, column 7, lines 59-67, column 8, lines 1-11
a first conductivity type impurity concentration of the second region [n-type region 26 underlying first gate] is higher than a first conductivity type impurity concentration of the first region [24][“An impurity concentration of the n-type impurities in the low resistance region 26 is higher than the impurity concentration of the n-type impurities in the drift region 24”],
a first conductivity type impurity concentration of the third region [n type region 26 between first and second gate] is higher than the first conductivity type impurity concentration of the first region [24][“An impurity concentration of the n-type impurities in the low resistance region 26 is higher than the impurity concentration of the n-type impurities in the drift region 24”],
the first portion in contact with the third silicon carbide region [36] and the fourth silicon carbide region [30].
PNG
media_image2.png
602
703
media_image2.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Oota et al. into the method of Yen et al. to include a first conductivity type impurity concentration of the second region is higher than a first conductivity type impurity concentration of the first region, a first conductivity type impurity concentration of the third region is higher than the first conductivity type impurity concentration of the first region; the first portion in contact with the third silicon carbide region and the fourth silicon carbide region. The ordinary artisan would have been motivated to modify Yen et al. in the above manner for the purpose of preventing the growth of the stacking fault in the silicon carbide layer and reliability can be improved [column 8, lines 1-11 of Oota et al.]; and providing a source electrode having increased contact area with the third silicon carbide region and the fourth silicon carbide region to form reliable electrical connection.
Yen et al. and Oota et al. fails to disclose
wherein the first conductivity type impurity concentration of the fourth region is higher than the first conductivity type impurity concentration of the second region and the third region;
wherein the first conductivity type impurity concentration of the fourth region is 1.5 to 10 times the first conductivity type impurity concentration of the second region; and
the first conductivity type impurity concentration of the fourth region is 1.5 to 10 times the first conductivity type impurity concentration of the third region.
Okumura discloses in Fig. 1, Fig. 7A, paragraph [0066], [0069], [0072], [0078]
wherein the first conductivity type impurity concentration of the fourth region [17] is higher than the first conductivity type impurity concentration of the second region [5 right]; and
the first conductivity type impurity concentration of the fourth region [17] is higher than the first conductivity type impurity concentration of the third region [5];
wherein the first conductivity type impurity concentration of the fourth region [17] is 1.5 to 10 times the first conductivity type impurity concentration of the second region [5/5a]; and
the first conductivity type impurity concentration of the fourth region [17] is 1.5 to 10 times the first conductivity type impurity concentration of the third region [5/5a].
[paragraph [0066], “an n+-type region (first semiconductor region of the first conductivity type) 17 having a peak impurity concentration higher than the n-type high-concentration region 5”; paragraph [0069] “the impurity concentration of the n+-type region 17 may be in a range from 1×1017/cm3 to 1×1020/cm3”; paragraph [0078], “dose amount during ion implantation for forming the first n-type region 5a, for example, may be set so that the impurity concentration becomes about 1×1017/cm3”].
PNG
media_image3.png
439
444
media_image3.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Okumura into the method of Yen et al. and Oota et al. to include wherein the first conductivity type impurity concentration of the fourth region is higher than the first conductivity type impurity concentration of the second region and the third region; wherein the first conductivity type impurity concentration of the fourth region is 1.5 to 10 times the first conductivity type impurity concentration of the second region; and the first conductivity type impurity concentration of the fourth region is 1.5 to 10 times the first conductivity type impurity concentration of the third region. The ordinary artisan would have been motivated to modify Yen et al., and Oota et al. in the above manner for the purpose of enabling the position where electric field concentrates to be controlled [paragraph [0072] of Okumura].
In addition, Applicant has not provided any criticality of the claimed range. The ordinary artisan would have been motivated to modify Yen et al., Oota et al. and Okumura to include the claimed range for at least the purpose of optimization and routine experimentation. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Yen et al. fails to disclose
the seventh region having a shallower depth than a depth of the fifth region and a depth of the sixth region;
wherein the depth of the seventh region is one-half or less the depth of the fifth region; and
the depth of the seventh region is one-half or less the depth of the sixth region.
Kono et al. discloses in Fig. 5A, paragraph [0037], [0047]-[0052]
the seventh region [31a] having a shallower depth than a depth of the fifth region [31b left] and a depth of the sixth region [31b right];
wherein the depth of the seventh region [31a] is one-half or less the depth of the fifth region [31 left]; and
the depth of the seventh region [31a] is one-half or less the depth of the sixth region [31 right].
PNG
media_image4.png
431
448
media_image4.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Kono et al. into the method of Yen et al. to include the seventh region having a shallower depth than a depth of the fifth region and a depth of the sixth region; wherein the depth of the seventh region is one-half or less the depth of the fifth region; and the depth of the seventh region is one-half or less the depth of the sixth region. The ordinary artisan would have been motivated to modify Yen et al. in the above manner for the purpose of reducing the chip surface area, reducing conduction loss, reducing/ minimizing the forming of stacking faults and reliably suppressing leakage current in the semiconductor device [paragraph [0047]-[0052] of Kono et al.].
Regarding claim 7, Yen et al. discloses in Fig. 2A-2D, Fig. 4
a third gate electrode [50 right] extending in the first direction [Y direction], spaced from the second gate electrode [50 middle] in the second direction [X direction], so that the second gate electrode [50 middle] is between the first gate electrode [50 left] and the third gate electrode [50 right]; and
a third gate insulating layer [40 right],
wherein the silicon carbide layer [20 and 30] further includes
a fifth silicon carbide region [32 right] of the second conductivity type provided between the first silicon carbide region [20] and the first surface and separated from the second silicon carbide region [32 left] in the second direction [X direction][paragraph [0025]],
a sixth silicon carbide region [34 right] of the second conductivity type provided between the fifth silicon carbide region [32 right] and the first surface and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the fifth silicon carbide region [32 right][paragraph [0025]], and
a seventh silicon carbide region [33 right] of the first conductivity type provided between the fifth silicon carbide region [32 right] and the first surface [paragraph [0025]],
the second gate electrode [50 middle] faces the fifth silicon carbide region [32 right],
the second gate insulating layer [40 middle] is provided between the fifth silicon carbide region [32 right] and the second gate electrode [50 middle],
the third gate electrode [50 right] faces the fifth silicon carbide region [32],
the third gate insulating layer [40 right] is provided between the fifth silicon carbide region [32 right] and the third gate electrode [50 right], and
the first electrode [1101] further includes a third portion provided between the second gate electrode [50 middle] and the third gate electrode [50 right] and in contact with the sixth silicon carbide region [34].
PNG
media_image8.png
463
682
media_image8.png
Greyscale
Oota suggests in Fig. 1 the third portion of the first electrode [12] in contact with the sixth silicon carbide region [36 right] and the seventh silicon carbide region [30 right].
Consequently, the combination of Yen et al. and Oota discloses limitations of claim 7.
Regarding claim 9, Kono et al. discloses in Fig. 7B
wherein the third portion is aligned with the second portion in the second direction;
PNG
media_image9.png
421
537
media_image9.png
Greyscale
Regarding claim 10, Yen et al. discloses in Fig. 2C-2D
wherein the first surface is between the first gate electrode [50 left] and the second silicon carbide region [32 left], and between the second gate electrode [50 middle] and the second silicon carbide region [32 left].
Regarding claims 12, 19, and 20, Yen et al. discloses in Fig. 2A-2D, Fig. 4 a semiconductor device comprising:
a silicon carbide layer [20 and 30] including a first surface and a second surface on opposite sides of the silicon carbide layer, the silicon carbide layer [20 and 30] including
a first silicon carbide region [20] of a first conductivity type [n type][paragraph [0024]],
a second silicon carbide region [32] of a second conductivity type [p type] provided between the first silicon carbide region [20] and the first surface [paragraph [0025]],
a third silicon carbide region [34] of the second conductivity type [p type] provided between the second silicon carbide region and the first surface and having a second conductivity type impurity concentration higher than a second conductivity type impurity concentration of the second silicon carbide region [paragraph [0025]], and
a fourth silicon carbide region [33] of the first conductivity type [ n type] provided between the second silicon carbide region [32] and the first surface [paragraph [0025]],
a first gate electrode [50] extending in a first direction [Y direction] parallel to the first surface and facing the second silicon carbide region [32];
a second gate electrode [50] extending in the first direction, spaced from the first gate electrode [50] in a second direction [X direction] parallel to the first surface and perpendicular to the first direction, and facing the second silicon carbide region [32];
a first gate insulating layer [40] provided between the second silicon carbide region [32] and the first gate electrode [50];
a second gate insulating layer [40] provided between the second silicon carbide region [32] and the second gate electrode [50];
a first electrode [1101] provided on the first surface side of the silicon carbide layer [20 and 30], and having a plurality of first portions provided between the first gate electrode [50] and the second gate electrode [50] and in contact with the third silicon carbide region [34] and a plurality of second portions in contact with the first silicon carbide region [20][Fig. 2C, Fig. 2D]; and
a second electrode [120] provided on the second surface side of the silicon carbide layer [20 and 30], wherein
wherein the first silicon carbide region [20] includes a first region [lower region of 20], and second, third, and fourth regions [upper regions of 20 that directly contact region [32]] provided between the first region [lower region of 20] and the second silicon carbide region [32],
the second silicon carbide region [32] includes a fifth region facing the first gate electrode [50], a sixth region facing the second gate electrode [50], and a seventh region provided between the fifth region and the sixth region [Fig. 2C],
the second region is provided between the first region and the fifth region,
the third region is provided between the first region and the sixth region, and
the fourth region is provided between the first region and the seventh region.
PNG
media_image5.png
473
682
media_image5.png
Greyscale
PNG
media_image6.png
545
733
media_image6.png
Greyscale
PNG
media_image7.png
474
658
media_image7.png
Greyscale
Yen et al. fails to disclose
a first conductivity type impurity concentration of the second region is higher than a first conductivity type impurity concentration of the first region,
a first conductivity type impurity concentration of the third region is higher than the first conductivity type impurity concentration of the first region,
the first portion in contact with the third silicon carbide region and the fourth silicon carbide region.
Oota et al. discloses in Fig. 1, Fig. 6, column 4, lines 49-60, column 7, lines 59-67, column 8, lines 1-11
a first conductivity type impurity concentration of the second region [n-type region 26 underlying first gate] is higher than a first conductivity type impurity concentration of the first region [24][“An impurity concentration of the n-type impurities in the low resistance region 26 is higher than the impurity concentration of the n-type impurities in the drift region 24”],
a first conductivity type impurity concentration of the third region [n type region 26 between first and second gate] is higher than the first conductivity type impurity concentration of the first region [24][“An impurity concentration of the n-type impurities in the low resistance region 26 is higher than the impurity concentration of the n-type impurities in the drift region 24”],
the first portion in contact with the third silicon carbide region [36] and the fourth silicon carbide region [30].
PNG
media_image2.png
602
703
media_image2.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Oota et al. into the method of Yen et al. to include a first conductivity type impurity concentration of the second region is higher than a first conductivity type impurity concentration of the first region, a first conductivity type impurity concentration of the third region is higher than the first conductivity type impurity concentration of the first region; and the first portion in contact with the third silicon carbide region and the fourth silicon carbide region. The ordinary artisan would have been motivated to modify Yen et al. in the above manner for the purpose of preventing the growth of the stacking fault in the silicon carbide layer and reliability can be improved [column 8, lines 1-11 of Oota et al.]; and providing a source electrode having increased contact area with the third silicon carbide region and the fourth silicon carbide region to form reliable electrical connection.
Yen et al., and Oota et al. fails to disclose
wherein the first conductivity type impurity concentration of the fourth region is higher than the first conductivity type impurity concentration of the second region and the third region;
wherein the first conductivity type impurity concentration of the fourth region is 1.5 to 10 times the first conductivity type impurity concentration of the second region; and
the first conductivity type impurity concentration of the fourth region is 1.5 to 10 times the first conductivity type impurity concentration of the third region.
Okumura discloses in Fig. 1, Fig. 7A, paragraph [0066], [0069], [0072], [0078]
wherein the first conductivity type impurity concentration of the fourth region [17] is higher than the first conductivity type impurity concentration of the second region [5 right]; and
the first conductivity type impurity concentration of the fourth region [17] is higher than the first conductivity type impurity concentration of the third region [5];
wherein the first conductivity type impurity concentration of the fourth region [17] is 1.5 to 10 times the first conductivity type impurity concentration of the second region [5/5a]; and
the first conductivity type impurity concentration of the fourth region [17] is 1.5 to 10 times the first conductivity type impurity concentration of the third region [5/5a].
[paragraph [0066], “an n+-type region (first semiconductor region of the first conductivity type) 17 having a peak impurity concentration higher than the n-type high-concentration region 5”; paragraph [0069] “the impurity concentration of the n+-type region 17 may be in a range from 1×1017/cm3 to 1×1020/cm3”; paragraph [0078], “dose amount during ion implantation for forming the first n-type region 5a, for example, may be set so that the impurity concentration becomes about 1×1017/cm3”].
PNG
media_image3.png
439
444
media_image3.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Okumura into the method of Yen et al., and Oota et al. to include wherein the first conductivity type impurity concentration of the fourth region is higher than the first conductivity type impurity concentration of the second region and the third region; wherein the first conductivity type impurity concentration of the fourth region is 1.5 to 10 times the first conductivity type impurity concentration of the second region; and the first conductivity type impurity concentration of the fourth region is 1.5 to 10 times the first conductivity type impurity concentration of the third region. The ordinary artisan would have been motivated to modify Yen et al., and Oota et al. in the above manner for the purpose of enabling the position where electric field concentrates to be controlled [paragraph [0072] of Okumura].
In addition, Applicant has not provided any criticality of the claimed range. The ordinary artisan would have been motivated to modify Yen et al., Oota et al. and Okumura to include the claimed range for at least the purpose of optimization and routine experimentation. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
Yen et al. fails to disclose
the seventh region having a shallower depth than a depth of the fifth region and a depth of the sixth region;
wherein the depth of the seventh region is one-half or less the depth of the fifth region; and
the depth of the seventh region is one-half or less the depth of the sixth region.
Kono et al. discloses in Fig. 5A, paragraph [0037], [0047]-[0052]
the seventh region [31a] having a shallower depth than a depth of the fifth region [31b left] and a depth of the sixth region [31b right];
wherein the depth of the seventh region [31a] is one-half or less the depth of the fifth region [31 left]; and
the depth of the seventh region [31a] is one-half or less the depth of the sixth region [31 right].
PNG
media_image4.png
431
448
media_image4.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Kono et al. into the method of Yen et al. to include the seventh region having a shallower depth than a depth of the fifth region and a depth of the sixth region; wherein the depth of the seventh region is one-half or less the depth of the fifth region; and the depth of the seventh region is one-half or less the depth of the sixth region. The ordinary artisan would have been motivated to modify Yen et al. in the above manner for the purpose of reducing the chip surface area, reducing conduction loss, reducing/ minimizing the forming of stacking faults and reliably suppressing leakage current in the semiconductor device [paragraph [0047]-[0052] of Kono et al.].
Regarding claims 13 and 15, Yen et al. discloses in Fig. 2A-2D, Fig. 4
a third gate electrode [50 right] extending in the first direction [Y direction] and facing the second silicon carbide region [32], wherein the third gate electrode [50 right] is spaced from the second gate electrode [50 middle] in the second direction [X direction], so that the second gate electrode [50 middle] is between the first gate electrode [50 left] and the third gate electrode [50 right]; and
a third gate insulating layer [40 right] provided between the second silicon carbide region [32] and the third gate electrode [50 right],
wherein the plurality of the first portions [70] of the first electrode and the plurality of the second portions [80] of the first electrode are arranged alternately in at least one of the first and second directions [Fig. 2B, Fig. 4];
wherein the plurality of the first portions [70] of the first electrode and the plurality of the second portions [80] of the first electrode are arranged alternately in the first direction but not in the second direction [Fig. 2B].
PNG
media_image8.png
463
682
media_image8.png
Greyscale
Regarding claim 14, Kono et al. suggests in Fig. 7B
wherein the plurality of the first portions of the first electrode and the plurality of the second portions of the first electrode are arranged alternately in both the first and second directions.
PNG
media_image10.png
421
537
media_image10.png
Greyscale
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Kono et al. into the method of Yen et al. to include wherein the plurality of the first portions of the first electrode and the plurality of the second portions of the first electrode are arranged alternately in both the first and second directions. The ordinary artisan would have been motivated to modify Yen et al. in the above manner for the purpose of providing suitable alternative arrangement of the first and second portions of the first electrode.
Claims 5 and 8 rejected under 35 U.S.C. 103 as being unpatentable over Yen et al. (US Pub. 20170250275) in view of Okumura (US Pub. 20200266294) and Oota et al. (US Pat. 9887285) and Kono et al. (US Pub. 20150263158) as applied to claim 1 and 7 above and further in view of Furukawa (Us Pub. 20190088775).
Regarding claim 5, Yen et al. fails to disclose
wherein the depth of the fifth region is 1.5 µm or more and 2 µm or less, and the depth of the sixth region is 1.5 µm or more and 2 µm or less.
However, Applicant has not provided any criticality of the claimed range. The ordinary artisan would have been motivated to modify Yen et al. to include wherein the depth of the fifth region is 1.5 µm or more, and the depth of the sixth region is 1.5 µm or more for at least the purpose of optimization and routine experimentation to provide sufficient depths of the fifth and sixth regions for their intended operation. The claimed ranges are merely optimizations, and as such are not patentable over the prior art. "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). "The normal desire of scientists or artisans to improve upon what is already generally known provides the motivation to determine where in a disclosed set of percentage ranges is the optimum combination of percentages." Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382.
For further support, Furukawa is cited.
Furukawa discloses in Fig. 1, paragraph [0019], [0021]
wherein the depth of the fifth region [30 left] is 1.5 µm or more, and the depth of the sixth region [30 right] is 1.5 µm or more.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Furukawa into the method of Yen et al. to include wherein the depth of the fifth region is 1.5 µm or more, and the depth of the sixth region is 1.5 µm or more. The ordinary artisan would have been motivated to modify Yen et al. in the above manner for the purpose of providing sufficient depths of the fifth and sixth regions.
Regarding claim 8, Yen et al. and Oota et al. fails to disclose
wherein a distance in the second direction between the fifth region and the sixth region is larger than a distance in the second direction between the second silicon carbide region and the fifth silicon carbide region.
However, one of ordinary skill in the art would have recognized the finite number of predictable solutions for a distance in the second direction between the fifth region and the sixth region with respect to a distance in the second direction between the second silicon carbide region and the fifth silicon carbide region: a distance in the second direction between the fifth region and the sixth region is smaller than/greater than/equal to a distance in the second direction between the second silicon carbide region and the fifth silicon carbide region. Absent unexpected results, it would have been obvious to try a distance in the second direction between the fifth region and the sixth region is greater than a distance in the second direction between the second silicon carbide region and the fifth silicon carbide region to achieve desired device performance.
For further support, Furukawa is cited.
Furukawa discloses in Fig. 1
wherein a distance in the second direction between the fifth region and the sixth region is larger than a distance in the second direction between the second silicon carbide region and the fifth silicon carbide region.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Furukawa into the method of Yen et al. and Oota et al. to include wherein a distance in the second direction between the fifth region and the sixth region is larger than a distance in the second direction between the second silicon carbide region and the fifth silicon carbide region. The ordinary artisan would have been motivated to modify Yen et al. and Oota et al. in the above manner for the purpose of providing suitable distance in the second direction between the fifth region and the sixth region with respect to a distance in the second direction between the second silicon carbide region and the fifth silicon carbide region.
Response to Arguments
Applicant’s arguments with respect to claims 1, 4-16, 19-20 have been considered but are moot because the new ground of rejection.
In addition, Applicant's arguments filed 03/23/2026 have been fully considered but they are not persuasive because of the following reasons:
In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Further, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). In this case, Kono is cited to teach the depth of the seventh region with respect to a depth of the fifth region and a depth of the sixth region for the purpose of reducing the chip surface area, reducing conduction loss, reducing/ minimizing the forming of stacking faults and reliably suppressing leakage current in the semiconductor device. Oota et al. is cited to teach a first conductivity type impurity concentration of the second region and the third region with respect to a first conductivity type impurity concentration of the first region for the purpose of preventing the growth of the stacking fault in the silicon carbide layer and reliability can be improved. Okumura is cited to teach a first conductivity type impurity concentration of the fourth region with respect to a first conductivity type impurity concentration of the second region and the third region for the purpose of enabling the position where electric field concentrates to be controlled.
Per MPEP 2131: The elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required. In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990).
It is noted that claim 1 recites “the first silicon carbide region includes a first region, and second, third, and fourth regions.” Therefore, Applicant explicitly claims that a continuous region can includes multiple regions defined at different locations. Thus, even though Oota discloses a continuous low-resistance region provided between the source electrode and the drift region, Oota discloses a fourth region provided between a first region and a seventh region and having a higher impurity concentration than the second and third regions beneath deeper body portions.
PNG
media_image2.png
602
703
media_image2.png
Greyscale
Overall, Applicant’s arguments are not persuasive. The claims stand rejected and the Action is made FINAL.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT D HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SOPHIA T NGUYEN/ Primary Examiner, Art Unit 2893
Prosecution Insights