DETAILED ACTION
This action is responsive to the pending claims, 1-22, received 19 February 2026 and the interview held 19 February 2026. Claims 2-3 are canceled. Accordingly, the detailed action of claims 1, 3-22 is as follows:
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The 35 U.S.C. 112(f) interpretation presented in the previous office action has been withdrawn in view of applicant’s amendments. (Remarks pg 11)
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 5 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 5 recites “configuring the internal loopback port as an untagged VLAN member”, however, the examiner is unable to find support for said feature. After careful review of the specification, the specification supports configuring the internal loopback port as a VLAN member (Specification [0024]). The specifics of the membership, tagged or untagged, are not positively recited.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 18 rejected under 35 U.S.C. 103 as being unpatentable over Pappu (US 20180095844 A1, hereafter referred to as Pappu) in view of Ameling et al (US 20230115762 A1, hereafter referred to as Ameling).
Regarding claim 18, Pappu teaches one or more non-transitory media having computer-readable instructions for controlling a network device to perform a method encoded thereon (Pappu [0070-0071 and 0077-0078]), the method comprising:
writing a test pattern of bits to one or more fields of at least one test packet (Pappu [0031, 0059] teaches generating test packets based upon a IO protocol, wherein the packets are subject to an bit error determination [0021, 0022]);
injecting the at least one test packet into a packet processing system of a network device (Pappu [0032, 0060] discloses providing test packets to the transaction layer);
causing the at least one test packet to loop through ingress and egress portions of the packet processing system (Pappu [0018] teaches changing the data path to a test path including loopbacks to return the test packet [0021, 0022, 0061]);
trapping the at least one test packet (Pappu [0061, 0035] teaches receiving the returned test packet); and
determining whether the test pattern of the at least one test packet has been altered (Pappu [0035] teaches comparing the returned packet to check for data correctness and errors).
However, Pappu does not explicitly teach loop multiple times, monitoring one or more criteria corresponding to a packet traffic flow rate of the network device; and responsive to at least one of the (a) the one or more criteria or (b) user input regarding a target bandwidth or a target packet traffic flow rate for the network device, controlling a number of test packets simultaneously looping through the ingress and egress portions of the packet processing system.
Ameling, in an analogous art, teaches causing the at least one test packet to loop multiple times (Ameling [0126] teaches the test packet loop for a predetermined number of traversals or loops or amount of time);
monitoring one or more criteria corresponding to a packet traffic flow rate of the network device (Ameling [0101] teaches the number of test packets to be recycled is determined based on current observable performance metrics including monitored traffic rates or loads); and
responsive to at least one of the (a) the one or more criteria or (b) user input regarding a target bandwidth or a target packet traffic flow rate for the network device (Ameling [0101] teaches the number of test packets to be recycled is determined based on current observable performance metrics including monitored traffic rates or loads. Additionally, Ameling [0037] teaches the user providing test traffic generation requirements and test result performance metrics, wherein the observable performance metrics include queue depths or traffic rates or loads [0101]), controlling a number of test packets simultaneously looping through the ingress and egress portions of the packet processing system (Ameling [0101] teaches the number of test packets to be recycled is determined based on current observable performance metrics including monitored traffic rates or loads).
It would have been obvious for a person having ordinary skill in the art, before the effective filing date of the claimed invention, to modify Pappu in view of Ameling in order to configure the at least one test packet which loops through ingress and egress portions of the packet processing system, as taught by Pappu, to do so multiple times, as taught by Ameling and monitor one or more criteria corresponding to a packet traffic flow rate of the network device; and responsive to at least one of the (a) the one or more criteria or (b) user input regarding a target bandwidth or a target packet traffic flow rate for the network device, controlling a number of test packets simultaneously looping through the ingress and egress portions of the packet processing system, as taught by Ameling.
One of ordinary skill in the art would have been motivated in order to reduce resources consumed (Ameling [0027]).
Claims 1, 4-5, 7, 9-12, 19 rejected under 35 U.S.C. 103 as being unpatentable over Pappu (US 20180095844 A1, hereafter referred to as Pappu) in view of Ameling et al (US 20230115762 A1, hereafter referred to as Ameling) in view of Suzuki (JP2006067054 A, hereafter referred to as Suzuki).
Regarding claim 1, Pappu teaches a method, comprising:
writing a test pattern of bits to one or more fields of at least one test packet (Pappu [0031, 0059] teaches generating test packets based upon a IO protocol, wherein the packets are subject to an bit error determination [0021, 0022]);
injecting the at least one test packet into a packet processing system of a network device (Pappu [0032, 0060] discloses providing test packets to the transaction layer);
causing the at least one test packet to loop through ingress and egress portions of the packet processing system (Pappu [0018] teaches changing the data path to a test path including loopbacks to return the test packet [0021, 0022, 0061]);
trapping the at least one test packet (Pappu [0061, 0035] teaches receiving the returned test packet); and
determining whether the test pattern of the at least one test packet has been altered (Pappu [0035] teaches comparing the returned packet to check for data correctness and errors).
However, Pappu does not explicitly teach loop multiple times, wherein causing the at least one test packet to loop multiple times involves causing the packet processing system to send the at least one test packet to an internal loopback port and wherein causing the at least one test packet to be sent to the internal loopback port involves associating a previously-unused virtual local area network (VLAN) identification number (ID) with the internal loopback port.
Ameling, in an analogous art, teaches causing the at least one test packet to loop multiple times (Ameling [0126] teaches the test packet loop for a predetermined number of traversals or loops or amount of time).
It would have been obvious for a person having ordinary skill in the art, before the effective filing date of the claimed invention, to modify Pappu in view of Ameling in order to configure the at least one test packet which loops through ingress and egress portions of the packet processing system, as taught by Pappu, to do so multiple times, as taught by Ameling.
One of ordinary skill in the art would have been motivated in order to reduce resources consumed (Ameling [0027]).
However, Pappu-Ameling does not explicitly teach wherein causing the at least one test packet to loop multiple times involves causing the packet processing system to send the at least one test packet to an internal loopback port and wherein causing the at least one test packet to be sent to the internal loopback port involves associating a previously-unused virtual local area network (VLAN) identification number (ID) with the internal loopback port.
Suzuki, in an analogous art, teaches writing a test pattern of bits to one or more fields of at least one packet (Suzuki [0079 and 0115] teaches generating a MAC frame encapsulating a loop detection OAM);
injecting the at least one test packet into a packet processing system of a network device (Suzuki [0118] teaches transmitting a frame including the loop detection OAM from the subscriber port corresponding to a service VLAN identifier); wherein causing the at least one test packet to loop involves causing the packet processing system to send the at least one test packet to an internal loopback port (Suzuki [0046, 0115 and 0118] teaches generating and transmitting a frame with a loop detection OAM, wherein the frame encapsulating the loop detection OAM [0086] is addressed to the address of the subscriber port) and wherein causing the at least one test packet to be sent to the internal loopback port involves associating a previously-unused virtual local area network (VLAN) identification number (ID) with the internal loopback port (Suzuki [0051, 0059] teaches a relationship in which a single service VLAN identifier is predetermined for a subscriber port such that the value of a VLAN identifier is uniquely determined based on the port such that the Service VLAN is predetermined for each subscriber port).
It would have been obvious for a person having ordinary skill in the art, before the effective filing date of the claimed invention, to modify Pappu-Ameling in view of Suzuki in order to configure the at least one test packet looping multiple times through the ingress and egress portions of the packet processing system, as taught by Pappu-Ameling, to involve sending the test packet to an internal loopback port and wherein causing the at least one test packet to be sent to the internal loopback port involves associating a previously-unused virtual local area network identification number with the internal loopback port, as taught by Suzuki.
One of ordinary skill in the art would have been motivated in order to detect a loop wasting resources at a subscriber’s site and provider network, resulting in a reduction in the ability to forward frames to other subscribers (Suzuki [0013]) thereby protecting other subscribers (Suzuki [0058]) while avoiding erroneously detecting the occurrence of a loop (Suzuki [0048]).
Regarding claim 4, Pappu-Ameling-Suzuki teaches the limitations of claim 1, as rejected above.
Additionally, Pappu-Ameling-Suzuki teaches the method further comprising configuring the internal loopback port as a VLAN trunk port (Suzuki [0111] discloses the port, at which the frame is received, is a subscriber port or trunk port).
Regarding claim 5, Pappu-Ameling-Suzuki teaches the limitations of claim 1, as rejected above.
Additionally, Pappu-Ameling-Suzuki teaches the method further comprising configuring the internal loopback port as an untagged VLAN member of the previously-unused VLAN ID (Suzuki [0051, 0059] teaches a relationship in which a single service VLAN identifier is predetermined for a subscriber port).
Regarding claim 7, Pappu-Ameling-Suzuki teaches the limitations of claim 1, as rejected above.
Additionally, Pappu-Ameling-Suzuki teaches the method wherein causing the at least one test packet to be sent to the internal loopback port involves the at least one test packet being injected with metadata that causes the at least one test packet to egress the internal loopback port (Suzuki [0118] teaches generating a MAC frame which includes an encapsulated loop detection OAM and service VLAN identifier [0090] and transmitting it from the subscriber port corresponding to the service VLAN identifier [0118]).
Regarding claim 9, Pappu-Ameling-Suzuki teaches the limitations of claim 1, as rejected above.
Additionally, Pappu-Ameling-Suzuki teaches the method further comprising controlling a number of test packets simultaneously looping through the ingress and egress portions of the packet processing system (Ameling [0096] teaches a user-specified test plan to determine whether test packets are to be recycled [0101]. Additionally, [0042] teaches obtained performance metrics used to dynamically adjust an amount of test traffic).
Regarding claim 10, Pappu-Ameling-Suzuki teaches the limitations of claim 9, as rejected above.
Additionally, Pappu-Ameling-Suzuki teaches the method further comprising receiving user input (Ameling [0096] teaches a user-specified test plan), wherein controlling the number of test packets simultaneously looping through the ingress and egress portions of the packet processing system is responsive to the user input (Ameling [0096] teaches a user-specified test plan to determine whether test packets are to be recycled [0101]).
Regarding claim 11, Pappu-Ameling-Suzuki teaches the limitations of claim 10, as rejected above.
Additionally, Pappu-Ameling-Suzuki teaches the method wherein the user input includes input regarding a target bandwidth or a target packet traffic flow rate for the network device (Ameling [0037] teaches the user providing test traffic generation requirements and test result performance metrics, wherein the observable performance metrics include queue depths or traffic rates or loads [0101]).
Regarding claim 12, Pappu-Ameling-Suzuki teaches the limitations of claim 9, as rejected above.
Additionally, Pappu-Ameling-Suzuki teaches the method further comprising monitoring one or more criteria corresponding to a packet traffic flow rate of the network device, wherein controlling the number of test packets simultaneously looping through the ingress and egress portions of the packet processing system is responsive to the one or more criteria (Ameling [0101] teaches the number of test packets to be recycled is determined based on current observable performance metrics including monitored traffic rates or loads).
Regarding claim 19, Pappu-Ameling teaches the limitations of claim 18, as rejected above.
However, Pappu-Ameling does not explicitly teach the one or more non-transitory media wherein causing the at least one test packet to loop multiple times involves causing the packet processing system to send the at least one test packet to an internal loopback port.
Suzuki, in an analogous art, teaches the one or more non-transitory media wherein causing the at least one test packet to loop multiple times involves causing the packet processing system to send the at least one test packet to an internal loopback port (Suzuki [0046, 0115 and 0118] teaches generating and transmitting a frame with a loop detection OAM, wherein the frame encapsulating the loop detection OAM [0086] is addressed to the address of the subscriber port).
It would have been obvious for a person having ordinary skill in the art, before the effective filing date of the claimed invention, to modify Pappu-Ameling in view of Suzuki in order to configure the at least one test packet looping multiple times through the ingress and egress portions of the packet processing system, as taught by Pappu-Ameling, to involve sending the test packet to an internal loopback port, as taught by Suzuki.
One of ordinary skill in the art would have been motivated in order to detect a loop wasting resources at a subscriber’s site and provider network, resulting in a reduction in the ability to forward frames to other subscribers (Suzuki [0013]) thereby protecting other subscribers (Suzuki [0058]) while avoiding erroneously detecting the occurrence of a loop (Suzuki [0048]).
Allowable Subject Matter
Claim 6, 8, 16, 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 13-17, 21-22 allowed.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jiang et al (EP 1392020 B1);
Iwamatsu (JP 2007142501 A);
Sommers (US 20220116304 A1);
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEAN TOKUTA whose telephone number is (571)272-5145. The examiner can normally be reached M-TH 630-430.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brian Gillis can be reached at 5712727952. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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SHEAN TOKUTA
Primary Examiner
Art Unit 2446
/SHEAN TOKUTA/Primary Examiner, Art Unit 2446