DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to an application filed on 09/01/2023.
Applicant’s election without traverse of Species I in the reply filed on 11/24/2025 is acknowledged.
Claims 1-15 are pending for examination.
Claim Objections
Claim 2 recites the limitation "a corresponding phase" in line 7. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Murata et al. (US 2013/0033209 A1 and Murata hereinafter).
As to Claim 1, Murata in its teachings as shown in Fig.1-6 as best illustrated by Fig.1 disclose a motor control circuit (see [Abstract]) comprising:
an n-phase inverter (1) that controls a motor (4) of n-phases (three phases – U, V, W);
a current detection circuit (Rs via 10, 20) that detects a motor current flowing through the motor of the n-phases (see [0027]); and
a current control circuit (3) that controls the inverter for each of a control cycle based on a command current and the motor current detected by the current detection circuit (The control part 3 calculates a detected value of the motor current based on the outputs of the first current detection circuit 10 and the second current detection circuit 20, calculates a target value of a current to be allowed to flow through the motor and generates a command value for allowing the motor current of the target value to flow through the motor 4- see also [0031]) wherein
the inverter (1) includes transistor pairs of the n-phases provided for each phase of the motor (Q1, Q4 of U-phase; Q2, Q5 of V-phase; Q3, Q6 of W-phase of the motor 4), and
the current control circuit stops (see [0057]), for each of the control cycle, a switching operation in at least one transistor pair of the transistor pairs of the n-phases (the control part 3 calculates a command value and outputs this command value to the PWM circuit 2 and generates six kinds of PWM signals having duties in accordance with the command value from the control part 3 to make the switching elements Q1 to Q6 perform on/off operations with PWM signals in order for the current to flow through the motor 4- see [0032] and also the flowchart of Fig.4, S1-S12).
As to Claim 2, Murata disclose the motor control circuit according to claim 1, wherein
each of the transistor pairs (Q1-Q6) of the n-phases includes:
a first transistor (Q1) that switches whether or not to cause the motor current to flow from a first reference voltage node (a node between an upper arm A1 and A4 connected to the U-PHASE of the inverter 1) to a corresponding phase (U-PHASE) of the motor; and
a second transistor (Q4) that switches whether or not to cause the motor current to flow from a corresponding phase (U-PHASE) of the motor to a second reference voltage node (a ground voltage node of the U-PHASE of the inverter 1 connected to the current detector Rs), and
the current control circuit (3) continuously turns off, for each of the control cycle, the first transistor in at least one transistor pair of the transistor pairs of the n-phases during the control cycle (based on the control signal of the control circuit 3 via PWM circuit 2 one transistor (Q1 or Q4) is always turned off to avoid short circuit during commutation in order for the current to flow to the motor – see also [0032]).
As to Claim 3, Murata disclose the motor control circuit according to claim 2, wherein
the current control circuit sequentially switches, for each of the control cycle, a type of the transistor pair including the first transistor that is continuously turned off during the control cycle (see [0032]).
As to Claim 4, Murata disclose the motor control circuit according to claim 2, wherein
in each of the transistor pairs of the n-phases, the current control circuit turns on, for each of the control cycle, one of the first transistor and the second transistor and turns off another based on the command current and the motor current detected by the current detection circuit (commutation – see also [0032]).
As to Claim 5, Murata disclose the motor control circuit according to claim 2, wherein
the current control circuit (3) includes:
a comparator (OP1, OP2) that outputs, for each of the n-phases, a signal indicating whether or not the command current is larger than the motor current detected by the current detection circuit; and
a control signal generator (output of 10 and 20) that generates a control signal for turning on one of the first transistor and the second transistor and turning off another based on an output signal of the comparator in each of the transistor pairs of the n-phases (see the flowchart of Fig.4, S1-S12 and also [0041] – [0058]).
As to Claim 6, Murata disclose the motor control circuit according to claim 5, wherein
in each of the transistor pairs of the n-phases, for each of the control cycle, the current control circuit turns on the first transistor and causes the motor current to flow from the first reference voltage node to the corresponding phase of the motor via the first transistor in a case where the comparator outputs a signal indicating that the command current is larger than the motor current, and turns on the second transistor and causes the motor current to flow from the corresponding phase of the motor to the second reference voltage node via the second transistor in a case where the comparator outputs a signal indicating that the command current is less than or equal to the motor current (see the flowchart of Fig.4, S1-S12 and also [0041] – [0058]).
As to Claim 7, Murata disclose the motor control circuit according to claim 6,
wherein in a case where the comparator outputs a signal indicating that the command current is less than or equal to the motor current over a plurality of the consecutive control cycles, the current control circuit turns off the first transistor and turns on the second transistor continuously during the plurality of consecutive control cycles in each of the transistor pairs of the n-phases (see the flowchart of Fig.4, S1-S12 and also [0041] – [0058]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 8, 9 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Murata in view of Tatewaki (US 2020/0091854 A1).
As to Claim 8, Murata disclose the motor control circuit according to claim 2, however, it doesn’t explicitly disclose:
the current control circuit detects a difference between the command current and the motor current detected by the current detection circuit for each of the n-phases, and turns on one of the first transistor and the second transistor and turns off another within a period of a time length corresponding to the difference for each of the control cycle
Nonethless, Tatewaki in its teachings as shown in Fig.1-11 disclose at timing t3 in FIG. 3, the HiSide-FET 1 is controlled to be in the energized state (ON state) and the LoSide-FET 2 is controlled to be in the non-energized state (OFF state), and a positive current denoted by a symbol A in FIG. 2 flows from the FET 1 to the U phase. Further, at timings t1 and t5, the FET 2 is controlled to be ON and the FET 1 is controlled to be OFF, and a positive current denoted by a symbol B in FIG. 2 flows from the FET 2 toward the U phase (see [0043] - [0048] and see also Fig.3 and Fig.5)
Therefore, it would have been an obvious modification before the effective filing date of the instant application for the control circuit to turn on one of the first transistor and the second transistor and turns off another within a period of a time length corresponding to the difference for each of the control cycle as thought by Tatewaki within the teachings of Murata to achieve precise control over the motor's torque, speed, and position while ensuring safe, efficient, and stable operation.
As to Claim 9, Murata in view of Tatewaki disclose the motor control circuit according to claim 8, the current control circuit turns on, for each of the control cycle, the first transistor for a period proportional to the difference in each of the transistor pairs of the n-phases (Tatewaki: see [0043] - [0048] and also Fig.3 and Fig.5).
As to Claim 12, Murata disclose the motor control circuit according to claim 2, however, it doesn’t explicitly disclose:
the current control circuit turns on, for each of the control cycle, all of the second transistors in the transistor pairs of the n-phases in a partial period of the control cycle, and
the current detection circuit detects the motor current within the partial period.
Nonethless, Tatewaki in its teachings as shown in Fig.1-11 as best illustrated by Fig.2-5 disclose the current control circuit turns on (COMMAND DUTY), for each of the control cycle (1 cycle), all of the second transistors in the transistor pairs (FET 1, FET 2) of the n-phases in a partial period (t2,t4) of the control cycle, and the current detection circuit detects the motor current within the partial period (see [0043] - [0048] and also Fig.3 and Fig.5)
Therefore, it would have been an obvious modification before the effective filing date of the instant application for the control circuit to turn on for each of the control cycle and the current detection circuit to detect the motor current within a partial period as thought by Tatewaki within the teachings of Murata to allow accurate feedback for smooth torque/speed control by ensuring all phases momentarily connect for measurement and optimizing efficiency across the entire control cycle.
As to Claim 13, Murata in view of Tatewaki disclose the motor control circuit according to claim 12, wherein
the control cycle includes a first period (t1) and a second period (t2-t3) following the first period, and
in each of the transistor pairs of the n-phases, for each of the control cycle, the current control circuit turns on one of the first transistor and the second transistor and turns off another in the first period based on the command current and the motor current detected by the current detection circuit, and turns on all of the second transistors in the transistor pairs of the n-phases in the second period (Tatewaki: see [0043] - [0048] and also Fig.3 and Fig.5).
As to Claim 14, Murata in view of Tatewaki disclose the motor control circuit according to claim 13, wherein
the current detection circuit detects the motor current at a timing when a current flowing from the corresponding phase of the motor to the second reference voltage node via the second transistors is stable within the second period (Tatewaki: see [0043] - [0048] and also Fig.3 and Fig.5).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Murata in view of Suzuki et al. (US 2018/0167004 A1).
As to Claim 15, Murata disclose the motor control circuit according to claim 1, however, it doesn’t explicitly disclose:
a rotation speed detector that detects a rotation speed of the motor; and
a command current generator that generates the command current based on a command speed and the rotation speed detected by the rotation speed detector
Nonethless, Suzuki in its teachings as shown in Fig.1-13 disclose that the differential calculator 55 differentiates the rotational angle θ detected by rotational angle sensor 45 of the motor 80 in each motor control cycle to calculate the motor angular velocity ω and the differential calculator 55 further differentiates the motor angular velocity ω to calculate an angular acceleration ωdot and outputs the motor angular acceleration ωdot to the fundamental voltage correction calculator 56 in each motor control cycle to output a fundamental voltage correction Va (see [0087] – [0090])
Therefore, it would have been an obvious modification before the effective filing date of the instant application for the control circuit to include a command current generator that generates the command current based on a command speed and the rotation speed detected by the rotation speed detector as thought by Suzuki within the teachings of Murata in order to adjust motor/generator power, keeping it stable despite load changes, ensuring consistent output (frequency/voltage), preventing overspeed/damage, and optimizing performance.
Allowable Subject Matter
Claims 10-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In view of the limitations the closest prior art including the prior works of the assignee/inventor does not explicitly describe or reasonably suggest or render obvious in combination with all the given limitations a difference between the command current and the motor current detected by the current detection circuit; and a control signal generator that generates, for each of the n-phases, a control signal having a pulse width proportional to the difference, and each of the transistor pairs of the n-phases turns on one of the first transistor and the second transistor and turns off the other based on the corresponding control signal.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure (US 2015/0061554 A1: A motor control apparatus has an inverter circuit having a plurality of pairs of upper and lower arms provided so as to correspond to a number of phases, and switching elements provided on each of the upper arms and the lower arms of each phase that drive a motor on the basis of ON or OFF operations of the respective switching elements, a single current detector that detects a current of the motor flowing through the inverter circuit, and a duty calculator that calculates duties of PWM signals for turning the switching elements ON or OFF on the basis of a deviation between a current value of the current detected by the current detector and a target current value – see [Abstract]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GABRIEL T AGARED whose telephone number is (571)270-1981. The examiner can normally be reached 8-5 (Mon- Thur).
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/GABRIEL AGARED/ Primary Examiner, Art Unit 2846