Prosecution Insights
Last updated: October 02, 2026
Application No. 18/459,766

CHIP-ON-FILM PACKAGE AND DISPLAY DEVICE INCLUDING THE SAME

Non-Final OA §102§103
Filed
Sep 01, 2023
Priority
Sep 15, 2022 — RE 10-2022-0116148
Examiner
SENGDARA, VONGSAVANH
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
3 (Non-Final)
72%
Grant Probability
Favorable
3-4
OA Rounds
2m
Est. Remaining
91%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
683 granted / 946 resolved
+4.2% vs TC avg
Strong +18% interview lift
Without
With
+18.4%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
78 currently pending
Career history
1018
Total Applications
across all art units

Statute-Specific Performance

§101
2.1%
-37.9% vs TC avg
§103
51.8%
+11.8% vs TC avg
§102
27.3%
-12.7% vs TC avg
§112
17.9%
-22.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 946 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 Receipt is acknowledged of a request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e) and a submission, filed on 06/11/2026. Response to Arguments Applicant’s arguments with respect to claim(s) rejected have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4, 6-9 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipate by Lin et al. 20210111153 (Lin). PNG media_image1.png 595 1137 media_image1.png Greyscale Regarding claim 1, fig. 2 of Lin discloses a chip-on-film package, comprising: a lower base film 110 including a first surface (bottom) and a second surface (top surface), which are opposite to each other; an upper base film (layer 160/152/151) including a third surface (bottom surface) and a fourth surface (top surface), which are opposite to each other, and is disposed on the lower base film; a first semiconductor chip 150 mounted on and electrically connected to the second surface of the lower base film and spaced apart from the third surface; a second semiconductor chip 120 mounted on and electrically connected to the third surface of the upper base film and spaced apart from the second surface; and an interposer film (141/121/112) interposed between the lower and upper base films, wherein the second and third surfaces face each other. Regarding claims 1-3, fig. 2 of Lin discloses a chip-on-film package, comprising: a lower base film 110 including a first surface (bottom) and a second surface (top surface), which are opposite to each other; an upper base film (layer 160/152/151) including a third surface (bottom surface) and a fourth surface (top surface), which are opposite to each other, and is disposed on the lower base film; a first semiconductor chip 150 (left) mounted on and electrically connected to the second surface of the lower base film and spaced apart from the third surface; a second semiconductor chip 150 (right) mounted on and electrically connected to the third surface of the upper base film and spaced apart from the second surface; and an interposer film (141/121/112) interposed between the lower and upper base films, wherein the second and third surfaces face each other; wherein the first semiconductor chip and the second semiconductor chip do not overlap with each other in a vertical direction with respect to the second surface of the lower base film; wherein at least part of the first semiconductor chip overlaps with the second semiconductor chip in a horizontal direction, which intersects the vertical direction. Regarding claim 4, it is necessary the case the fig. 2 of Lin discloses wherein a distance, in a horizontal direction, between the first semiconductor chip 150 and the second semiconductor chip 150 is about 6 mm or less (such as zero because counting distance between with value of 0 and increment thereafter). Regarding claim 6, fig. 2 of Kim discloses further comprising: lower conductive lines (lines of 112 at the bottom of 141) disposed on the second surface of the lower base film; and upper conductive lines (lines of 112 adn121 on upper surface of 141) disposed on the third surface of the upper base film. Regarding claim 7, fig. 2 of Lin discloses further comprising: to a lower protective member (bottom member of 141) covering at least portions of the lower conductive line; and an upper protective member (upper member of 141) covering at least portions of the upper conductive lines. Regarding claim 8, fig. 2 of Lin discloses wherein the interposer film includes a top surface and a bottom surface, which are opposite to each other, and further includes first interposer conductive lines (top pad portion on top of 121) and second interposer conductive lines (bottom pad portion on bottom of 121), wherein the first interposer conductive lines are disposed on a top surface of the interposer film and are connected to the upper conductive lines (there exist a physical connection as all elements are connected), and wherein the second interposer conductive lines are disposed on the bottom surface of the interposer film and are connected to the lower conductive lines (there exist a physical connection as all elements are connected). Regarding claim 9, fig. 2 of Lin disclose further comprising: interposer vias (hole around 112/121) penetrating the interposer film and connecting the first interposer conductive lines to the second interposer conductive lines. Regarding claim 11, fig. 2 of Lin disclose wherein a length of the upper base film is different from a length of the lower base film. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kim. Regarding claims 5 and 10, Lin discloses claim 1, but does not disclose wherein a thickness, in a vertical direction with respect to the second surface of the lower base film, of the interposer film is about 30 μm to about 40 μm; wherein a width of the interposer film is about 35 mm to about 156 mm. However, although Lin is silent about the claimed range, it should be noted that a range of value inherently exist. Therefore, the prior art of Lin provides foundation for experimental optimization and suggests a progress of changes in size/proportion in order to meet the device dimension. Therefore, while the structure of Kim does not quantitatively state a ratio, the courts have held that when the only difference between the claimed invention and the prior art is a size/proportion, then a prima facie case of obviousness exists [See MPEP 2144.04(IV)(A)]. Therefore, it would have been obvious a form a package of Lin wherein said range of the of the interposer film is about 30 μm to about 40 μm; wherein a width of the interposer film is about 35 mm to about 156 mm in order to meet the device dimension. Allowable Subject Matter Claims 12-20 are allowed. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, PURVIS A. Sue can be reached on (571 )272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893
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Prosecution Timeline

Show 6 earlier events
Mar 17, 2026
Final Rejection mailed — §102, §103
May 15, 2026
Response after Non-Final Action
Jun 11, 2026
Request for Continued Examination
Jun 15, 2026
Response after Non-Final Action
Jul 15, 2026
Non-Final Rejection mailed — §102, §103
Aug 11, 2026
Interview Requested
Aug 19, 2026
Examiner Interview Summary
Aug 19, 2026
Applicant Interview (Telephonic)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
72%
Grant Probability
91%
With Interview (+18.4%)
3y 3m (~2m remaining)
Median Time to Grant
High
PTA Risk
Based on 946 resolved cases by this examiner. Grant probability derived from career allowance rate.

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