DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 5, 6, 10, and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakano (US 20140048859 A1).
Regarding claim 1, FIG. 2A of Nakano teaches a semiconductor device (40; FIG. 1A; column 2, line 51) comprising:
a first insulating film (15; FIG. 2A; paragraph 0080);
a second insulating film (22; FIG. 2A; paragraph 0084); and
a tungsten film (17; FIG. 2A; paragraph 0080) provided between the first insulating film and the second insulating film, the tungsten film having a crystal particle (paragraph 0083), wherein a thickness T (paragraph 0116) of the tungsten film in a first direction from the first insulating film toward the second insulating film and an average particle size APS (paragraph 0083) of the crystal particle satisfy APS/T ≤ 2 (paragraph 0083; paragraph 0116).
Regarding claim 2, FIG. 10A and FIG. 10B of Nakano teach the semiconductor device according to claim 1, wherein the thickness T of the tungsten film (17; FIG. 10A; FIG. 10B; paragraph 0116) is 60 nm or less (paragraph 0116).
Regarding claim 5, FIG. 2A of Nakano teaches the semiconductor device according to claim 1, further comprising a barrier metal film (16; FIG. 2A; paragraph 0080) covering the tungsten film (17; FIG. 10A; FIG. 10B; paragraph 0116).
Regarding claim 6, FIG. 2C of Nanako teaches the semiconductor device according to claim 5, wherein the barrier metal film (16; FIG. 2C; paragraph 0081) contains TiN (paragraph 0081).
Regarding claim 7; FIG. 2A of Nakano teaches the semiconductor device according to claim 1, wherein the tungsten film (17; FIG. 10A; FIG. 10B; paragraph 0116) contains B (paragraph 0081).
Regarding claim 10, FIG. 2A of Nanako teaches the semiconductor device according to claim 1, wherein a ratio APS/T of the average particle size APS relative to the thickness T (paragraph 0116) of the tungsten film (17; FIG. 2A; paragraph 0080) is 0.3 or more (paragraph 0083; paragraph 0116).
Regarding claim 12, FIG. 2A of Nakano teaches the semiconductor device according to claim 1, further comprising:
a substrate (1; FIG.2A; paragraph 0079),
wherein the first direction is a vertical direction against the substrate (FIG. 2A).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Nakano in view of Miyanaga et al. (US 8766250 B2).
Regarding claim 3, FIG. 1A of Nakano teaches the semiconductor device according to claim 1. Nakano does not teach wherein the average particle size APS of the crystal particle of the tungsten film is 50 nm or less.
FIG. 1A of Miyanaga et al. teaches a metal film (70; FIG. 1A; column 2, line 52) with tungsten (column 4, lines 62-65) where the crystal atoms have a side length of 1 nm (column 12, line 2).
Nakano and Miyanaga et al. are both analogous to the claimed invention in that they involve semiconductor devices with tungsten layers. Therefor, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Nakano so that the average particle size APS of the crystal particle of the tungsten film is 50 nm or less. This allows the crystals to be structurally optimized (column 11, lines 58-59).
Regarding claim 9, FIG. 1A of Nakano teaches the semiconductor device according to claim 1. Nakano does not teach a ratio APS/T of the average particle size APS relative to the thickness T of the tungsten film being 1 or less.
FIG. 1A of Miyanaga et al. teaches a tungsten (column 4, lines 62-65) film of 150 nm in thickness (column 16, lines 8-9) was formed as the metal film 70 (70; FIG. 1A; column 2, line 52) where the crystal atoms have a side length of 1 nm (column 12, line 2).
Nakano and Miyanaga et al. are both analogous to the claimed invention in that they involve semiconductor devices with tungsten layers. Therefor, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Nakano so that a ratio APS/T of the average particle size APS relative to the thickness T of the tungsten film is 1 or less. This allows the crystals to be structurally optimized (column 11, lines 58-59).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Nakano in view of Watanabe et al. (US 20050029094 A1).
Regarding claim 4, Nakano teaches the semiconductor device according to claim 1. Nakano does not teach the tungsten film having a peak at orientation (110) and a peak at orientation (211).
Watanabe et al. teach a crystal orientation ratio (211)/{(110)+(200)+(211)+(220)+(310)} obtained when peak intensities of crystal planes (110), (200), (211), (220) and (310) of a surface of the target to be sputtered are analyzed by X-ray diffraction (paragraph 0030).
Nakano and Watanabe et al. are both analogous to the claimed invention in that they involve semiconductor devices using tungsten. Therefor, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Nakano to have peaks at orientations (110) and (211). Crystals planes (110) and (211) are known crystal planes (paragraph 0047), and when their ratios are controlled, the thickness of the tungsten fil is improved and the generation of unwanted particles is reduced (paragraph 0026).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Nakano in view of Kitao et al. (US 10541250 B2).
Regarding claim 8, FIG. 2A of Nakano teaches the semiconductor device according to claim 7, further comprising a barrier metal film (16; FIG. 2A; paragraph 0080) covering the tungsten film (17; FIG. 10A; FIG. 10B; paragraph 0116). Nakano does not teach the tungsten film containing B at a first concentration at a position P closer to the barrier metal film and containing B at a second concentration lower than the first concentration at a position Q farther from the barrier metal film than the position P.
Kitao et al. teaches a linear film (20; FIG. 15; paragraph 72) formed using a nitride of a metal (which will act as the metal barrier film) and, on top of that, the boron-containing tungsten films (61; FIG. 17; paragraph 95) and the tungsten films (22; FIG. 17; column 12, lines 45-46) alternately formed to form a stacked film (63; FIG. 17; column 12, lines 46-47), with the boron concentration in the tungsten film being lower than the boron concentration in the boron-containing tungsten film(column 12, lines 47-51).
Nakano and Kitao et al. are both analogous to the claimed invention in that they involve semiconductor devices using tungsten layers. it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Nakano to have the tungsten film containing B at a first concentration at a position P closer to the barrier metal film and containing B at a second concentration lower than the first concentration at a position Q farther from the barrier metal film than the position P. This is the result of how boron inevitably diffuses from the boron-containing tungsten film (column 12, lines 47-49).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Nakano in view of Fukuzumi et al. (US 20160276363 A1).
Regarding claim 11, Nakano teaches the semiconductor device according to claim 1. Nakano does not teach the device further comprising:
a semiconductor channel extending through the first insulating film, the second insulating film, and the tungsten film in the first direction; and
a charge storage film provided between the tungsten film and the semiconductor channel.
FIG. 2 and FIG. 3 of Fukuzumi et al. teach a memory hole being formed within the stacked body including the plurality of electrode layers (WL; FIG. 2; paragraph 0034) and the plurality of insulating layers (40; FIG. 2; paragraph 0034), with the electrode layers containing tungsten (paragraph 0196), a channel body as a semiconductor channel (20; FIG. 2; paragraph 0035 provided within the memory hole, and, between the electrode layers and the channel body, a charge storage film (32; FIG. 3; paragraph 0037) is provided.
Nakano and Fukuzumi et al. are both analogous to the claimed invention in that they involve semiconductor devices using tungsten layers and insulated layers. Therefor, it would have been obvious to a person with ordinary skill in the art before the effective filing date of the claimed invention to have modified Nakano to have a semiconductor channel extending through the first insulating film, the second insulating film, and the tungsten film in the first direction, as well as a charge storage film provided between the tungsten film and the semiconductor channel. This allows the semiconductor channel to properly channel the memory cells that the tungsten film acts as the control gate for while the charge storage functions a data memory later that accumulates charge injected from the channel body (paragraph 0040).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yamakazi et al. (US 20230051739 A1) concerns a memory device formed from stacking insulators and inserting conductors like tungsten. Higuchi et al. (US 20150371997 A1) concerns a memory device created by lairing first and second insulating films, electrodes, conductive layers, and a semiconductor layer..
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A VLCEK whose telephone number is (571)272-9665. The examiner can normally be reached Mon-Fri, 9:00 AM -5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/J.A.V./ Examiner, Art Unit 2817
/RATISHA MEHTA/ Primary Examiner, Art Unit 2817