DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on 09/01/2023 has been considered and
placed in the application file.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-7 and 9-13 are rejected under 35 U.S.C. 103 as being unpatentable over Kotrc (U.S. 10,775,823).
Regarding claim 1, Kotrc (hereinafter, Ref~823) discloses (please see Fig. 2 and related text for details) an amplifier circuit( 57 of Fig. 2) comprising:
a plurality of gain stages (see Fig. 2 for details) that change a gain (via bias/current adjustment features shown in Fig. 2) in each stage and include a first gain stage (centered by 81/82 of Fig. 2) and a final gain stage (centered by transistor 31 of Fig. 2);
an output terminal (38 of Fig. 2) that outputs a signal amplified by the plurality of gain stages;
a negative input terminal (gate of 82 of Fig. 2) connected to an input node (inverting terminal) of the first gain stage;
a feedback circuit (please note that Ref~823 teaches that “a voltage divider or other circuitry may be utilized to form the feedback (FB) signal to be representative of the value of voltage 15 as described in col. 3, between lines 45-55) connected between an output node of the final gain stage and the negative input terminal;
a first resistor (please note there would be an inherent resistance provided by the current mirror 33/34 of Fig. 2 and said resistance would be functionally equivalent to the claimed resistor) connected between the output node of the final gain stage and the output terminal; an
active load (87/88 of Fig. 2 can be read as the claimed load, since it can be adjusted based on the ON/OFF of the transistor 74) of the first gain stage including a first transistor (e.g., 87 of Fig. 2);
a second resistor (please note there would be an inherent resistance provided by the transistor 86 of Fig. 2 and/or resistance provided by switch/transistor 74 of Fig. 2 and said resistance would be functionally equivalent to the claimed resistor) connected to a gate or a base of the first transistor; and
a capacitor (75 of Fig. 2) connected between the gate or the base of the first transistor and the output node of the final gain stage as seen, meeting claim 1.
Regarding claim 6, Ref~823 discloses the amplifier circuit according to claim 1, wherein each of the plurality of gain stages includes a common-source amplifier circuit or a common-emitter amplifier circuit as seen, meeting claim 6.
Regarding claim 7, Ref~823 discloses the amplifier circuit according to claim 1, wherein the first gain stage includes a differential circuit (formed by 81/82 of Fig. 2), meeting claim 7.
Regarding claim 9, Kotrc discloses an amplifier circuit (57 of Fig. 2) comprising:
a plurality of gain stages (80/60 of Fig. 2) that change a gain in each stage and include a first gain stage (centered by 81/82 of Fig. 2), a second gain stage (centered by 125:128 of Fig. 2), and a final gain stage (centered by 31 of Fig. 2);
an output terminal (drain terminal of transistor 31 of Fig. 2) that outputs a signal amplified by the first gain stage and the final gain stage;
a negative input terminal (gate of transistor 82 of Fig. 2) connected to an input node of the first gain stage; a feedback circuit (please note that Ref~823 teaches that “a voltage divider or other circuitry may be utilized to form the feedback (FB) signal to be representative of the value of voltage 15” as described in col. 3, between lines 45-55 ) connected between an output node (38 of Fig. 2) of the final gain stage and the negative input terminal;
a first resistor (please note an inherent resistance provided by the current mirror 33/34 of Fig. 2 is functionally equivalent to the claimed resistor) connected between the output node of the final gain stage and the output terminal; and
a capacitor (capacitor 75 of Fig. 2) and the second gain stage connected in series to a path from the output node of the final gain stage to an input node of the final gain stage, meeting claim 9.
Regarding claim 10, Ref~823 does not expressly disclose “wherein a gain of the second gain stage is larger than 1”. However, these are normal design parameters in the field depending on custom specifications, meeting claim 10.
Regarding claim 11, Ref~823 discloses the amplifier circuit according to claim 9, wherein the second gain stage includes a common-source amplifier circuit or a common-emitter amplifier circuit as seen from Fig. 2, meeting claim 11.
Regarding claim 12, Ref~823 discloses the amplifier circuit according to claim 1, comprising a switching circuit (74 of Fig. 2) that performs selection for connecting the output node of the final gain stage to any one of a plurality of load circuits, wherein the first resistor includes an on-resistor of the switching circuit, meeting claim 12.
Regarding claim 13, Ref~823 discloses the amplifier circuit according to claim 1, wherein the feedback circuit has wiring and has no active element and no passive element, and the amplifier circuit operates as a voltage follower circuit as seen from Fig. 2, meeting claim 13.
Allowable Subject Matter
Claims 2-5, 8 and 14-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEU P NGUYEN whose telephone number is 571-272-8577. The examiner can normally be reached on Monday-Friday 8:30AM-6:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/HIEU P NGUYEN/Primary Examiner, Art Unit 2843