DETAILED ACTION
This office action is in response to the application filed on 09/01/2023. Claims 1-30 have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/01/2023 and 01/13/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that use the word “means” or “step” but are nonetheless not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph because the claim limitation(s) recite(s) sufficient structure, materials, or acts to entirely perform the recited function. Such claim limitation(s) is/are: means for in claim 30.
Because this/these claim limitation(s) is/are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-30 are rejected under 35 U.S.C. 103 as being unpatentable over Vetro (US 6,519,288) in view of Lu (US 2019/0392716).
Regarding claim 1, Vetro discloses the following claim limitations: and a video decoder coupled to the memory and to a cache, the video decoder configured to decode an input frame of the video data to generate a first video frame and including an inline downscaler configured to generate a second video frame corresponding to the first video frame downscaled for display output (Vetro, Column 3 lines 17-27 discloses FIG. 15 illustrates a conventional apparatus for decoding and down-converting an incoming HD bitstream. A variable length decoder (VLD) and dequantizer (IQ) 10 receives an incoming HD transmission, performs variable length decoding on the MPEG encoded video signals, and dequantizes the resulting DCT coefficients to produce arrays of dequantized DCT coefficients. The resulting DCT coefficient blocks are then converted to the spatial domain by an inverse discrete cosine transformer (IDCT) 14. A picture store 22 stores the two previous anchor pictures (e.g., I or P-pictures; down converter i.e. inline downscaler).
Vetro does not explicitly disclose the following claim limitation: A device comprising: a memory configured to store video data.
However, in the same field of endeavor in the same field of endeavor Lu discloses more explicitly the following: a device comprising: a memory configured to store video data (Lu, paragraph 48 discloses a processor 125; a memory 127).
It would have been obvious to one the ordinary skill in the art at the time of invention to modify the teachings of Vetro with Lu to create the decoding apparatus of Vetro with a vehicle system comprising a processor and memory.
The reasoning being is to improve flying range of drones (Lu, paragraph 4).
Regarding claim 2, Vetro and Lu discloses the device of claim 1, wherein the video decoder is configured to output the first video frame and the second video frame in parallel (Vetro, fig. 8 illustrates the recited claim language).
Regarding claim 3, Vetro and Lu discloses the device of claim 1, wherein the video decoder is configured to select between storing the second video frame into the memory or into the cache (Lu, paragraph 117 discloses the communication module 203 receives data from components of the selection module 197 and stores the data in the memory 227 (or a buffer or cache of the memory 227, or a standalone buffer or cache which is not depicted in FIG. 2B). The same motivation that was utilized in claim 1 applies equally as well to claim 3.
Regarding claim 4, Vetro and Lu discloses the device of claim 1, wherein the video decoder is configured to store a first portion of the second video frame into the memory and to store a second portion of the second video frame into the cache (Vetro, Column 3 lines 17-27 discloses FIG. 15 illustrates a conventional apparatus for decoding and down-converting an incoming HD bitstream. A variable length decoder (VLD) and dequantizer (IQ) 10 receives an incoming HD transmission, performs variable length decoding on the MPEG encoded video signals, and dequantizes the resulting DCT coefficients to produce arrays of dequantized DCT coefficients. The resulting DCT coefficient blocks are then converted to the spatial domain by an inverse discrete cosine transformer (IDCT) 14. A picture store 22 stores the two previous anchor pictures (e.g., I or P-pictures; down converter i.e. inline downscaler… Lu, paragraph 117 discloses the communication module 203 receives data from components of the selection module 197 and stores the data in the memory 227 (or a buffer or cache of the memory 227, or a standalone buffer or cache which is not depicted in FIG. 2B). The same motivation that was utilized in claim 1 applies equally as well to claim 4.
Regarding claim 5, Vetro and Lu discloses the device of claim 1, wherein the first video frame is stored into the memory, and wherein the second video frame is stored into the cache (Vetro, Column 3 lines 17-27 discloses FIG. 15 illustrates a conventional apparatus for decoding and down-converting an incoming HD bitstream. A variable length decoder (VLD) and dequantizer (IQ) 10 receives an incoming HD transmission, performs variable length decoding on the MPEG encoded video signals, and dequantizes the resulting DCT coefficients to produce arrays of dequantized DCT coefficients. The resulting DCT coefficient blocks are then converted to the spatial domain by an inverse discrete cosine transformer (IDCT) 14. A picture store 22 stores the two previous anchor pictures (e.g., I or P-pictures; down converter i.e. inline downscaler… Lu, paragraph 117 discloses the communication module 203 receives data from components of the selection module 197 and stores the data in the memory 227 (or a buffer or cache of the memory 227, or a standalone buffer or cache which is not depicted in FIG. 2B). The same motivation that was utilized in claim 1 applies equally as well to claim 5.
Regarding claim 6, Vetro and Lu discloses the device of claim 1, wherein the first video frame is stored into the memory based on a determination that the first video frame is a reference frame, and wherein storage of full-resolution non-reference frames to the memory is skipped (Vetro, fig. 8 illustrates the recited claim language).
Regarding claim 7, Vetro and Lu discloses the device of claim 1, further comprising a display unit configured to receive the second video frame and to generate an output to a display device (Lu, paragraph 54 discloses output display device). The same motivation that was utilized in claim 1 applies equally as well to claim 7.
Regarding claim 8, Vetro and Lu discloses the device of claim 7, wherein the display unit is configured to receive the second video frame from the cache (Lu, paragraph 54 discloses output display device). The same motivation that was utilized in claim 1 applies equally as well to claim 8.
Regarding claim 9, Vetro and Lu discloses the device of claim 7, wherein the display unit is configured to receive the second video frame from the memory (Lu, paragraph 54 discloses output display device). The same motivation that was utilized in claim 1 applies equally as well to claim 9.
Regarding claim 10, Vetro and Lu discloses the device of claim 7, wherein the display unit is configured to selectively receive the second video frame from the memory or from the cache (Lu, paragraph 117 discloses the communication module 203 receives data from components of the selection module 197 and stores the data in the memory 227 (or a buffer or cache of the memory 227, or a standalone buffer or cache which is not depicted in FIG. 2B). The same motivation that was utilized in claim 1 applies equally as well to claim 10.
Regarding claim 11, Vetro and Lu discloses the device of claim 7, wherein the display unit is configured to receive a first portion of the second video frame from the memory and a second portion of the second video frame from the cache (Vetro, Column 3 lines 17-27 discloses FIG. 15 illustrates a conventional apparatus for decoding and down-converting an incoming HD bitstream. A variable length decoder (VLD) and dequantizer (IQ) 10 receives an incoming HD transmission, performs variable length decoding on the MPEG encoded video signals, and dequantizes the resulting DCT coefficients to produce arrays of dequantized DCT coefficients. The resulting DCT coefficient blocks are then converted to the spatial domain by an inverse discrete cosine transformer (IDCT) 14. A picture store 22 stores the two previous anchor pictures (e.g., I or P-pictures; down converter i.e. inline downscaler… Lu, paragraph 117 discloses the communication module 203 receives data from components of the selection module 197 and stores the data in the memory 227 (or a buffer or cache of the memory 227, or a standalone buffer or cache which is not depicted in FIG. 2B). The same motivation that was utilized in claim 1 applies equally as well to claim 11.
Regarding claim 12, Vetro and Lu discloses the device of claim 1, further comprising a display device configured to display an output based on the second video frame (Lu, paragraph 54 discloses output display device). The same motivation that was utilized in claim 1 applies equally as well to claim 12.
Regarding claim 13, Vetro and Lu discloses the device of claim 1, further comprising one or more processors that include the video decoder (Lu, paragraph 48 discloses a processor 125; a memory 127). The same motivation that was utilized in claim 1 applies equally as well to claim 13.
Regarding claim 14, Vetro and Lu discloses the device of claim 13, further comprising a modem coupled to the one or more processors and configured to receive the video data (Lu, paragraph 48 discloses a processor 125; a memory 127). The same motivation that was utilized in claim 1 applies equally as well to claim 14.
Regarding claim 15, Vetro and Lu discloses the device of claim 13, wherein the one or more processors are integrated in an extended reality headset device that is configured to display an output based on the second video frame (Lu, paragraph 54 discloses output display device; Lu, paragraph 26 discloses a DSRC message is a wireless message that is specially configured to be sent and received by highly mobile devices such as vehicles). The same motivation that was utilized in claim 1 applies equally as well to claim 15.
Regarding claim 16, Vetro and Lu discloses the device of claim 13, wherein the one or more processors are integrated in at least one of a mobile phone, a tablet computer device, or a wearable electronic device (Lu, paragraph 26 discloses a DSRC message is a wireless message that is specially configured to be sent and received by highly mobile devices such as vehicles). The same motivation that was utilized in claim 1 applies equally as well to claim 16.
Regarding claim 17, Vetro and Lu discloses the device of claim 13, wherein the one or more processors are integrated in a vehicle, the vehicle further including a display device configured to display an output based on the second video frame (Lu, fig. 1). The same motivation that was utilized in claim 1 applies equally as well to claim 17.
Regarding claim 18, Vetro and Lu discloses the device of claim 13, wherein the one or more processors are included in an integrated circuit (Lu, paragraph 48 discloses a processor 125; a memory 127). The same motivation that was utilized in claim 1 applies equally as well to claim 18.
With regard to claims 19-30, claims 19-30 lists all the same elements and features to claims 1-18 as outlined above. Therefore, the same rationale that was utilized in claims 1-18 applies equally as well to claims 19-30.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JERRY T JEAN BAPTISTE whose telephone number is (571)272-6189. The examiner can normally be reached Monday-Friday 9-5PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Vaughn can be reached at 571-272-3922. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JERRY T JEAN BAPTISTE/Primary Examiner, Art Unit 2481