DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The present application is being examined under the claims filed 11/03/2025. Claims 1, 7, 8, 11, 17, 18, and 20 are amended. Claims 1-20 are pending. Claims 1-20 are rejected.
Response to Arguments
I. Applicant's arguments filed 10/21/2025 have been fully considered but they are not persuasive.
II. Applicant argues “The independent claims as amended recite where a BMC logs a first value each time a BIOS initializes a first parameter, determines that the first value represents a first excursion from a value received during a prior initialization of the first parameter, determines a health status for the information handling system based upon the first excursion, and provides an indication of the health status. The art of record fails to disclose the features of the independent claims as amended and those claims therefore are allowable, as are the claims that depend therefrom.” Examiner respectfully disagrees.
Karpagavinayagam teaches wherein the BMC is configured to log the first value [when] the BIOS initializes the first parameter, to determine that the first value represents a first excursion from a value received during a prior initialization of the first parameter (Karpagavinayagam par. 40, the host health monitor 136 can further analyze the health data of a period of time stored in the data store [i.e., prior initializations, see par. 31, SMI handler 202 can be considered as part of the initialization component 192, and par. 38, SMI handler 202 can use a message defined by the management protocol to send the health data [i.e., first values] to the BMC 102, and par. 40, host health monitor 136 (on BMC 102) can store the health data in a data store after receiving health data, i.e., the data store contains health data from prior initializations, also see process at FIG. 3]; and par. 47, the service processor determines that a first hardware component of the at least one hardware components is defective based on the health data in the data store [i.e., prior initializations, see above]... in certain configurations, the first hardware component is determined to be defective based on a number of times the first hardware component has been in the one or more predetermined health conditions [i.e., determine excursions from a “healthy” initialization]).
The “value received” being evaluated in Karpagavinayagam is the one or more predetermined health conditions of the component, based on its current operating conditions (i.e., the parameters used to initialize the component). The health condition is used to determine a health status for the information handling system based upon the first excursion (Karpagavinayagam par. 46, the initialization component operates in the system management mode and obtains the health data, then par. 47, the service processor receives the message from the initialization component and analyzes the health data and determine if at least one hardware components is defective [i.e., health status]) and the system provides an indication of the health status (Karpagavinayagam FIG. 3, step 320 and 322, initialization component sends message (i.e., indication) with included health data to the host [also see par. 46]; and par. 40, the host health monitor 136 may determine that the particular hardware component is defective and generates a warning for that particular hardware component).
Therefore, Karpagavinayagam discloses the limitation “where a BMC logs a first value each time a BIOS initializes a first parameter, determines that the first value represents a first excursion from a value received during a prior initialization of the first parameter, determines a health status for the information handling system based upon the first excursion, and provides an indication of the health status.”
Claim Objections
Claim 3 is objected to because of the following informalities:
Regarding Claim 3, line 1 appears to be missing the word “wherein,” such that the claim reads “The information handling system of claim 2, wherein the DIMM is a fifth generation double data rate (DDR5)” (emphasis added).
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 7, 8, 10, 11, 17, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Karpagavinayagam et. al. (US 2019/0171507 A1) in view of Cho et. al. (US 2022/0398152 A1).
Regarding Claim 1, Karpagavinayagam discloses an information handling system (Karpagavinayagam FIG 1. computing system 100) comprising;
a baseboard management controller (BMC) (Karpagavinayagam FIG. 1, BMC 102);
a first I/O device (Karpagavinayagam FIG. 1, memory 184 on host 180); and
a Basic Input/Output System (BIOS) executed by a processor separately from the BMC (Karpagavinayagam FIG. 1, CPU 182 on host 180, separate from BMC 102; and par. 26, the host CPU 182 loads an initialization component 192 (e.g., a basic input/output system (BIOS)) from the storage devices 185 into the host memory 184), and configured to initialize a first parameter of the first I/O device with a first value, wherein the BIOS includes an I/O health check module (Karpagavinayagam par. 26, 31, and 36, POST used to initialize the standard system components, and performs reliability test via SMI handlers and system management mode [i.e., health check, see par. 31, "the host CPU 182 can be interrupted to enter a system management mode (SMM)… when the host CPU 182 enters the SMM, the host CPU 182 executes the SMI handler 202 stored at the pre-configured location. The SMI handler 202 can be considered as part of the initialization component 192.", i.e., SMI handler is part of the BIOS], generate error and trigger SMI; and par. 26, the POST initialize the standard system components and sets the default values [i.e., initializes first parameters] for a table of interrupt vectors, default values point to standard interrupt handlers in the memory 114 or a ROM) configured each time the BIOS initializes the first parameter, to receive the first value, to determine whether the first value is within a first range of first values (Karpagavinayagam par. 26, 31, and 36, POST used to initialize the standard system components [i.e., an instance for each component, i.e., each time], and performs reliability test [i.e., receive first values, see par. 31, initialization component 192 can gather health status [i.e., first values] of those hardware components, also see par. 37, severity of the errors may be used to reflect the hardware health status (e.g., “OK,” “Warning,” or Critical) [i.e., range of first values]], test may generate error, and trigger SMI), and to provide the first value to the BMC (Karpagavinayagam par. 38, SMI [which is part of BIOS, see par. 31] communicates with BMC, SMI handler 202 subsequently can use a message defined by the management protocol to send the health data [i.e., first values] to the BMC 102);
wherein the BMC is configured to log the first value [when] the BIOS initializes the first parameter (Karpagavinayagam par. 40, host health monitor 136 (which is a part of the BMC) can store the health data in a data store (e.g., a database) on the BMC 102 [i.e., logging]; and par. 38, health data includes the identity of the hardware component (e.g., the host CPU 182) for which the health data were generated, the type of health condition (e.g., thermal or power), the severity of the health condition (e.g., low, medium, or high), health condition data (e.g., the actual temperature of the host CPU 182), etc.; also see FIG. 3, step 328 store health data in data store) to determine that the first value represents a first excursion from a value received during a prior initialization of the first parameter (Karpagavinayagam par. 40, the host health monitor 136 can further analyze the health data of a period of time stored in the data store [i.e., prior initializations, see par. 31, SMI handler 202 can be considered as part of the initialization component 192, and par. 38, SMI handler 202 can use a message defined by the management protocol to send the health data [i.e., first values] to the BMC 102, and par. 40, host health monitor 136 (on BMC 102) can store the health data in a data store after receiving health data, i.e., the data store contains health data from prior initializations, also see process at FIG. 3]; and par. 47, the service processor determines that a first hardware component of the at least one hardware components is defective based on the health data in the data store [i.e., prior initializations, see above]... in certain configurations, the first hardware component is determined to be defective based on a number of times the first hardware component has been in the one or more predetermined health conditions [i.e., determine excursions from a “healthy” initialization]) to determine a health status for the information handling system based upon the first excursion (Karpagavinayagam par. 46, the initialization component operates in the system management mode and obtains the health data, then par. 47, the service processor receives the message from the initialization component and analyzes the health data and determine if at least one hardware components is defective), and to provide an indication of the health status (Karpagavinayagam FIG. 3, step 320 and 322, initialization component sends message (i.e., indication) with included health data to the host [also see par. 46]; and par. 40, the host health monitor 136 may determine that the particular hardware component is defective and generate a warning for that particular hardware component).
Karpagavinayagam does not explicitly teach:
wherein the BMC is configured to log the first value each time the BIOS initializes the first parameter.
In the analogous art of monitoring parameters to determine proper functioning of a device, Cho teaches an information handling system (Cho FIG. 1, IHS 100 connected to BMC 132):
where the parameter is logged each time, the BIOS initializes the first parameter (Cho par. 30, bootloader 222 specifies the parameters engine 224 is to monitor and control [i.e., the parameters are initialized at boot]; and par. 31, engine 224 is configured to continually log events during its operation, such as parameters that are received by the engine 224 [the engine receives these parameters at the time of boot from the bootloader]).
Therefore, it would have been obvious of one of ordinary skill in the art, having the teachings of Karpagavinayagam and Cho before them, before the effective filing date of the claimed invention, to combine Karpagavinayagam’s system for monitoring and updating component health statuses with Cho’s logging values at initialization, the motivation being to detect and prevent damage to components of the IHS (Cho par. 16).
Regarding Claim 7, Karpagavinayagam in view of Cho teaches information handling system of claim 1.
Claim 7 recites the limitations of claim 1 using a second parameter. Both Karpagavinayagam and Cho disclose tracking multiple parameters to track overall health of system components (Karpagavinayagam par. 62, BMC 566 monitors health-related aspects associated with the computer system 502, such as, but not limited to, the temperature of one or more components of the computer system 502, speed of rotational components (e.g., spindle motor, CPU Fan, etc.) within the system, the voltage across or applied to one or more components within the system 502, and the available or used capacity of memory devices within the system 502 [also see Karpagavinayagam par. 26, POST is used to initialize the standard system components, such as system timers, system DMA (Direct Memory Access) controllers, system memory controllers, system I/O devices and video hardware]; and Cho par. 30 and 36, configuration file may include fields for selecting whether or not a fan speed and/or a memory write rate may be monitored and/or controlled by the engine).
Therefore, the method of claim 1 is carried out by Karpagavinayagam in view of Cho by initializing and monitoring an additional parameter (the second parameter).
Regarding Claim 8, Karpagavinayagam in view of Cho teaches information handling system of claim 1.
Claim 8 recites the limitations of claim 1 using a second I/O device. Both Karpagavinayagam and Cho disclose tracking multiple I/O devices to track overall health of the system (Karpagavinayagam par. 24, system management components 206 monitors the health conditions of the host CPU 182, the host memory 184, the storage devices 185, and the hardware components 186-1 to 186-N; and Cho par. 36, CPU, memory, and I/O usage information 236 may be monitored).
Therefore, the method of claim 1 is carried out by Karpagavinayagam in view of Cho by initializing and monitoring an additional I/O device (the second I/O device).
Regarding Claim 10, Karpagavinayagam in view of Cho teaches information handling system of claim 1 wherein the indication includes:
an alert indication when the parameter value exhibits an excursion from a range that has a first value (Cho FIG. 3 step 312, checks if parameter is out of range; and Cho par. 49, in response to the parameter being out of range, the method 300 may generate an alert signal or message), a watch indication when the parameter value exhibits the excursion that has a second value greater than the first value, a warning indication when the parameter value exhibits the excursion that has a third value greater than the fourth value (Karpagavinayagam par. 38, the severity of the health condition may be indicated (e.g., low, medium, or high) [i.e., severity of indications (alert, watch, warning)]; also see par. 37, severity of the errors may be used to reflect the hardware health status “OK,” “Warning,” or “Critical”), a failure indication when the parameter value exhibits the excursion that has a fourth value greater than the third value (Karpagavinayagam par. 37, SMI handler 202 will construct or frame a BMC SEL record that has information of the failed component) [also see par. 40, thresholds for indicating health statuses, such as frequency and severity of errors generated by particular a hardware component, when frequency and severity meets predetermined thresholds (e.g., 5 severe errors in 12 hours), the host health monitor 136 may determine that the particular hardware component is defective and generate a warning; also see par. 41, e.g., host CPU 182 has reached a critical high temperature based on the health data].
Regarding Claim 11, Karpagavinayagam discloses a method for operating an IHS (Karpagavinayagam FIG 1. computing system 100).
The remainder of claim 11 is similar in scope to claim 1 as addressed above and is thus rejected under the same rationale.
Regarding Claim 17, the claim is similar in scope to claim 7 as addressed above and is thus rejected under the same rationale.
Regarding Claim 18, the claim is similar in scope to claim 8 as addressed above and is thus rejected under the same rationale.
Regarding Claim 20, Karpagavinayagam discloses a manufacturing system (Karpagavinayagam par. 29, computer 180 may be a computer system in a data center), comprising;
a management system (Karpagavinayagam par. 29-30, host computer [i.e., management system] may exchange data with other computer systems in the data center or exchange data with machines on the Internet; and par. 30, BMC 102 may be in communication with the communication network 170); and
a plurality of information handling systems (Karpagavinayagam par. 29, the host computer 180 may be a computer system in a data center and the host computer 180 may exchange data with other computer systems in the data center), each information handling system including the components of claim 1.
wherein the management system is configured to receive the indications from the BMCs and to determine a manufacturing trend for the information handling systems based upon the indications (Karpagavinayagam par. 38, health information includes original equipment manufacturer (OEM) system event log (SEL) and carry a Manufacturer ID, and the health data of the host computer; and par. 29-30, the remote device 175 may send IPMI messages to the BMC 102 over the communication network 170, also see par. 40, health data can be stored in the communication network 170; and par. 40, use data in the database to determine the overall health condition of each of the host CPU 182, the host memory 184, the storage devices 185, and the hardware components 186-1 to 186-N).
The remainder of claim 20 is similar in scope to claim 1 as addressed above and is thus rejected under the same rationale.
Claims 2-6, 9, 12-16, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Karpagavinayagam in view of Cho further in view of Chaikan (US 11526411 B2) [previously cited].
Regarding Claim 2, Karpagavinayagam in view of Cho teaches information handling system of claim 1. Karpagavinayagam in view of Cho further teach:
wherein the first I/O device is a […] memory module (Karpagavinayagam par. 34, health condition of memory 184 is monitored; or Cho par. 30, a memory write rate may be monitored and/or controlled by the engine 224).
Karpagavinayagam in view of Cho does not explicitly teach:
wherein the first I/O device is a dual in-line memory module (DIMM).
In the analogous art of monitoring functionality of hardware devices, Chaikan teaches memory may be in the form of one or more DDR Dual In-Line Memory Modules (DIMMs) (Chaikan Col. 3 lines 5-17, memory channel and memory 120 represents one or more DDR Dual In-Line Memory Modules (DIMMs)).
Therefore, it would have been obvious of one of ordinary skill in the art, having the teachings of Karpagavinayagam, Cho, and Chaikan before them, before the effective filing date of the claimed invention, to combine Karpagavinayagam’s and Cho’s system architecture and functionality with Chaikan’s memory form factor, the motivation being to be in accordance with a particular DDR standard (Chaikan Col. 3 lines 5-17).
Regarding Claim 3, Karpagavinayagam in view of Cho, further in view of Chaikan teaches information handling system of claim 2, wherein:
the DIMM is a fifth generation double data rate (DDR5) DIMM (Chaikan Col. 3 lines 5-17, a DDR channel and the connected DDR DIMMs can be in accordance with a particular DDR standard, such as a DDR5 standard).
Regarding Claim 4, Karpagavinayagam in view of Cho, further in view of Chaikan teaches information handling system of claim 3,
wherein the parameter includes one of a command/address bus write leveling (Cho par. 30, memory write rate and memory read rate), a data bus read/write leveling, a timing margin (Cho par. 36, processing rate or data throughput), and a read/write voltage margin (Karpagavinayagam par. 62, voltage applied; or Cho par. 36, output voltage and current draw)).
Regarding Claim 5, Karpagavinayagam in view of Cho teaches information handling system of claim 1.
Karpagavinayagam in view of Cho does not explicitly teach
wherein the first I/O device is a PCIe device.
In the analogous art of monitoring functionality of hardware devices, Chaikan teaches
wherein the first I/O device is a PCIe device (Chaikan Col. 3 lines 38-48, I/O channel may link chipset 110 and memory (NV-RAM 140) using PCIe [i.e., first I/O device]).
Therefore, it would have been obvious of one of ordinary skill in the art, having the teachings of Karpagavinayagam, Cho, and Chaikan before them, before the effective filing date of the claimed invention, to combine Karpagavinayagam’s and Cho’s system architecture and functionality with Chaikan’s I/O form factor, the motivation being to be in accordance with a particular I/O standards (Chaikan Col. 3 lines 42-48).
Regarding Claim 6, Karpagavinayagam in view of Cho teaches information handling system of claim 1.
Karpagavinayagam in view of Cho does not explicitly teach
wherein the first I/O device is a SATA device.
In the analogous art of monitoring functionality of hardware devices, Chaikan teaches wherein the first I/O device is a SATA device (Chaikan FIG. 2, SATA device 240; also see col. 3 lines 55-62, disk controller 150 [i.e., first I/O device] includes a disk interface 152 that connects the disc controller to a hard disk drive (HDD), example of disk interface 152 includes a serial ATA (SATA) interface).
Regarding Claim 9, Karpagavinayagam in view of Cho teaches information handling system of claim 8,
the first I/O device is a [memory module] (Karpagavinayagam par. 34, health condition of memory 184 is monitored; or Cho par. 30, a memory write rate may be monitored and/or controlled by the engine 224).
a second I/O device […] (Karpagavinayagam par. 24, system management components 206 monitors the health conditions of the host CPU 182, the host memory 184, the storage devices 185, and the hardware components 186-1 to 186-N; and Cho par. 36, CPU, memory, and I/O usage information 236 may be monitored).
Karpagavinayagam in view of Cho does not explicitly teach
wherein the first I/O device is a DIMM; and
the second I/O device is a Peripheral Component Interconnect-Express (PCIe) device.
In the analogous art of monitoring functionality of hardware devices, Chaikan teaches wherein the I/O devices may be a DIMM or a PCIe device, as addressed with claims 3 and 5 above respectively.
Therefore, it would have been obvious of one of ordinary skill in the art, having the teachings of Karpagavinayagam, Cho, and Chaikan before them, before the effective filing date of the claimed invention, to combine Karpagavinayagam’s and Cho’s system architecture and functionality with Chaikan’s I/O form factors, the motivation being to be in accordance with particular I/O standards (Chaikan Col. 3 lines 42-48).
Regarding Claim 12, the claim is similar in scope to claim 2 as addressed above and is thus rejected under the same rationale.
Regarding Claim 13, the claim is similar in scope to claim 3 as addressed above and is thus rejected under the same rationale.
Regarding Claim 14, the claim is similar in scope to claim 4 as addressed above and is thus rejected under the same rationale.
Regarding Claim 15, the claim is similar in scope to claim 5 as addressed above and is thus rejected under the same rationale.
Regarding Claim 16, the claim is similar in scope to claim 6 as addressed above and is thus rejected under the same rationale.
Regarding Claim 19, the claim is similar in scope to claim 9 as addressed above and is thus rejected under the same rationale.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLE JIAWEI WENTZEL whose telephone number is (703) 756-4762. The examiner can normally be reached 9:30am-5:30pm ET (Mon-Fri).
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/C.J.W./Examiner, Art Unit 2175
/ANDREW J JUNG/Supervisory Patent Examiner, Art Unit 2175
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