DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Applicant’s election of Group I, Claims 1-8 and 10-17, drawn to a device, for examination, without traverse, has been acknowledged. Claims 1-18 remain pending. Claims 9 and 18 are withdrawn from consideration.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, and 11-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Uchimura et al (US 2021/0082940).
Regarding Claim 1, Uchimura et al discloses a semiconductor memory device (NAND memory [0080] Fig 6) comprising: a stacked body (shown in annotated Fig 6) including a first insulating layer (insulating layers 72 [0082]) and a first conductive layer (conductive layers [0082]) alternately stacked (shown in Fig 6) in a first direction (z-direction Fig 6);
a columnar body (pillar MP has a columnar structure [0083]) including: a first insulating portion (core layer 84 may contain an insulator [0107]) extending in the first direction (z- direction Fig 6) in the stacked body (shown in annotated Fig 6), a first semiconductor portion (semiconductor layer 82 [0105]) disposed between the first insulating portion (84) and the stacked body (shown in annotated Fig 6), and
a third insulating portion (insulating layer 803 [0114]) disposed between a second insulating portion (insulating layer 801 [0114]) disposed between the first semiconductor portion (82) and the stacked body (shown in annotated Fig 6), and the second insulating portion (801) and the stacked body (shown in annotated Fig 6), the columnar body (MP) having a first end (top end shown in Fig 6) and a second end (bottom end shown in Fig 6) opposite to the first end (top end shown in Fig 6); and
a second conductive layer (cap layer (conductive layer) 86 [0105]) disposed on the stacked body (shown in annotated Fig 6) and electrically connected to the first semiconductor portion (82) at the first end (top end shown in Fig 6) of the columnar body (MP),
wherein the first insulating portion (84) blocks an inner side of the first semiconductor portion (82) at the first end (top end shown in Fig 6) of the columnar body (MP), and the first insulating portion (84) having a space (air gap 90 [0106]) in the first semiconductor portion (82) at a position closer to the second end (bottom end shown in Fig 6) than the first end (top end shown in Fig 6).
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Regarding Claim 2, Uchimura et al discloses the limitations of claim 1 as explained above. Uchimura et al further discloses
wherein the stacked body (shown in annotated Fig 6) includes a first stacked body (shown in annotated Fig 6) and a second stacked body (shown in annotated Fig 6), the second stacked body (shown in annotated Fig 6) further spaced from the second conductive layer (86) than the first stacked body (shown in annotated Fig 6),
wherein the columnar body (shown in annotated Fig 6) includes
a first columnar body (shown in annotated Fig 6) extending in the first direction (z-direction Fig 6) in the first stacked body (shown in annotated Fig 6) and
a second columnar body (shown in annotated Fig 6) extending in the first direction (z-direction Fig 6) in the second stacked body (shown in annotated Fig 6), and
wherein the first insulating portion (84) in the first columnar body (shown in annotated Fig 6) in the first stacked body (shown in annotated Fig 6) blocks the inner side of the first semiconductor portion (82) at the first end of the first columnar body (shown in annotated Fig 6), and
the first insulating portion (84) of the first and second columnar bodies (shown in annotated Fig 6) at a position closer to the second end (bottom end shown in Fig 6) than the first end (top end shown in Fig 6) has a space (90) in the first insulating portion (84).
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Regarding Claim 3, Uchimura et al discloses the limitations of claim 1 as explained above. Uchimura et al further discloses
wherein the stacked body (shown in annotated Fig 6) includes a first stacked body (shown in annotated Fig 6) and a second stacked body (shown in annotated Fig 6), the second stacked body (shown in annotated Fig 6) further spaced from the second conductive layer (86) than the first stacked body (shown in annotated Fig 6),
wherein the columnar body (MP) includes a first columnar body (shown in annotated Fig 6) extending in the first direction (z-direction Fig 6) in the first stacked body (shown in annotated Fig 6) and a second columnar body (shown in annotated Fig 6) extending in the first direction (z-direction Fig 6) in the second stacked body (shown in annotated Fig 6),
wherein the inner side of the first semiconductor portion (82) is filled with the first insulating portion (84) in the first columnar body (shown in annotated Fig 6) in the first stacked body (shown in annotated Fig 6), and
wherein the first insulating portion (84) of the second columnar body (shown in annotated Fig 6) in the second stacked body (shown annotated Fig 6) has a space (90) in the first insulating portion (84).
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Regarding Claim 4, Uchimura et al discloses the limitations of claim 1 as explained above. Uchimura et al further discloses
wherein a width (shown in annotated Fig 6) of the columnar body (MP) on a cross-sectional surface of the first direction (z-direction Fig 6) narrows as the columnar body (MP) becomes closer to the second conductive layer (86).
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Regarding Claim 5, Uchimura et al discloses the limitations of claim 1 as explained above. Uchimura et al further discloses
wherein a thickness of the first insulating portion (84) at the first end (top end shown in Fig 6) is thicker than a thickness of the first insulating portion (84) on an inner wall of the first semiconductor portion (82) in a portion of the space (90).
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Regarding Claim 6, Uchimura et al discloses the limitations of claim 1 as explained above. Uchimura et al further discloses
wherein the stacked body (shown in annotated Fig 6) includes a first stacked body (shown in annotated Fig 6) close to the second conductive layer (86), a second stacked body (shown in annotated Fig 6) further spaced from the second conductive layer (86) than the first stacked body (shown in annotated Fig 6), and a third stacked body (shown in annotated Fig 6) further spaced from the second conductive layer (86) than the second stacked body (shown in annotated Fig 6), wherein the columnar body (MP) includes:
a first columnar body (shown in annotated Fig 6) extending in the first direction (z-direction Fig 6) in the first stacked body (shown in annotated Fig 6),
a second columnar body (shown in annotated Fig 6) extending in the first direction (z-direction Fig 6) in the second stacked body (shown in annotated Fig 6), and
a third columnar body (shown in annotated Fig 6) extending in the first direction (z-direction) in the third stacked body (shown in annotated Fig 6),
wherein the inner side of the first semiconductor portion (82) is filled with the first insulating portion (84) in the first columnar body (shown in annotated Fig 6) in the first stacked body (shown in annotated Fig 6),
wherein the first insulating portion (84) of the second columnar body (shown in annotated Fig 6) in the second stacked body (shown in annotated Fig 6) has a space (90) in the first insulating portion (84), and
wherein the inner side of the first semiconductor portion (82) is filled with the first insulating portion (84) in the third columnar body (shown in annotated Fig 6) in the third stacked body (shown in annotated Fig 6).
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Regarding Claim 7, Uchimura et al discloses the limitations of claim 1 as explained above. Uchimura et al further discloses
wherein the first insulating portion (84) forms a hollow portion (shown in Fig 6) hollowed on a side closer to the second end (bottom end shown in Fig 6) than the first semiconductor portion (82) at the first end (top end shown in Fig 6), and
wherein the second conductive layer (86) is buried in the hollow portion (shown in Fig 6) to be connected to an inner surface of the first semiconductor portion (82).
Regarding Claim 8, Uchimura et al discloses the limitations of claim 2 as explained above. Uchimura et al further discloses
wherein the first insulating portion (84) of the first stacked body (shown in annotated Fig 6) is separated from the first insulating portion (84) of the second stacked body (shown in annotated Fig 6).
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Regarding Claim 11, Uchimura et al discloses the limitations of claim 1 as explained above. Uchimura et al further discloses
wherein the semiconductor memory device (NAND memory [0080] Fig 6) is a nonvolatile device (NAND).
Regarding Claim 12, Uchimura et al discloses the limitations of claim 1 as explained above. Uchimura et al further discloses
further comprising a memory cell array (memory cell array 10 [0056] Fig 1).
Regarding Claim 13, Uchimura et al discloses the limitations of claim 1 as explained above. Uchimura et al further discloses
wherein the first insulating layer (72) is formed of silicon oxide (may contain silicon oxide [0102]).
Regarding Claim 14, Uchimura et al discloses the limitations of claim 1 as explained above. Uchimura et al further discloses
wherein the first semiconductor portion (82) includes a semiconductor channel (in the broadest reasonable interpretation, the semiconductor portion 82 can be considered to be a semiconductor channel in that it occupies the center portion of the memory pillar MP).
Regarding Claim 15, Uchimura et al discloses the limitations of claim 1 as explained above. Uchimura et al further discloses
herein the first semiconductor portion (82) is formed of silicon (82 may be a silicon (Si) layer [0108]).
Regarding Claim 16, Uchimura et al discloses the limitations of claim 1 as explained above. Uchimura et al further discloses
wherein the first conductive layer (70) is plate shaped (may be a plate-like structure [0101]).
Regarding Claim 17, Uchimura et al discloses the limitations of claim 1 as explained above. Uchimura et al further discloses
wherein the first conductive layer (70) is formed on tungsten (may contain tungsten W [0101]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Uchimura et al (US 2021/0082940) in view of Oike (US 2020/0075618).
Regarding Claim 1, Uchimura et al discloses the limitations of claim 1 as explained above.
Uchimura et al does not directly disclose
wherein the first conductive layer is formed of polysilicon.
Oike, in the related art of semiconductor devices that include three-dimensional memory devices, discloses
wherein the first conductive layer (upper conductive layer 13 [0030]) is formed of polysilicon (polysilicon [0030]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Uchimura et al to include a first conductive layer formed of polysilicon as taught by Oike in order to have a conductive layer function as a common source line [0030]. Further, a person of ordinary skill in the art would have recognized that having a conductive layer formed of polysilicon would be a simple substitution of one known element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Iwai et al (US 2020/0251488) which discloses a vertical NAND device with a semiconductor layer [0112], and Tsutsumi et al (US 2020/0251489) which discloses and alternating stack of insulating layers and conductive layers in a three-dimensional memory device [0004].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID PAUL SEDOROOK whose telephone number is (571)272-4158. The examiner can normally be reached Monday - Friday 7:30 am -5pm.
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812