DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement (IDSs) submitted on December 23, 2025 and January 13, 2026 are in compliance with the provisions of 37 CFR 1.97 and 1.98. Accordingly, the IDSs are being considered by the Examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-4, 6, 7, and 9-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the Applicant), regards as the invention.
Regarding amended independent claim 1, lines 12-15 recite: “fourth wires, one of which connects the first semiconductor switching element and the control chip, and an other of which connects the second semiconductor switching element and the control chip, and extending in a direction perpendicular to a direction in which the first semiconductor switching element and the second semiconductor switching element are arranged.” This recited language used to define the invention is ambiguous and clarification and/or correction are/is required to make its meaning clear and precise whereby the metes and bounds of the claimed invention can be ascertained. No new matter may be added. For example, it is unclear whether the recited “fourth wires” only includes two wires “one of which connects the first semiconductor switching element and the control chip, and an other of which connects the second semiconductor switching element and the control chip” or if “fourth wires” includes more than two wires. As another example, if there are more than two “fourth wires”, then it is unclear whether all of the “fourth wires” “extend[] in a direction perpendicular to a direction in which the first semiconductor switching element and the second semiconductor switching element are arranged” or just the “one” and “an other” of the “fourth wires” “extend[] in a direction perpendicular to a direction in which the first semiconductor switching element and the second semiconductor switching element are arranged.” For purpose of examination, the Examiner is interpreting lines 12-15 of claim 1 as reciting: “fourth wires, one of which connects the first semiconductor switching element and the control chip, and an other of which connects the second semiconductor switching element and the control chip, and all of the fourth wires extending in a direction perpendicular to a direction in which the first semiconductor switching element and the second semiconductor switching element are arranged” because of this ambiguity. Claims 2-4, 6, 7, and 9-11 are also indefinite because they depend from amended independent claim 1.
Regarding claim 9, lines 1-3 recite: “wherein an extending direction of the fourth wires is perpendicular to an extending direction of the plurality of first wires.” This recited language used to define the invention is ambiguous and clarification and/or correction are/is required to make its meaning clear and precise whereby the metes and bounds of the claimed invention can be ascertained. No new matter may be added. For example, it is unclear whether the recited “an extending direction of the fourth wires” is the same “extending in a direction perpendicular to a direction in which the first semiconductor switching element and the second semiconductor switching element are arranged” recited in amended independent claim 1 or a different extending direction. As another example, it is unclear if “fourth wires” only includes two wires “one of which connects the first semiconductor switching element and the control chip, and an other of which connects the second semiconductor switching element and the control chip” or if “fourth wires” includes more than two wires. As an additional example, it is unclear whether all of “the fourth wires” only extend in “an extending direction” or if only at least one of “the fourth wires” must extend in “an extending direction”. As a further example, it is unclear whether all of “the plurality of first wires” only extend in “an extending direction” or if only at least one of “the plurality of first wires” must extend in “an extending direction”. For purpose of examination, the Examiner is interpreting lines 1-3 of claim 9 as reciting: “wherein the extending direction of all of the fourth wires is perpendicular to an extending direction of all of the plurality of first wires” because of this ambiguity.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4, 6, 7, and 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over US 2014/0184303 A1 (Hasegawa) in view of US 2021/0327781 A1 (Isozaki) and US 2013/0155745 A1 (Tanaka).
Regarding claim 1, Hasegawa discloses, A semiconductor device (semiconductor device (100); FIG. 2; [0030]) comprising:
a first semiconductor switching element (first semiconductor switching element (7); FIG. 2; [0032]) composed of silicon ([0146]);
a second semiconductor switching element (second semiconductor switching element (1); FIG. 2; [0032]) having a rectangular shape (FIG. 2) with a long side facing the first semiconductor switching element (7) (annotated FIG. 2, below) in plan view (FIG. 2 is a plan view), having an area smaller than that of the first semiconductor switching element (7) (area of second semiconductor switching element (1) is smaller than the area of first semiconductor switching element (1); FIG. 2) in plan view (FIG. 2), and composed of a wide bandgap semiconductor ([[0146]—silicon carbide (SiC) and [0011] of Applicant’s specification—wide bandgap semiconductor includes silicon carbide (SiC));
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a plurality of first wires (plurality of first wires (16); FIG. 2; [0041]) connecting the first semiconductor switching element (7) and the second semiconductor switching element (1), and composed of silver or gold ([[0125] and [0126]);
a control chip (control chip (18); FIG. 2; [0046]) configured to control the first semiconductor switching element (7) and the second semiconductor switching element (1).
But, Hasegawa does not appear to explicitly disclose,
the plurality of first wires being 40 µm or less in diameter; and
fourth wires, one of which connects the first semiconductor switching element and the control chip, and an other of which connects the second semiconductor switching element and the control chip, and extending in a direction perpendicular to a direction in which the first semiconductor switching element and the second semiconductor switching element are arranged1.
However, in analogous art, Isozaki discloses, a semiconductor device (semiconductor device (1); FIG. 1; [0025]) having a first semiconductor switching element (first semiconductor switching element (4); annotated FIG. 1, below; [0031]) and second semiconductor switching element (second semiconductor switching element (4); annotated FIG. 1, below; [ 0031]) connected together by one or more of plurality of wires (plurality of wires (W1-W6); FIG. 1; [0043]). Isozaki also discloses that plurality of wires (W1-W6) may be comprised of gold ([0043]) and have a diameter of 25 µm or greater and 600 µm or less. Isozaki additionally discloses that connection points (annotated FIG. 1, below) of wires (e.g., W2 and W5) may be placed along an arrangement direction in an alternate manner.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hasegawa and Isozaki before him/her that the gold plurality of first wires (16) of Hasegawa can be 40 µm or less in diameter, as taught by Isozaki, because the recited diameter range of 40 µm or less overlaps with the diameter range of 25 µm or greater and 600 µm or less disclose by Isozaki. See, MPEP 2144.05(I)—In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists.
But, Hasegawa in view of Isozaki does not appear to explicitly disclose, fourth wires, one of which connects the first semiconductor switching element and the control chip, and an other of which connects the second semiconductor switching element and the control chip, and extending in a direction perpendicular to a direction in which the first semiconductor switching element and the second semiconductor switching element are arranged.
However, in analogous art, Tanaka discloses, that it is well-known that in a semiconductor device (semiconductor device (100A); FIG. 16; [0138]) one of fourth wires (fourth wires (13) and (13A); FIG. 16; [0042] and [0140]) can be predicably formed to connect a first semiconductor switching element (first semiconductor switching element (7); FIG. 16; [0033]) and control chip (control chip (18); FIG. 16; [0042]) and an other of which can be predicably formed to connect a second semiconductor switching element (second semiconductor switching element (1); FIG. 16; [0033]) and control chip (18). Tanaka also discloses that it is well-known that fourth wires (13 and 13A) extend in a direction (the plane defined by X Axis and Y Axis, annotated FIG. 16, below) perpendicular to a direction (Z Axis, annotated FIG. 16, below) in which first semiconductor switching element (7) and second semiconductor switching element (1) are arranged (first and second semiconductor switching elements (1) and (7) are arranged with respect to the Z-Axis direction so as not to be on top of each other).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hasegawa, Isozaki, and Tanaka before him/her that it is well-known that semiconductor device (100) of Hasegawa in view of Isozaki could be predicably formed to include fourth wires, one of which connects the first semiconductor switching element (7) and the control chip (18), and an other of which connects the second semiconductor switching element (1) and the control chip (18), as taught by Tanaka, and extending in a direction perpendicular to a direction in which the first semiconductor switching element (7) and the second semiconductor switching element (1) are arranged, as also taught by Tanaka, with no change in the function of the plurality of fourth wires because they would still connect first semiconductor switching element (7) and second semiconductor switching element (1) to control chip (18) or the function of elements (1) and (7) because they would still act as semiconductor switching devices. See, MPEP 2143(A)—Combining Prior Art Elements According to Known Methods to Yield Predicable Results.
The Examiner also notes that having separate fourth wires, one between control chip (18) and first semiconductor switching element (7) and one between control chip (18) and second semiconductor switching element (1) of Hasegawa in view of Isozaki would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, based on the teaching of Tanaka, because it would allow control chip (18) to independently control first semiconductor switching element (7) and second semiconductor switching element (1). See, MPEP 2144(I) —The rationale to modify or combine the prior art does not have to be expressly stated in the prior art; the rationale may be expressly or impliedly contained in the prior art or it may be reasoned from knowledge generally available to one of ordinary skill in the art, established scientific principles, or legal precedent established by prior case law. Please also see, MPEP 2144(IV)—The reason or motivation to modify the reference may often suggest what the inventor has done, but for a different purpose or to solve a different problem. It is not necessary that the prior art suggest the combination to achieve the same advantage or result discovered by applicant.
Regarding claim 2, Hasegawa in view of Isozaki and Tanaka discloses, The semiconductor device (100) according to claim 1, wherein in plan view (FIG. 2), a longitudinal direction (annotated FIG. 2, above) of the second semiconductor switching element (1) is perpendicular to an extending direction (annotated FIG. 2, above) of the plurality of first wires (16).2
Regarding claim 3, Hasegawa in view of Isozaki and Tanaka discloses, The semiconductor device (100) according to claim 1, wherein connection points (annotated FIG. 1, above) of the plurality of first wires (16) with the first semiconductor switching element (7) and the second semiconductor switching element (1) are placed along an arrangement direction of the plurality of first wires (16) in an alternate manner (annotated FIG. 1, above).3
Regarding claim 4, Hasegawa in view of Isozaki and Tanaka discloses, The semiconductor device (100) according to claim 1, further comprising:
a sealing resin (sealing resin (RP); FIG. 2; [0044], all of Hasegawa) having a resin gate trace (resin gate trace (G1); FIG. 2; [0056], all of Hasegawa) and covering the first semiconductor switching element (7), the second semiconductor switching element (1), and the control chip (18).
But, Applicant may argue that Hasegawa in view of Isozaki and Tanaka does not appear to explicitly disclose, wherein loop heights of the plurality of first wires increase in order of increasing distance from the resin gate trace.
However, Hasegawa discloses that it is well-known that plurality of first wires (16) and wire (wire (15); FIG. 22; [0041]) can be predicably formed to have loop heights (annotated FIG. 22, below) that increase in order of increasing distance from connecting points (annotated FIG. 22) between semiconductor switching elements (semiconductor switching elements (4 and 10); FIG. 22; [0032]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hasegawa, Isozaki, and Tanaka before him/her that loop heights of the plurality of first wires (16) of Hasegawa in view of Isozaki and Tanaka can be predicably formed to increase in order of increasing distance from the resin gate trace (G1) at their connecting points (annotated FIG. 2, above), as taught by Hasegawa, with no change in the function of plurality of first wires (16) because they would still connect first semiconductor switching element (7) and second semiconductor switching element (1). See, MPEP 2143(A), above.
Regarding claim 6, Hasegawa in view of Isozaki and Tanaka discloses, The semiconductor device (100) according to claim 1, further comprising:
a first lead frame (lead frame (T1); FIG. 2; [0032], all of Hasegawa) on which the first semiconductor switching element (7) and the second semiconductor switching element (1) are mounted;
a second lead frame (second lead frame (T2); FIG. 2; [0032], all of Hasegawa); and
a plurality of second wires (plurality of second wires (17); FIG. 2; [0041], all of Hasegawa) connecting the first semiconductor switching element (7) mounted on the first lead frame (T1) and the second lead frame (T2).
But, Applicant may argue that Hasegawa in view of Isozaki and Tanaka does not appear to explicitly disclose, the plurality of second wires being 40 µm or less in diameter.
However, in analogous art, Isozaki discloses, a semiconductor device (semiconductor device (1); FIG. 1; [0025]) having a first semiconductor switching element (first semiconductor switching element (4); annotated FIG. 1, above; [0031]) and second semiconductor switching element (second semiconductor switching element (4); annotated FIG. 1, above; [ 0031]) connected together by one or more of plurality of wires (plurality of wires (W1-W6); FIG. 1; [0043]). Isozaki also discloses that one or more of wires (W1-W6) are connected between lead frame (lead frame (60); FIG. 1; [0036]) and first and second semiconductor switching elements (4). Isozaki additionally discloses that plurality of wires (W1-W6) may be comprised of gold ([0043]) and have a diameter of 25 µm or greater and 600 µm or less.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Hasegawa, Isozaki, and Tanaka before him/her that the plurality of second wires (17) of Hasegawa can be 40 µm or less in diameter, as taught by Isozaki, because the recited diameter range of 40 µm or less overlaps with the diameter range of 25 µm or greater and 600 µm or less disclose by Isozaki. See, MPEP 2144.05(I), above.
Regarding claim 7, Hasegawa in view of Isozaki and Tanaka discloses, The semiconductor device (100) according to claim 1, further comprising:
a first lead frame (lead frame (T1); FIG. 2; [0032], all of Hasegawa) on which the first semiconductor switching element (7) and the second semiconductor switching element (1) are mounted;
a second lead frame (second lead frame (T2); FIG. 2; [0032], all of Hasegawa); and
a third wire (third wire (17); FIG. 2; [0041], all of Hasegawa) connecting at least one of between the first semiconductor switching element (7) mounted on the first lead frame (T1) and the second lead frame (T2) or between the first semiconductor switching element and the second semiconductor switching.
But, Applicant may argue that Hasegawa in view of Isozaki and Tanaka does not appear to explicitly disclose, and having a diameter larger than that of the first wires.
However, there are a finite number of predicable solutions regarding the diameter of third wire (17) of Hasegawa in view of Isozaki relative to first wires (16)—i.e., the diameter of third wire (17) can be: (i) the same, (ii) smaller, or (iii) larger than that of the first wires (16)—and, absent unexpected results, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to try each of them, one of which is recited in claim 7. See, MPEP 2143(E)—“Obvious To Try”—Choosing From A Finite Number Of Identified, Predicable Solutions, With A Reasonable Expectation Of Success.
The Examiner also notes that the larger diameter of third wire (17) of Hasegawa in view of Isozaki would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention because it would allow third wire (17) to carry more current than first wires (16). See, MPEP 2144(I) and 2144(IV), above.
Regarding claim 9, Applicant may argue that Hasegawa in view of Isozaki and Tanaka does not appear to explicitly disclose, wherein an extending direction of the fourth wires is perpendicular to an extending direction of the plurality of first wires4.
However, there are a finite number of predicable solutions regarding an extending direction of the fourth wires of Hasegawa in view of Isozaki and Tanaka relative to an extending direction of the plurality of first wires (16)—i.e., an extending direction of the fourth wires can be: (i) parallel to an extending direction of the plurality of first wires (16), (ii) perpendicular to an extending direction of the plurality of first wires (16), or (iii) at an angle that is neither parallel nor perpendicular to an extending direction of the plurality of first wires (16)—and, absent unexpected results, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to try each of them, one of which is recited in claim 9. See, MPEP 2143(E), above.
The Examiner also notes that an extending direction of the fourth wires is perpendicular to an extending direction of the plurality of first wires (16) is a result effective variable that would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select to optimize a length of the fourth wires and/or first wires (16) to be as short as possible to minimize characteristics of the fourth wires and/or first wires (16) such a resistance and/or impedance. Please see, MPEP 2144.05(II).
Regarding claim 10, Hasegawa in view of Isozaki and Tanaka discloses, The semiconductor device (100) according to claim 1, wherein the control chip (18) directly faces (FIG. 2) the first semiconductor switching element (7) and the second semiconductor switching element (1).5
Regarding claim 11, Hasegawa in view of Isozaki and Tanaka discloses, The semiconductor device (100) according to claim 1, wherein
the control chip (18) directly faces the first semiconductor switching element (7) and the second semiconductor switching element (1), and
the direction in which the first semiconductor switching element (7) and the second semiconductor switching element (1) are arranged extends from a center of the first semiconductor switching element (7) in plan view (FIG. 2 of Hasegawa is a plan view, first semiconductor switching element (7) has a center) to a center of the second semiconductor switching element (1) in plan view (FIG. 2 of Hasegawa is a plan view, second semiconductor switching element (1) has a center) (annotated FIG. 2, above).6
Response to Amendments and Arguments
Applicant’s cancelation of dependent claim 5 in the Amendment filed on March 2, 2026 (hereinafter the “Reply”) has overcome the objection to claim 5 in the Office Action dated December 2, 2025 (hereinafter the “Office Action”). Applicant’s amendment of independent claim 1 and arguments with respect thereto on pages five (5)-seven (7) of the Reply regarding the rejection of claims 1-8 under 35 U.S.C. 103 in the Office Action have been fully considered. However, they are not deemed persuasive, as detailed above in this Final Office Action and for at least the reasons discussed below.
For example, page six (6) of the Reply states:
Starting on page 12, the Office Action rejects claim 8, asserting that Hasegawa, Isozaki, and Tanaka suggest "fourth wires, one of which connects the first semiconductor switching element and the control chip, and an other of which connects the second semiconductor switching element and the control chip, and extending in a direction perpendicular to a direction in which the first semiconductor switching element and the second semiconductor switching element are arranged" based on FIG. 16 of Tanaka. Notably, the Office Action asserts that "a direction in which the first semiconductor switching element and the second semiconductor switching element are arranged" as claimed could be considered to be a direction along the "Z Axis" in an annotated version of FIG. 16 of Tanaka (herein "annotated FIG. 16 of Tanaka"). See pages 13 and 14 of the Office Action.
Applicant respectfully submits that one of ordinary skill in the art would consider the interpretation set forth in the rejection of claim 8 to be unreasonable in light of the present disclosure. To this end, the features of claim 8 are supported by FIG. 9 and paragraph 0038 of the present specification. Considered in light of FIG. 9 and paragraph 0038 of the present specification, Applicant respectfully contends that one of ordinary skill in the art would not consider Hasegawa or Tanaka's semiconductor elements 1 and 7 to be arranged in a direction along the "Z Axis" in annotated FIG. 16 of Tanaka. Rather, the various semiconductor elements 1 and 7 in annotated FIG. 16 of Tanaka appear to be arranged along a column direction and a row direction of a 2-by-6 matrix in directions along the "X Axis" and "Y Axis." Although directions in which the first semiconductor element and the second semiconductor element are arranged are a column direction and a row direction of a 2-by-6 matrix in Tanaka, these directions are not perpendicular to an extending direction of the line 13.
The Examiner respectfully disagrees with these arguments. For example, Applicants above-quoted remarks regarding Fig. 9 and paragraph [0038] of the application appear to be reading limitations from the specification into amended independent claim 1 which now includes the recited limitations of canceled dependent claim 8. The Examiner respectfully submits that reading limitations from the specification into the claims is improper and that amended independent claim 1 is not limited to what is shown in FIG. 9 and paragraph [0038] of Applicant’s applicant. Please see, MPEP 2145(IV)—Arguing Limitations Which Are Not Claimed. The Examiner also respectfully notes that amended independent claim 1 currently contains no recited language that limits it to only the structure disclosed in Fig. 9 and described in paragraph [0038].
As another example, the Examiner respectfully notes that the rejection of amended independent claim 1 is not based on first semiconductor element (7) and second semiconductor element (1) being “arranged in a direction along the ‘Z-Axis’ in annotated FIG. 16 of Tanaka” (emphasis added), as asserted in Applicant’s above-quoted remarks. Rather, the rejection of amended independent claim 1 is based on first semiconductor element (7) and second semiconductor element (1) being arranged with respect to the Z-Axis direction in annotated FIG. 16 of Tanaka so that they do not overlap. The Examiner respectfully submits that just because first semiconductor element (7) and second semiconductor element (1) may be also arranged with respect to the X-Axis and Y-Axis of Hasegawa in view of Isozaki and Tanaka, as argued by Applicant, this does not preclude first semiconductor element (7) and second semiconductor element (1) from also being arranged with respect to the Z-Axis, as originally noted in the Office Action and also noted again in this Final Office Action. The Examiner also respectfully notes that amended independent claim 1 currently contains no recited language that limits such an arrangement of first semiconductor element (7) and second semiconductor element (1) with respect to the Z-axis.
As an additional example, regarding the recitation of directions in amended independent claim 1, paragraph [0009] of Applicant’s application regarding directions states that such directions “may not necessarily coincide with the positions or directions at the time of implementation.” The Examiner respectfully submits that this language suggests that Applicant may intend the meaning of the recited limitation of “perpendicular” in amended independent claim 1 to read on more than just a 90 degree angle between an extending direction of first semiconductor element with respect to an extending direction of second semiconductor element. For clarity of the written record, the Examiner respectfully requests that Applicant please clarify if the recited limitation of “perpendicular” in amended independent claim 1 is limited to only a 90 degree angle between an extending direction of first semiconductor element with respect to an extending direction of second semiconductor element or if it reads on additional angles other than a 90 degree angle between an extending direction of first semiconductor element with respect to an extending direction of second semiconductor element.
As another example, page seven (7) of the Reply states:
Furthermore, Applicant notes that paragraph 0038 of the present specification states: "the length of the gate wire 6 can be shortened, so disconnection of the gate wire 6 during injection of the sealing resin 8 can be suppressed." Applicant respectfully submits that this benefit of the features of claim 1 is not disclosed in any of the cited references. As such, the cited references fail to render obvious the features of claim 1 for at least this additional reason.
The Examiner respectfully notes that this above-quoted language appears to be concerned with a result effective variable (i.e., the length of gate wire 6) and its consequence with respect to disconnection thereof during injection of sealing resin 8. However, as noted above in this Final Office Action, the Examiner respectfully submits that there are other result effective variables that would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select to optimize a length of the recited wires of amended independent claim 1 to be as short as possible to minimize characteristics of these wires such a resistance and/or impedance. Please see, MPEP 2144.05(II).
As an additional example, page seven (7) of the Reply states:
New claims 9-11 recite additional protection to which Applicant is entitled. The specification and drawings support the features of new claims 9-11. See, e.g., FIG. 9 and the corresponding description in the original specification. Applicant respectfully submits that new claims 9-11 are allowable at least by virtue of their dependence on amended allowable independent claim 1, and for the additional features recited.
For instance, Tanaka fails to disclose that an extending direction of the fourth wires is perpendicular to an extending direction of the plurality of first wires. See claim 9.
Further, Tanaka fails to disclose "the control chip directly faces the first semiconductor switching element and the second semiconductor switching element" as recited in new claims 10 and 11.
Additionally, claim 11 further recites "the direction in which the first semiconductor switching element and the second semiconductor switching element are arranged extends from a center of the first semiconductor switching element in plan view to a center of the second semiconductor switching element in plan view." Applicant respectfully submits that Tanaka fails to disclose that any direction extending "from a center of the first semiconductor switching element in plan view to a center of the second semiconductor switching element in plan view" is perpendicular to the line 13.
The Examiner respectfully disagrees, as detailed above in this Final Office Action. Also, the Examiner respectfully notes that each of new claims 9-11 recites directional limitations (e.g., “extending direction” and “directly faces”). As noted above, paragraph [0009] of Applicant’s application regarding directions states that such directions “may not necessarily coincide with the positions or directions at the time of implementation.” Additionally, the Examiner respectfully notes that new claims 9-11 are rejected based on the combination of Hasegawa in view of Isozaki and Tanaka, not just Tanaka, as argued by Applicant in the above-quoted remarks.
For clarity of the written record, the Examiner respectfully notes that Applicant’s Reply has failed to specifically address any of the detailed rejections of dependent claims 2-4, 6, and 7 under 35 U.S.C. 103 in the Office Action. Page seven (7) of the Reply merely alleges that dependent claims 2-4, 6, and 7 are patentable because of their dependence on amended independent claim 1.
Notwithstanding the above, to advance prosecution, the Examiner respectfully requests that Applicant please consider a telephone interview with the Examiner to discuss proposed claim amendments to at least independent claim 1 and dependent claims 9 to overcome rejection of claims 1-4, 6, 7, and 9-11 under 35 USC 112(b), and independent claims 1 to overcome the rejection of claims 1-4, 6, 7, and 9-11 under 35 U.S.C. 103 prior to submitting a written response to this Final Office Action. The Examiner would welcome such a proposed discussion of these claim amendments and is available at the number provided below.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Erik A. Anderson whose telephone number is (703) 756-1217. The Examiner can normally be reached Monday-Friday 8:30 a.m.-4:30 p.m. (Pacific Time Zone).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, William B. Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/ERIK A. ANDERSON/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
1 Please see the rejection of amended independent claim 1 under 35 U.S.C. 112(b), above, for how this recited language of amended independent claim 1 is being interpreted for purpose of examination. Please also see, for example, paragraph [0009] of Applicant’s application regarding directions, such as “perpendicular”, recited in amended independent claim 1, which states that such directions “may not necessarily coincide with the positions or directions at the time of implementation.”
2 Please also see, for example, paragraph [0009] of Applicant’s application regarding directions, such as recited in claim 2, which states that such directions “may not necessarily coincide with the positions or directions at the time of implementation.”
3 Please also see, for example, paragraph [0009] of Applicant’s application regarding directions, such as recited in claim 3, which states that such directions “may not necessarily coincide with the positions or directions at the time of implementation.”
4 Please see the rejection of amended independent claim 9 under 35 U.S.C. 112(b), above, for how this recited language of amended independent claim 9 is being interpreted for purpose of examination. Please also see, for example, paragraph [0009] of Applicant’s application regarding directions, such as “perpendicular”, recited in new claim 9, which states that such directions “may not necessarily coincide with the positions or directions at the time of implementation.”
5 Please also see, for example, paragraph [0009] of Applicant’s application regarding directions, such as “directly faces” recited in new claim 10, which states that such directions “may not necessarily coincide with the positions or directions at the time of implementation.”
6 Please also see, for example, paragraph [0009] of Applicant’s application regarding directions, such as recited in new claim 11, which states that such directions “may not necessarily coincide with the positions or directions at the time of implementation.”
Prosecution Insights