Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office acknowledges receipt of the following item(s) from the Applicant:
Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d), However, none of the certified copies of the priority documents have been received.
Claims 1-29 are pending in the application.
Election/Restrictions
Applicant’s election without traverse of Group III (claims 22-29) is acknowledged.
Therefore, claims 1-21 are withdrawn from further consideration.
Since the applicant makes an election without traverse of Group III (claims 22-
29). Therefore, the arguments is not needed.
Claim Objections
Claim(s) 23-29 objected to because of the following informalities:
Regarding claim 23: change “counting a number of times of the changing” to “comprising counting a number of times of the changing the verification voltage” to have a more clear and concise connection to the depended upon claim 22.
Regarding claim 24: change “corresponding to the number of times” to “corresponding to the number of times of the changing the verification voltage” to have a more clear and concise connection to the depended upon claim 23.
Regarding claims 25 and 26: change “the generating comprises” to “the generating of program pulses comprises” to have a more clear and concise connection to the depended upon claim 24.
Regarding claim 27: change “corresponding to the number of times” to “corresponding to the number of times of the changing the verification voltage” to have a more clear and concise connection to the depended upon claim 23.
Regarding claims 28 and 29: change “the generating comprises” to “the generating of erase pulses comprises” to have a more clear and concise connection to the depended upon claim 27.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 22 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 20210295927 A1).
Regarding claim 22: Park discloses semiconductor memory device (1100, FIG. 1) comprising: providing a word line with a verification voltage (verify voltages to selected word line, par. 109, FIG. 8) having a target level (verify voltage levels, e.g. VPV2 and VPV4, par. 109, FIG. 8); detecting a change in an output of a page buffer that senses a bit line of a memory cell connected to the word line (page buffer senses bit line current change, par. 116); and changing the verification voltage (changing verify voltages, FIG. 8) by a preset voltage level (voltage level difference between program states, par. 109) until the change is detected (detected based on a threshold voltage, par. 116).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20210295927 A1) in view of Liu et al. (US 20240203512 A1).
Regarding claim 23: Park does not disclose counting a number of times of the changing.
Liu does disclose a memory apparatus for smart verify for program-verify iterations (100, FIG. 1) comprising counting a number of times of the changing (smart-verify loop counter counts number of incremented program-verify iterations occur, par. 122).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Park with the count configuration of Liu to allow the system to monitor the number of verify iterations performed for the operation.
Regarding claim 24: Park does not disclose selecting a step size corresponding to the number of times; and generating a program pulse based on the selected step size.
Liu does disclose a memory apparatus for smart verify for program-verify iterations (100, FIG. 1) comprising selecting a step size (ΔVS, par. 123) corresponding to the number of times (ΔVS can be related to the counted number of changes SVloopn, par. 123-124); and generating a program pulse based on the selected step size (acquired smart-verify voltage VAN is used as a reference for programming memory cells such as program pulses, par. 123-125).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Park with the configuration of Liu to generate an appropriate program pulse for the following iteration based on the previously determined iteration’s step count.
Claim(s) 25-26 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20210295927 A1) in view of Liu et al. (US 20240203512 A1), in further view of Nobunaga (US 20090238006 A1).
Regarding claims 25 and 26: Park and Liu do not disclose the generating comprises increasing at least one of a voltage level of the program pulse and duration of the program pulse as the step size is greater.
Nobunaga does disclose a memory device for adjusting programming voltage pulses in response to a number of failures (100, FIG. 1) wherein the generating comprises increasing at least one of a voltage level of the program pulse (following program pulses can be increasing in magnitude, FIG. 2) and duration of the program pulse (following program pulses can be increasing in duration, FIG. 2) as the step size is greater (based on the ΔV level size, FIG. 2).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Park and Liu with the configuration of Nobunaga to allow the following program pulses of the operation to be modified based on the step size voltage between the iterations.
Claim(s) 27-29 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20210295927 A1) in view of Liu et al. (US 20240203512 A1), in further view of Huang (US 20220223210 A1).
Regarding claim 27: Park and Liu do not disclose selecting a step size; and generating an erase pulse based on the selected step size.
Huang does disclose an architecture for memory operation (100, FIG. 1) comprising: selecting a step size corresponding to the number of times (step size increases loop continues, FIG. 4 and 8); and generating an erase pulse based on the selected step size (erase pulses applied incrementally as ISPE step increases, par. 3, FIG. 4).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Park and Liu with the configuration of Huang to allow the system to generate erase pulses based on step size corresponding to the number of times the verification voltage is changed in the program verify operation.
Regarding claims 28 and 29: Park and Liu do not disclose the generating comprises increasing at least one of a voltage level of the erase pulse and duration of the erase pulse as the step size is greater.
Huang does disclose an architecture for memory operation (100, FIG. 1) comprising: the generating comprises increasing at least one of a voltage level of the erase pulse (erase pulses of increasing levels, FIG. 4) and duration of the erase pulse as the step size is greater (greater ISPE steps results in erase pulse increasing further, FIG. 4).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Park and Liu with the configuration of Huang to allow the following erase pulses of the operation to be modified based on the step size voltage between the iterations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY THINH TANG whose telephone number is (571)272-6845. The examiner can normally be reached Monday-Friday 7:30-5:00 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at (571)272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHONY THINH TANG/Examiner, Art Unit 2827
/AMIR ZARABIAN/Supervisory Patent Examiner, Art Unit 2827
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