DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
2. Claims 1, 12, 14-15 and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Farooq et al. U.S. Patent Application Publication 2023/0230901 A1 (the ‘901 reference, of record and cited in a related International Search Report).
The reference discloses in Fig. 2, para [26] (paragraph(s) [0026]) and other text an integrated circuit, a method of fabricating an integrated circuit and an integrated circuit (IC) package as claimed.
Referring to claim 1, the ‘901 reference discloses an integrated circuit (IC), comprising:
a circuit layer (126/127);
a plurality of first metallization layers (128) disposed on a first side of the circuit layer and coupled to the circuit layer (126/127);
a plurality of second metallization layers (124) disposed on a second side of the circuit layer opposite to the first side and coupled to the circuit layer (126/127);
a stiffening layer (thick silicon 122) disposed on one (124) of the plurality of first metallization layers (128) and the plurality of second metallization layers (124); and
a first via (110) extending through the stiffening layer (122) to couple the one (124) of the plurality of first metallization layers and the plurality of second metallization layers to a first contact (Cu pillar and/or solder bonding (pad) ~104, para [44]) on the stiffening layer (122).
Referring to claim 12, the reference further discloses that the stiffening layer (122) comprises silicon (para [26]).
Referring to claim 14, the reference further discloses a second contact (121) coupled to the other one (128) of the plurality of first metallization layers (128) and the plurality of second metallization layers (124) and configured to couple the circuit layer (126/127) to an external circuit ((via or) packaging substrate 120, para [26, 34]).
Referring to claim 15, for the device detailed above for claim 1, the reference further discloses that the IC is integrated into an integrated circuit package (including packaging substrate 120, para [26, 34]).
Referring to claim 17 and using the same reference characters, interpretations, and citations as detailed above for claim 1 where applicable, the reference discloses a method of fabricating an integrated circuit (IC), the method comprising:
forming a circuit layer (126/127, Fig. 2);
forming a plurality of first metallization layers (128) on a first side of the circuit layer;
forming a plurality of second metallization layers (124) on a second side of the circuit layer opposite to the first side;
disposing a stiffening layer (122) on one (124) of the plurality of first metallization layers (128) and the plurality of second metallization layers (124); and
forming a first via (110) extending through the stiffening layer (122) from a first side of the stiffening layer adjacent to the one (124) of the plurality of first metallization layers and the plurality of second metallization layers to a first contact (~104) on a second side of the stiffening layer (122).
Referring to claim 18 and using the same reference characters, interpretations, and citations as detailed above for claim 1 where applicable, the reference discloses an integrated circuit (IC) package comprising:
a first package substrate (“underlying top die” 102, Fig. 2, in an upside-down view, and note that the IC package is operational in any orientation in space); and
an IC comprising:
a circuit layer (126/127);
a plurality of first metallization layers (128) disposed on a first side of the circuit layer and coupled to the circuit layer (126/127);
a plurality of second metallization layers (124) disposed on a second side of the circuit layer opposite to the first side and coupled to the circuit layer (126/127);
a stiffening layer (122) disposed on one (124) of the plurality of first metallization layers (128) and the plurality of second metallization layers (124); and
a first via (110) extending through the stiffening layer (122) from a first side of the stiffening layer adjacent to the one (124) of the plurality of first metallization layers and the plurality of second metallization layers to a first contact (~104) on a second side of the stiffening layer (122),
wherein the first contact (~104) is coupled to the first package substrate (102).
Alternately, referring to claim 18 and using the same reference characters, interpretations, and citations as detailed above for claim 1 where applicable, the reference discloses an integrated circuit (IC) package comprising:
a first package substrate (120, Fig. 2); and
an IC comprising:
a circuit layer (126/127);
a plurality of first metallization layers (upper metallization layers of thick wiring 128 (~128)) disposed on a first side of the circuit layer (126/127) and coupled to the circuit layer (126/127);
a plurality of second metallization layers (124) disposed on a second side of the circuit layer opposite to the first side and coupled to the circuit layer (126/127);
a stiffening layer (lowest layer of the thick wiring 128) disposed on one (said upper metallization layers of thick wiring 128) of the plurality of first metallization layers (~128) and the plurality of second metallization layers (124); and
a first via (not labeled) extending through the stiffening layer (said lowest layer of the thick wiring 128) from a first side of the stiffening layer adjacent to the one of the plurality of first metallization layers (~128) and the plurality of second metallization layers (124) to a first contact (121, para [26]) on a second side of the stiffening layer,
wherein the first contact (121) is coupled to the first package substrate (120).
Referring to claim 19, the reference further discloses:
a second contact (110/104, para [26, 44]) coupled to the other one (124) of the plurality of first metallization layers (~128) and the plurality of second metallization layers (124); and
a second IC (102) coupled to the second contact (110/104).
3. Claims 1, 13, 15 and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yu et al. U.S. Patent Application Publication 2023/0170320 A1 (the ‘320 reference, of record and cited in a related International Search Report).
The reference discloses in Fig. 18 and related text an integrated circuit and a method of fabricating an integrated circuit as claimed.
Referring to claim 1, the ‘320 reference discloses an integrated circuit (IC), comprising:
a circuit layer (73, para [36]);
a plurality of first metallization layers (80, para [36]) disposed on a first side of the circuit layer and coupled to the circuit layer (73);
a plurality of second metallization layers (100A/100B, para [46]) disposed on a second side of the circuit layer (73) opposite to the first side and coupled to the circuit layer (73);
a stiffening layer (embedded power component 100C, par [49]) disposed on one (100A/100B) of the plurality of first metallization layers (80) and the plurality of second metallization layers (100A/100B); and
a first via (125, see Fig. 10, para [49]) extending through the stiffening layer (100C) to couple the one (100A/100B) of the plurality of first metallization layers and the plurality of second metallization layers to a first contact (not labeled, that of interconnect 100D, para [48]) on the stiffening layer (100C).
Referring to claim 13, the reference further discloses that the stiffening layer (100C) comprises a trench capacitor (not depicted, para [49]) (inherently) coupled to the first via (125).
Referring to claim 15, for the device detailed above for claim 1, the reference further discloses that the IC is integrated into an integrated circuit package (including wafer 150, para [36]).
Referring to claim 17 and using the same reference characters, interpretations, and citations as detailed above for claim 1 where applicable, the reference discloses in Fig. 18 a method of fabricating an integrated circuit (IC), the method comprising:
forming a circuit layer (73);
forming a plurality of first metallization layers (80) on a first side of the circuit layer;
forming a plurality of second metallization layers (100A/100B) on a second side of the circuit layer opposite to the first side;
disposing a stiffening layer (100C) on one (100A/100B) of the plurality of first metallization layers (80) and the plurality of second metallization layers (100A/100B); and
forming a first via (125) extending through the stiffening layer (100C) from a first side of the stiffening layer adjacent to the one (100A/100B) of the plurality of first metallization layers and the plurality of second metallization layers to a first contact (not labeled) on a second side of the stiffening layer (100C).
Referring to claim 18 and using the same reference characters, interpretations, and citations as detailed above for claim 1 where applicable, the reference discloses in Fig. 18 an integrated circuit (IC) package comprising:
a first package substrate (wafer 150, Fig. 18, in an upside-down view, and note that the IC package is operational in any orientation in space); and
an IC (70) comprising:
a circuit layer (73);
a plurality of first metallization layers (80) disposed on a first side of the circuit layer and coupled to the circuit layer (73);
a plurality of second metallization layers (100A/100B) disposed on a second side of the circuit layer opposite to the first side and coupled to the circuit layer (73);
a stiffening layer (100C) disposed on one (100A/100B) of the plurality of first metallization layers (80) and the plurality of second metallization layers (100A/100B); and
a first via (125) extending through the stiffening layer (100C) from a first side of the stiffening layer adjacent to the one (100A/100B) of the plurality of first metallization layers and the plurality of second metallization layers to a first contact (not labeled, that of interconnect 100D, para [48]) on a second side of the stiffening layer (100C),
wherein the first contact (said not labeled contact of 100D) is coupled to the first package substrate (150).
Referring to claim 19, the reference further discloses:
a second contact (58, see Fig. 2, para [19]) coupled (via interconnect 60, para [36]) to the other one (80) of the plurality of first metallization layers (80) and the plurality of second metallization layers (100A/100B); and
a second IC (device layer 53, para [18]) coupled to the second contact (58).
4 Claims 1, 12, 14-15 and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Law et al. U.S. Patent Application Publication 2010/0225002 A1 (the ‘002 reference).
The reference discloses in Fig. 5 and related text an integrated circuit, a method of fabricating an integrated circuit and an integrated circuit (IC) package as claimed.
Referring to claim 1, the ‘002 reference discloses an integrated circuit (IC), comprising:
a circuit layer (layer comprising active devices 102 of die 505 and/or die 505, para [20, 36]);
a plurality of first metallization layers (lower metallization 201, para [26]) disposed on a first side of the circuit layer and coupled to the circuit layer (102 of and/or 505);
a plurality of second metallization layers (middle metallization 201) disposed on a second side of the circuit layer opposite to the first side and coupled to the circuit layer (102 of and/or 505);
a stiffening layer (die 501, para [36]) disposed on one (said lower metallization 201) of the plurality of first metallization layers (said lower metallization 201) and the plurality of second metallization layers (said upper metallization 201); and
a first via (lowest TSV 401, para [30]) extending through the stiffening layer (501) to couple the one (said lower metallization 201) of the plurality of first metallization layers and the plurality of second metallization layers to a first contact (lowest 405, para [34]) on the stiffening layer (501).
Referring to claim 12, the reference further discloses that the stiffening layer (die 501, which comprises substrate 101 (see Fig. 5, para [36]), which comprises silicon, para [20]) comprises silicon.
Referring to claim 14, the reference further discloses a second contact (top 405) coupled to the other one (said middle metallization 201) of the plurality of first metallization layers (said lower metallization 201) and the plurality of second metallization layers (said middle metallization 201) and configured to couple the circuit layer (102 of and/or 505) to an external circuit (die 507, para [36]).
Referring to claim 15, for the device detailed above for claim 1, the reference further discloses that the IC is integrated into an integrated circuit package (including packaging substrate 503, para [36]).
Referring to claim 17 and using the same reference characters, interpretations, and citations as detailed above for claim 1 where applicable, the reference discloses a method of fabricating an integrated circuit (IC), the method comprising:
forming a circuit layer (102 of and/or 505, Fig. 5);
forming a plurality of first metallization layers (lower metallization 201) on a first side of the circuit layer;
forming a plurality of second metallization layers (middle metallization 201) on a second side of the circuit layer opposite to the first side;
disposing a stiffening layer (die 501, para [36]) on one of the plurality of first metallization layers and the plurality of second metallization layers; and
forming a first via (lowest TSV 401, para [30]) extending through the stiffening layer (501) from a first side of the stiffening layer adjacent to the one of the plurality of first metallization layers and the plurality of second metallization layers to a first contact (lowest 405) on a second side of the stiffening layer (501).
Referring to claim 18 and using the same reference characters, interpretations, and citations as detailed above for claim 1 where applicable, the reference discloses an integrated circuit (IC) package comprising:
a first package substrate (503, Fig. 5, para [36]); and
an IC comprising:
a circuit layer (102 of and/or 505);
a plurality of first metallization layers (lower metallization 201) disposed on a first side of the circuit layer and coupled to the circuit layer;
a plurality of second metallization layers (middle metallization 201) disposed on a second side of the circuit layer opposite to the first side and coupled to the circuit layer (102 of and/or 505);
a stiffening layer (die 501, para [36]) disposed on one (said lower metallization 201) of the plurality of first metallization layers and the plurality of second metallization layers; and
a first via (lowest TSV 401, para [30]) extending through the stiffening layer (501) from a first side of the stiffening layer adjacent to the one of the plurality of first metallization layers and the plurality of second metallization layers to a first contact (lowest 405) on a second side of the stiffening layer (501),
wherein the first contact (said lowest 405) is coupled to the first package substrate (503).
Referring to claim 19, the reference further discloses:
a second contact (top 405) coupled to the other one (said middle metallization 201) of the plurality of first metallization layers and the plurality of second metallization layers; and
a second IC (die 507, para [36]) coupled to the second contact (top 405).
5. Claims 1-3, 7-8, 12, 14-15 and 17-19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hsiao et al. U.S. Patent Application Publication 20250038074 A1 (the ‘074 reference).
The reference discloses in Figs. 2A, 11, 17 and related text an integrated circuit, a method of fabricating an integrated circuit and an integrated circuit (IC) package as claimed.
Referring to claim 1, the ‘074 reference discloses an integrated circuit (IC), comprising:
a circuit layer (device layer 102, Fig. 11, para [22]);
a plurality of first metallization layers (frontside FMLI 110, para [21]) disposed on a first side of the circuit layer and coupled to the circuit layer (102);
a plurality of second metallization layers (backside BMLI 112) disposed on a second side of the circuit layer opposite to the first side and coupled to the circuit layer (102);
a stiffening layer (silicon wafer 122, para [21]) disposed on one (110 or 112) of the plurality of first metallization layers (110) and the plurality of second metallization layers (112); and
a first via (132, para [26]) extending through the stiffening layer (122) to couple (not electrically) the one (110), or to couple the one (112), of the plurality of first metallization layers (110) and the plurality of second metallization layers (112) to a first contact (upper most metal of interconnect 141 (~141), para [61]) on the stiffening layer (122).
Referring to claim 2, the reference further discloses in Figs. 2A, 11, para [24] that the circuit layer (102) comprises:
a semiconductor layer (202) comprising devices (transistors T1, T2);
a first isolation layer (inter-layer dielectric 218 and/or 222) disposed on the devices (T1, T2) on the first side of the circuit layer (102); and
a second isolation layer (shallow trench isolation 214, and/or inter-layer dielectric 224/115’, para [24, 25, 31]) disposed on the second side of the circuit layer.
Referring to claim 3, the reference further discloses that the first isolation layer (218 and/or 222) and the second isolation layer (214 and/or 224) comprise one of inter-layer dielectric (ILD) material, inter-metal dielectric (IMD) material, and shallow trench isolation (STI) material (para [0024-0025]).
Referring to claim 7, for the IC detailed above for claim 2, the reference further discloses back side vias (not labeled, Fig. 11) extending from the semiconductor layer (202, Fig. 2A, not labeled in Fig. 11) and through the second isolation layer (lower portion of 115’) to couple the devices (T1, T2, Fig. 2A, not labeled in Fig. 11) to the plurality of second metallization layers (upper portion of 112 (~112)).
Referring to claim 8, for the IC detailed above for claim 2, the reference further discloses front side vias (234 or 236, Fig, 2A, para [25], and note that Fig. 2A depicts only one via of the front side vias) extending through the first isolation layer (218 and/or 222) to couple the devices (T1, T2) to the plurality of first metallization layers (110).
Referring to claim 12, the reference further discloses that the stiffening layer (silicon wafer 122, para [21]) comprises silicon.
Referring to claim 14, the reference further discloses a second contact (128, para [61]) coupled to the other one (112) of the plurality of first metallization layers (110) and the plurality of second metallization layers (112) and configured to couple the circuit layer (102) to an external circuit (not shown, via bond pad 135, para [61]).
Referring to claim 15, for the device detailed above for claim 1, the reference further discloses that the IC is integrated into an integrated circuit package (including contact layer 137, para [61], contact layer 126, para [34]).
Referring to claim 17 and using the same reference characters, interpretations, and citations as detailed above for claim 1 where applicable, the reference discloses a method of fabricating an integrated circuit (IC), the method comprising:
forming a circuit layer (102, Fig. 11);
forming a plurality of first metallization layers (110) on a first side of the circuit layer;
forming a plurality of second metallization layers (112) on a second side of the circuit layer opposite to the first side;
disposing a stiffening layer (122, para [21]) on one (110) of the plurality of first metallization layers and the plurality of second metallization layers; and
forming a first via (132, para [26]) extending through the stiffening layer (122) from a first side of the stiffening layer adjacent to the one of the plurality of first metallization layers and the plurality of second metallization layers to a first contact (~141) on a second side of the stiffening layer (122).
Referring to claim 18 and using the same reference characters, interpretations, and citations as detailed above for claim 1 where applicable, the reference discloses an integrated circuit (IC) package comprising:
a first package substrate (contact layer 137, 126, Figs. 11, 17, para [61, 62]); and
an IC comprising:
a circuit layer (102);
a plurality of first metallization layers (110) disposed on a first side of the circuit layer and coupled to the circuit layer;
a plurality of second metallization layers (112) disposed on a second side of the circuit layer opposite to the first side and coupled to the circuit layer (102);
a stiffening layer (122, para [21]) disposed on one (110 or 112) of the plurality of first metallization layers (110) and the plurality of second metallization layers (112); and
a first via (132, para [26]) extending through the stiffening layer (122) from a first side of the stiffening layer adjacent to the one (110) of the plurality of first metallization layers and the plurality of second metallization layers to a first contact (~141, uppermost pad and/or metal layer of the first package substrate 126 (~126)) on a second side of the stiffening layer (122),
wherein the first contact (~141, ~126) is coupled to the first package substrate (137, 126).
Referring to claim 19, the reference further discloses:
a second contact (126’, Fig. 17, para [62]) coupled to the other one (112 or 110) of the plurality of first metallization layers (110) and the plurality of second metallization layers (112); and
a second IC (circuit layer 102’, Fig. 17, para [62]) coupled to the second contact (126’, via multi-layer interconnect 112’, para [65]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. §103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claim 16 is rejected under 35 U.S.C. §103 as being unpatentable over Hsiao et al. U.S. Patent Application Publication 20250038074 A1 (the ‘074 reference) in view of Su et al. U.S. Patent Application Publication 20170074923.
Referring to claim 16, the ‘074 reference discloses the IC as detailed above for claim 1, but does not discloses integrating the IC into a working electronic device.
Su, in disclosing an IC, teaches integrating the IC into a working electronic device such as a cellular phone, a computer and a navigation device (para [12]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have integrated the reference’s IC into a working electronic device such as a cellular phone, a computer and a navigation device. One would have been motivated to make such a modification in view of the teachings in Su to make useful electronic devices.
Thus, such a modification would have resulted in a device selected from the group consisting of a cellular phone, a computer and a navigation device, meeting the claim limitation “a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multicopter.”
7. Claim 4 is rejected under 35 U.S.C. §103 as being unpatentable over Hsiao et al. U.S. Patent Application Publication 20250038074 A1 (the ‘074 reference) in view of Gaul et al. U.S. Patent 5,807,783 or Huang U.S. Patent 6,235,567 B1.
Referring to claim 4, the ‘074 reference discloses the IC as detailed above for claim 1, the circuit comprising the circuit layer (102) which comprises MOS transistors (para [22, 23]), but does not disclose that a thickness of the circuit layer is less than two (2) microns (μm).
Gaul, in disclosing an IC comprising a circuit layer (10’, Fig. 4) including a MOS transistor (20), teaches that a thickness of the circuit layer is approximately 0.5 microns thick (col. 5, lines 20-25); or, Huang, in disclosing an IC comprising a circuit layer including a MOS transistor, teaches that a preferred thickness of the circuit layer is about 0.1 μm - 0.2 μm (col. 2, lines 55-60).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the reference’s circuit layer’s thickness of approximately 0.5 microns or about 0.1 μm - 0.2 μm. One would have been motivated to make such a modification in view of the teachings in Gaul or Huang for the implied purpose of making thin and compact IC.
Thus, such a modification would have resulted in an IC wherein a thickness of the circuit layer would have been less than two (2) microns (μm).
8. Claim 5 is rejected under 35 U.S.C. §103 as being unpatentable over Hsiao et al. U.S. Patent Application Publication 20250038074 A1 (the ‘074 reference) in view of Kim et al. U.S. Patent Application Publication 20200101577 or Chiu et al. U.S. Patent Application Publication 20220319945.
Referring to claim 5, the ‘074 reference discloses the stiffening layer 122 as detailed above for claim 1 and further discloses that the stiffening layer 122 is a carrier wafer (para [21]), but does not disclose that the stiffening layer has a thickness in a range of twenty (20) to one hundred (100) microns (μm).
Kim, in disclosing an IC comprising a carrier wafer (10), teaches that the carrier wafer has a thickness in a range of over one hundred μm (par [43]), thereby teaching that 100 μm or over is a suitable thickness for a carrier wafer; or, Chiu, in disclosing an IC comprising a carrier wafer (30W), teaches that the carrier wafer has a thickness in a range of 100 μm to 300 μm (par [69]), thereby teaching that 100 μm – 300 μm in thickness is a suitable range of thickness for a carrier wafer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the reference’s stiffening carrier wafer 122 having a thickness of over 100 μm or in a range of 100 μm to 300 μm. One would have been motivated to make such a modification in view of the teachings in Kim or Chiu for forming a stiffening carrier wafer.
Thus, such a modification would have resulted in an IC wherein the stiffening carrier wafer 122 would have had a thickness of over 100 μm or in a range of 100 μm to 300 μm, meeting the claim limitation “a thickness in a range of twenty (20) to one hundred (100) microns (μm).
9. Claim 6 is rejected under 35 U.S.C. §103 as being unpatentable over Hsiao et al. U.S. Patent Application Publication 20250038074 A1 (the ‘074 reference) in view of Gaul et al. U.S. Patent 5,807,783 or Huang U.S. Patent 6,235,567 B1 and further in view of Kim et al. U.S. Patent Application Publication 20200101577 or Chiu et al. U.S. Patent Application Publication 20220319945.
Referring to claim 6, the ‘074 reference in view of Gaul or Huang discloses that a thickness of the circuit layer (102) would have been approximately 0.5 μm thick as detailed above for claim 4, and the ‘074 reference in view of Kim or Chiu discloses that the stiffening carrier wafer (122) would have had a thickness in a range of 100 μm to 300 μm as detailed above for claim 5; thus it follows that a thickness of the stiffening layer would have been at least 200 times, meeting the claim limitation “at least ten (10) times”, a thickness of the circuit layer.
10. Claims 10-11 are rejected under 35 U.S.C. §103 as being unpatentable over Hsiao et al. U.S. Patent Application Publication 20250038074 A1 (the ‘074 reference) in view of Sanuki et al. U.S. Patent Application Publication 20140284488.
Referring to claims 10-11, the ‘074 reference discloses the plurality of first metallization layers (110) and the plurality of second metallization layers (112) as detailed above for claim 1, but does not disclose that a thickness of a first plurality of metal layers in the plurality of first metallization layers is in a range of 1.0 to 3.0 microns (μm) and that a thickness of a second plurality of metal layers in the plurality of second metallization layers is in a range of 1.0 to 3.0 microns (μm).
Sanuki, in disclosing an IC comprising a plurality of metallization layers (a multilayer interconnect structure), teaches that a thickness of the plurality of metallization layers is several μm (par [83]), thereby teaching that several μm is a suitable thickness for a plurality of metallization layers.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the reference’s plurality of first metallization layers (110) and plurality of second metallization layers (112) each having a thickness of several μm. One would have been motivated to make such a modification in view of the teachings in Sanuki for forming working plurality of first metallization layers (110) and plurality of second metallization layers (112).
Thus, such a modification would have resulted in an IC wherein a thickness of a first plurality of metal layers in the plurality of first metallization layers would have been several μm, meeting the claim limitation “is in a range of 1.0 to 3.0 microns (μm)” and a thickness of a second plurality of metal layers in the plurality of second metallization layers would have been several μm, meeting the claim limitation “is in a range of 1.0 to 3.0 microns (μm)”.
11. Claim 9 is rejected under 35 U.S.C. §103 as being unpatentable over Farooq et al. U.S. Patent Application Publication 2023/0230901 A1 (the ‘901 reference, of record and cited in a related International Search Report) in view of Trezza U.S. Patent Application Publication 20080261392 or Beyne U.S. Patent Application Publication 20120139127.
Referring to claim 9, the ‘901 reference discloses the first via (110) as detailed above for claim 1, and further discloses that the first via 110 has a height of about 50 μm (the height of the stiffening silicon layer 122, para [33]), but does not disclose that a height-to-width ratio of the first via is in a range of five to one (5:1) to ten to one (10:1).
Trezza, in disclosing an IC comprising a via, discloses that a diameter of the via is about 5 μm (para [24]), thereby teaching that 5 μm is a suitable diameter for the via; or, Beyne, in disclosing an IC comprising a via, discloses that a diameter (width) of the via is about 5 μm (par [34]), thereby teaching that 5 μm is a suitable diameter for the via.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have formed the reference’s first via (110) to have a diameter (width) of about 5 μm. One would have been motivated to make such a modification in view of the teachings in Trezza or Beyne for forming a working first via (110).
Thus, such a modification would have resulted in an IC wherein a height-to-width ratio of the first via is in a range of about ten to one (10:1) (50 μm: 5 μm), meeting the claim range of “five to one (5:1) to ten to one (10:1)”.
Conclusion
12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TU TU V HO whose telephone number is (571)272-1778. The examiner can normally be reached on Monday to Thursday 6:30 - 15:00, Monday through Thursday.
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11-25-2025
/TU-TU V HO/Primary Examiner, Art Unit 2818