DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ginetti et al., hereinafter Ginetti, US Patent No. 9,223,915.
Regarding Claim 1, Ginetti teaches a computer-implemented method for layout versus schematic (LVS) checking for a design process of an integrated circuit (IC), the computer-implemented method comprising:
receiving a layout of the IC at multiple hierarchical levels (Ginetti Col. 6, Lines 36-67 and Col. 7, Lines 1-46, wherein a layout of an IC design is received to perform a layout versus schematic check, the layout being hierarchical);
receiving a schematic of the IC at the multiple hierarchical levels (Ginetti Col. 6, Lines 36-67 and Col. 7, Lines 1-46, wherein a schematic of an IC design is received to perform a layout versus schematic check, the schematic being hierarchical);
establishing a requirement for name matching (Ginetti Col. 21, Lines 15-34, wherein checking for name mismatches establishes a requirement for matching names);
scanning the layout and the schematic at least at one of the multiple hierarchical levels (Ginetti Col. 14, Lines 38-59 and Col. 18, Lines 20-47, Col. 21, Lines 15-34, wherein name mismatches are identified by ascending and descending through the hierarchy of the layout and schematic, i.e. scanning); and
issuing an alert for one or more name inconsistencies identified during the scanning (Ginetti Col. 21, Lines 15-34 and Col. 22, Lines 38-50, wherein the identified mismatches are marked, the mark being an alert).
Regarding Claim 2, Ginetti further teaches wherein:
the scanning comprises comparing cells at one of the multiple hierarchical levels of the layout and the schematic (Ginetti Col. 14, Lines 38-59 and Col. 18, Lines 20-47, Col. 21, Lines 15-34, wherein name mismatches are identified by ascending and descending through the hierarchy of the layout and schematic, i.e. scanning, and comparing), and
the establishing of the requirement for name matching comprises stipulating that cell names match between the layout and the schematic for the one of the multiple hierarchical levels (Ginetti Col. 9, Lines 33-63, Col. 18, Lines 35-47, and Col. 20, Lines 50-67, wherein the destinations of nets and pins must correspond when checking connectivity, destinations including cell symbols with identifiers).
Regarding Claim 3, Ginetti further teaches wherein:
the scanning comprises comparing cells at one of the multiple hierarchical levels of the layout and the schematic (Ginetti Col. 14, Lines 38-59 and Col. 18, Lines 20-47, Col. 21, Lines 15-34, wherein name mismatches are identified by ascending and descending through the hierarchy of the layout and schematic, i.e. scanning, and comparing), and
the establishing of the requirement for name matching comprises stipulating that instance names match between the layout and the schematic for the one of the multiple hierarchical levels (Ginetti Col. 9, Lines 33-63, Col. 18, Lines 35-47, and Col. 20, Lines 50-67, wherein the nets and pin instances must correspond when checking connectivity).
Regarding Claim 4, Ginetti further teaches wherein:
the scanning comprises comparing pins for every cell at one of the multiple hierarchical levels of the layout and the schematic (Ginetti Col. 14, Lines 38-59 and Col. 18, Lines 20-47, Col. 21, Lines 15-34, wherein pin name mismatches are identified by ascending and descending through the hierarchy of the layout and schematic, i.e. scanning, and comparing), and
the establishing of the requirement for name matching comprises stipulating that pin names match between the layout and the schematic for the one of the multiple hierarchical levels (Ginetti Col. 21, Lines 15-34, wherein checking for pin name mismatches establishes a requirement for matching names for pins).
Regarding Claim 5, Ginetti further teaches flagging a missing element in the layout discovered during the scanning (Ginetti Col. 21, Lines 15-34, wherein missing connectivity is identified).
Regarding Claim 6, Ginetti further teaches determining a type of the missing element and storing the type in a record (Ginetti Col. 21, Lines 15-34 and Col. 22, Lines 38-50, wherein missing connectivity is identified with subsequent correction indicating that the identified missing connectivity information is stored).
Regarding Claim 7, Ginetti further teaches automatically correcting the one or more name inconsistencies (Ginetti Col. 22, Lines 38-50, wherein mismatches may be automatically corrected).
Regarding Claim 8, Ginetti teaches a computer program product for layout versus schematic (LVS) checking for a design process of an integrated circuit (IC), the computer program product comprising one or more computer readable storage media having computer readable program code collectively stored on the one or more computer readable storage media (Ginetti Col. 25, Lines 63-67 and Col. 26, Lines 1-9, see computer readable storage medium), the computer readable program code being executed by a processor of a computer system to cause the computer system to perform a method comprising:
receiving a layout of the IC at multiple hierarchical levels (Ginetti Col. 6, Lines 36-67 and Col. 7, Lines 1-46, wherein a layout of an IC design is received to perform a layout versus schematic check, the layout being hierarchical);
receiving a schematic of the IC at the multiple hierarchical levels (Ginetti Col. 6, Lines 36-67 and Col. 7, Lines 1-46, wherein a schematic of an IC design is received to perform a layout versus schematic check, the schematic being hierarchical);
establishing a requirement for name matching (Ginetti Col. 21, Lines 15-34, wherein checking for name mismatches establishes a requirement for matching names);
scanning the layout and the schematic at least at one of the multiple hierarchical levels (Ginetti Col. 14, Lines 38-59 and Col. 18, Lines 20-47, Col. 21, Lines 15-34, wherein name mismatches are identified by ascending and descending through the hierarchy of the layout and schematic, i.e. scanning); and
issuing an alert for one or more name inconsistencies identified during the scanning (Ginetti Col. 21, Lines 15-34 and Col. 22, Lines 38-50, wherein the identified mismatches are marked, the mark being an alert).
Regarding Claim 9, Ginetti further teaches wherein:
the scanning comprises comparing cells at one of the multiple hierarchical levels of the layout and the schematic (Ginetti Col. 14, Lines 38-59 and Col. 18, Lines 20-47, Col. 21, Lines 15-34, wherein name mismatches are identified by ascending and descending through the hierarchy of the layout and schematic, i.e. scanning, and comparing), and
the establishing of the requirement for name matching comprises stipulating that cell names match between the layout and the schematic for the one of the multiple hierarchical levels (Ginetti Col. 9, Lines 33-63, Col. 18, Lines 35-47, and Col. 20, Lines 50-67, wherein the destinations of nets and pins must correspond when checking connectivity, destinations including cell symbols with identifiers).
Regarding Claim 10, Ginetti further teaches wherein:
the scanning comprises comparing cells at one of the multiple hierarchical levels of the layout and the schematic (Ginetti Col. 14, Lines 38-59 and Col. 18, Lines 20-47, Col. 21, Lines 15-34, wherein name mismatches are identified by ascending and descending through the hierarchy of the layout and schematic, i.e. scanning, and comparing), and
the establishing of the requirement for name matching comprises stipulating that instance names match between the layout and the schematic for the one of the multiple hierarchical levels (Ginetti Col. 9, Lines 33-63, Col. 18, Lines 35-47, and Col. 20, Lines 50-67, wherein the nets and pin instances must correspond when checking connectivity).
Regarding Claim 11, Ginetti further teaches wherein:
the scanning comprises comparing pins for every cell at one of the multiple hierarchical levels of the layout and the schematic (Ginetti Col. 14, Lines 38-59 and Col. 18, Lines 20-47, Col. 21, Lines 15-34, wherein pin name mismatches are identified by ascending and descending through the hierarchy of the layout and schematic, i.e. scanning, and comparing), and
the establishing of the requirement for name matching comprises stipulating that pin names match between the layout and the schematic for the one of the multiple hierarchical levels (Ginetti Col. 21, Lines 15-34, wherein checking for pin name mismatches establishes a requirement for matching names for pins).
Regarding Claim 12, Ginetti further teaches wherein the method further comprises flagging a missing element the layout discovered during the scanning (Ginetti Col. 21, Lines 15-34, wherein missing connectivity is identified).
Regarding Claim 13, Ginetti further teaches wherein the method further comprises determining a type of the missing element and storing the type in a record (Ginetti Col. 21, Lines 15-34 and Col. 22, Lines 38-50, wherein missing connectivity is identified with subsequent correction indicating that the identified missing connectivity information is stored).
Regarding Claim 14, Ginetti further teaches wherein the method further comprises automatically correcting the one or more name inconsistencies (Ginetti Col. 22, Lines 38-50, wherein mismatches may be automatically corrected).
Regarding Claim 15, Ginetti teaches a computing system comprising:
a processor (Ginetti Col. 25, Lines 63-66, see processor);
a memory coupled to the processor (Ginetti Col. 25, Lines 63-66, see memory); and
one or more computer readable storage media coupled to the processor (Ginetti Col. 25, Lines 63-67 and Col. 26, Lines 1-9, see computer readable storage medium), the one or more computer readable storage media collectively containing instructions that are executed by the processor via the memory to cause the processor to perform steps for layout versus schematic (LVS) checking for a design process of an integrated circuit (IC) comprising:
receiving a layout of the IC at multiple hierarchical levels (Ginetti Col. 6, Lines 36-67 and Col. 7, Lines 1-46, wherein a layout of an IC design is received to perform a layout versus schematic check, the layout being hierarchical);
receiving a schematic of the IC at the multiple hierarchical levels (Ginetti Col. 6, Lines 36-67 and Col. 7, Lines 1-46, wherein a schematic of an IC design is received to perform a layout versus schematic check, the schematic being hierarchical);
establishing a requirement for name matching (Ginetti Col. 21, Lines 15-34, wherein checking for name mismatches establishes a requirement for matching names);
scanning the layout and the schematic at least at one of the multiple hierarchical levels (Ginetti Col. 14, Lines 38-59 and Col. 18, Lines 20-47, Col. 21, Lines 15-34, wherein name mismatches are identified by ascending and descending through the hierarchy of the layout and schematic, i.e. scanning); and
issuing an alert for one or more name inconsistencies identified during the scanning (Ginetti Col. 21, Lines 15-34 and Col. 22, Lines 38-50, wherein the identified mismatches are marked, the mark being an alert).
Regarding Claim 16, Ginetti further teaches wherein:
the scanning comprises comparing cells at one of the multiple hierarchical levels of the layout and the schematic (Ginetti Col. 14, Lines 38-59 and Col. 18, Lines 20-47, Col. 21, Lines 15-34, wherein name mismatches are identified by ascending and descending through the hierarchy of the layout and schematic, i.e. scanning, and comparing), and
the establishing of the requirement for name matching comprises stipulating that cell names match between the layout and the schematic for the one of the multiple hierarchical levels (Ginetti Col. 9, Lines 33-63, Col. 18, Lines 35-47, and Col. 20, Lines 50-67, wherein the destinations of nets and pins must correspond when checking connectivity, destinations including cell symbols with identifiers).
Regarding Claim 17, Ginetti further teaches wherein:
the scanning comprises comparing cells at one of the multiple hierarchical levels of the layout and the schematic (Ginetti Col. 14, Lines 38-59 and Col. 18, Lines 20-47, Col. 21, Lines 15-34, wherein name mismatches are identified by ascending and descending through the hierarchy of the layout and schematic, i.e. scanning, and comparing), and
the establishing of the requirement for name matching comprises stipulating that instance names match between the layout and the schematic for the one of the multiple hierarchical levels (Ginetti Col. 9, Lines 33-63, Col. 18, Lines 35-47, and Col. 20, Lines 50-67, wherein the nets and pin instances must correspond when checking connectivity).
Regarding Claim 18, Ginetti further teaches wherein:
the scanning comprises comparing pins for every cell at one of the multiple hierarchical levels of the layout and the schematic (Ginetti Col. 14, Lines 38-59 and Col. 18, Lines 20-47, Col. 21, Lines 15-34, wherein pin name mismatches are identified by ascending and descending through the hierarchy of the layout and schematic, i.e. scanning, and comparing), and
the establishing of the requirement for name matching comprises stipulating that pin names match between the layout and the schematic for the one of the multiple hierarchical levels (Ginetti Col. 21, Lines 15-34, wherein checking for pin name mismatches establishes a requirement for matching names for pins).
Regarding Claim 19, Ginetti further teaches wherein the steps for the LVS checking for the design process of the IC further comprise:
flagging a missing element in one of the layout and the schematic discovered during the scanning (Ginetti Col. 21, Lines 15-34, wherein missing connectivity is identified); and
determining a type of the missing element and storing the type in a record (Ginetti Col. 21, Lines 15-34 and Col. 22, Lines 38-50, wherein missing connectivity is identified with subsequent correction indicating that the identified missing connectivity information is stored).
Regarding Claim 20, Ginetti further teaches wherein the steps for the LVS checking for the design process of the IC further comprise automatically correcting the one or more name inconsistencies (Ginetti Col. 22, Lines 38-50, wherein mismatches may be automatically corrected).
Conclusion
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/ERIC D LEE/Primary Examiner, Art Unit 2851
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