Prosecution Insights
Last updated: October 27, 2026
Application No. 18/460,931

PACKAGE ARCHITECTURES HAVING VERTICALLY STACKED DIES WITH A COOLING MICROCHANNEL

Non-Final OA §112
Filed
Sep 05, 2023
Examiner
KEBEDE, BROOK
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
926 granted / 1042 resolved
+20.9% vs TC avg
Minimal +4% lift
Without
With
+4.5%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
25 currently pending
Career history
1059
Total Applications
across all art units

Statute-Specific Performance

§101
2.2%
-37.8% vs TC avg
§103
35.9%
-4.1% vs TC avg
§102
30.3%
-9.7% vs TC avg
§112
12.3%
-27.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1042 resolved cases

Office Action

§112
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 2-4 and 17-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 2 recites the limitation “wherein the first IC die is one of a plurality of first IC dies” in line 1. Claim 17 recites the limitation “wherein the first IC die is one of a plurality of first IC dies” in line 1. The limitation “the first IC die is one of a plurality of first IC dies” lacks clarity in the scope and the meaning for the followings: As best understood, independent claim 1, recites the first single IC die and claim 2 further recites plurality first dies part of the single IC die. That neither further limits the independent claim nor provides clarity. A broad range or limitation together with a narrow range or limitation that falls within the broad range or limitation (in the same claim) may be considered indefinite if the resulting claim does not clearly set forth the metes and bounds of the patent protection desired. See MPEP § 2173.05(c). In the present instance, claim 1 recites the broad recitation “a first IC die”, and the claim also recites “the first IC die is one of a plurality of first IC dies” which is the narrower statement of the range/limitation. The claim(s) are considered indefinite because there is a question or doubt as to whether the feature introduced by such narrower language is (a) merely exemplary of the remainder of the claim, and therefore not required, or (b) a required feature of the claims. Claim 3 recites the limitation “wherein the plurality of first IC dies are bonded together at respective first and second surfaces” in lines 1-2. However, the limitation lacks clarity in the meaning and the scope for the following reasons: Claim 18 recites the limitation “wherein the plurality of first IC dies are bonded together at respective first and second surfaces” in lines 1-2. However, the limitation lacks clarity in the meaning and the scope for the following reasons: As recited in claim 1 and 16, the first surface and the second surface are related to the first IC die. However, it is not clear which first IC die bonded to which surface of the first IC die. Claims 3-4 and 18-19 are also rejected as being directly or indirectly dependent on the rejected claim 2. Claim Objections Claims 1- are objected to because of the following informalities: Claim 1 recites the limitation “a second IC die” in line 2. Changing “a second IC die” to -- a second integrated circuit (IC) die-- provides better form of claim language and consistency. Claim 1 recites the limitation “a third surface orthogonal to the first and second surfaces,” in line 3. However, there is a lack of proper antecedent basis for “the first and second surfaces” in the claim. Changing “a third surface orthogonal to the first and second surfaces” to -- a third surface orthogonal to the first surface and the second surface of the firs IC die—provides proper antecedent basis and clarity throughout the claim. Claim 1 recites the limitation “a metallization stack with a conductive trace that is parallel to the first and second surfaces and exposed at the third surface” in lines 4-5. However, there is a lack of proper antecedent basis for “the first and second surfaces” in the claim. Changing “a metallization stack with a conductive trace that is parallel to the first and second surfaces and exposed at the third surface” to -- a metallization stack with a conductive trace that is parallel to the first surface and the second surface and exposed at the third surface of the first IC die-- provides proper antecedent basis and clarity throughout the claim. Claim 3 recites the limitation “a third surface orthogonal to the first and second surfaces” in lined 3-4. However, there is a lack of proper antecedent basis for “the first and second surfaces” in the claim. Changing “a third surface orthogonal to the first and second surfaces” to -- a third surface orthogonal to the first surface and the second surface of the first IC die-- provides proper antecedent basis and clarity throughout the claim. Claim 9 recites the limitation “a second IC die” in line 2. Changing “a second IC die” to -- a second integrated circuit (IC) die-- provides better form of claim language and consistency. Claim 9 recites the limitation “a third surface orthogonal to the first and second surfaces” in lines 3-4. However, there is a lack of proper antecedent basis for “the first and second surfaces” in the claim. Changing “a third surface orthogonal to the first and second surfaces” to -- a third surface orthogonal to the first surface and the second surface of the firs IC die-- provides proper antecedent basis and clarity throughout the claim. Claim 9 recites the limitation “a metallization stack with a conductive traces that are parallel to the first and second surfaces and exposed at the third surface” in lines 4-5. However, there is a lack of proper antecedent basis for “the first and second surfaces” in the claim. Changing “a metallization stack with a conductive traces that are parallel to the first and second surfaces and exposed at the third surface” to -- a metallization stack with a conductive traces that are parallel to the first surface and the second surface and exposed at the third surface of the first IC die-- provides proper antecedent basis and clarity throughout the claim. Claim 16 recites the limitation “a third surface orthogonal to the first and second surfaces” in line 3. However, there is a lack of proper antecedent basis for “the first and second surfaces” in the claim. Changing “a third surface orthogonal to the first and second surfaces” to -- a third surface orthogonal to the first surface and the second surface of the first IC die-- provides proper antecedent basis and clarity throughout the claim. Claim 16 recites the limitation “a metallization stack on the substrate along an interface that is parallel to the first and second surfaces” in lines 5-6. However, there is a lack of proper antecedent basis for “the first and second surfaces” in the claim. Changing “a metallization stack on the substrate along an interface that is parallel to the first and second surfaces” to -- a metallization stack on the substrate along an interface that is parallel to the first surface and the second surface of the first IC die-- provides proper antecedent basis and clarity throughout the claim. Claim 16 recites the limitation “the metallization stack including conductive traces that are parallel to the first and second surfaces and exposed at the third surface” in lines 6-7. However, there is a lack of proper antecedent basis for “the first and second surfaces” in the claim. Changing “the metallization stack including conductive traces that are parallel to the first and second surfaces and exposed at the third surface” to -- the metallization stack including conductive traces that are parallel to the first surface and the second surface and exposed at the third surface of the first IC die-- -- provides proper antecedent basis and clarity throughout the claim. Applicant’s cooperation is requested in reviewing the claims’ structure to ensure proper claim construction and to correct any subsequently discovered instances of claim language noncompliance. See Morton International Inc., 28USPQ2d 1190, 1195 (CAFC, 1993). Appropriate correction is required. Allowable Subject Matter Claims 1, 5-15, 16 and 20 are allowed. The following is a statement of reasons for the indication of allowable subject matter: Prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “the first IC die including a substrate with a microchannel, and a metallization stack with a conductive trace that is parallel to the first [surface] and [the] second surface[[s ]] and exposed at the third surface [of the first IC die],” as recited in claim 1, “a substrate with a microchannel, wherein the substrate is between the first IC die and the second IC die and bonded to a respective first or second surface of the first IC die and the second IC die,” as recited in claim 9, and “the first IC die including; a substrate with a microchannel, and a metallization stack on the substrate along an interface that is parallel to the first [surface] and [the] second surface[[s]] [of the first IC die], the metallization stack including conductive traces that are parallel to the first [surface] and [the] second surface[[s]] and exposed at the third surface [of the first IC die],” as recited in claim 16. Claims 5-8, 10-15 and 20 are also allowed as being directly or indirectly dependent of the allowed independent base claim. Claims 2-4 and 17-19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure Neal et al. (US 2020/0203256) disclose an IC package having a substrate and a fluid channel (i.e., microchannel) formed in the substrate. Suthram et al. (US 2023/0420409) disclose an IC die comprises a first surface, a second surface and the first surface is orthogonal to the second surface and a third surface that is coplanar to the fist surface and conductive traces in a dielectric layer. However, the prior art neither anticipates nor renders obvious the aforementioned allowable limitations of claims 1, 9 and 16. Correspondence Any inquiry concerning this communication or earlier communications from the examiner should be directed to BROOK KEBEDE whose telephone number is 571-272-1862. The examiner can normally be reached Monday Friday 8:00 AM 5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BROOK KEBEDE/ Primary Examiner, Art Unit 2894 /BK/ October 11, 2026
Read full office action

Prosecution Timeline

Sep 05, 2023
Application Filed
Jan 10, 2024
Response after Non-Final Action
Oct 14, 2026
Non-Final Rejection mailed — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
93%
With Interview (+4.5%)
2y 1m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1042 resolved cases by this examiner. Grant probability derived from career allowance rate.

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