Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II, Claims 10-20, in the reply filed on 3/23/2026 is acknowledged. Claims 1-9 are withdrawn from consideration.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 10-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1: Is the Claim to a Process, Machine, Manufacture or Composition of Matter?
Claim 10 recites a method of predicting characteristics of a target wafer, and Claim 18 recites a process control system. Therefore the Claims are to methods and a system, which are among the statutory categories of invention.
Step 2A: Prong One: Does the Claim Recite an Abstract Idea?
Independent claim 10 recites:
A method of predicting circuit characteristics of a target wafer, the method comprising:
collecting measured values of sample wafers among wafers manufactured in a semiconductor process and measuring one or more physical characteristics among a plurality of physical characteristics of the sample wafers;
classifying the collected measured values according to process paths of the sample wafers [the examiner finds that the foregoing underlined element recites a mental process because it can be performed by a human using pen and paper];
determining predicted values of one or more physical characteristics among the plurality of physical characteristics of the target wafer using a process path of the target wafer, the target wafer not among the sample wafers [the examiner finds that the foregoing underlined element recites a mental process because it can be performed by a human using pen and paper]; and
predicting circuit characteristics of the target wafer using measured values of the sample wafers and predicted values of the target wafer [the examiner finds that the foregoing underlined element recites a mental process because it can be performed by a human using pen and paper].
18. A process control system, comprising:
a big data collection server configured to collect, from a semiconductor fab, log data including process path information of wafers manufactured in the semiconductor fab and measured values of physical characteristics of sample wafers selected from among the manufactured wafers;
a virtual measurement server configured to obtain the measured values of the sample wafers from the big data collection server, to classify the measured values according to process paths of the sample wafers, to generate predicted values of physical characteristics of unmeasured target wafers according to the classified measured values and process paths of target wafers, and to store the generated predicted values, the unmeasured target wafers being different from the sample wafers [the examiner finds that the foregoing underlined element recites a mental process because it can be performed by a human using pen and paper]; and
a characteristic prediction server configured to obtain the measured values of the sample wafers from the big data collection server, to obtain the predicted values of the target wafers from the virtual measurement server, to predict circuit characteristics of the manufactured wafers using the measured values and predicted values, and to feedback a control signal to the semiconductor fab based on the predicted circuit characteristics [the examiner finds that the foregoing underlined element recites a mental process because it can be performed by a human using pen and paper].
Step 2A: Prong Two: Does the Claim Recite Additional Elements That Integrate The Abstract Idea Into a Practical Application?
Regarding Claim 10, the elements that are not underlined above are the additional elements (i.e., “collecting measured values of sample wafers among wafers manufactured in a semiconductor process and measuring one or more physical characteristics among a plurality of physical characteristics of the sample wafers”).
The examiner submits that the additional element does no more than generally link the use of the abstract idea to a particular technological environment or field of use because they are merely an incidental or token addition to the claim that does not alter or affect how the process steps of the abstract idea are performed. The collecting step merely recite gathering of data for use in the abstract idea (the classifying, determining, and predicting steps).
Regarding Claim 18, the elements that are not underlined above are the additional elements (i.e., “a big data collection server configured to collect, from a semiconductor fab, log data including process path information of wafers manufactured in the semiconductor fab and measured values of physical characteristics of sample wafers selected from among the manufactured wafers”; “a virtual measurement server configured to obtain the measured values of the sample wafers from the big data collection server”; “to store the generated predicted values”; “a characteristic prediction server configured to obtain the measured values of the sample wafers from the big data collection server, to obtain the predicted values of the target wafers from the virtual measurement server” and “to feedback a control signal to the semiconductor fab based on the predicted circuit characteristics”).
The examiner submits that the additional element does no more than generally link the use of the abstract idea to a particular technological environment or field of use because they are merely an incidental or token addition to the claim that does not alter or affect how the process steps of the abstract idea are performed. The collecting and obtaining steps merely recite gathering of data for use in the abstract idea. The storing and feedback step merely recites insignificant outputting of results of the abstract idea. The big data collection server, the virtual measurement server, and the characteristic prediction server merely recite generic computer hardware for implementing the abstract idea.
Thus, taken alone, the additional elements in claims 10 and 18 do not integrate the abstract idea into a practical application. Looking at the limitations as an ordered combination adds nothing that is not already present when looking at the elements taken individually. For example, there is no indication that the combination of elements improves the functioning of a computer or improves any other technology.
Step 2B: Does the Claim Recite Additional Elements That Amount to Significantly More Than the Abstract Idea?
The examiner submits that the additional elements do not amount to significantly more than the abstract idea for the same reasons discussed above with respect to the conclusion that the additional elements do not integrate the abstract idea into a practical application.
Dependent Claims 11-17 and 19-20 merely recite further details of the mental process, further data gathering, and/or generic computer hardware, and are also not patent eligible.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10, 18, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ko et al (U.S. Pub. No. 2011/0060441, hereinafter “Ko”).
Regarding Claim 10, Ko teaches a method of predicting circuit characteristics of a target wafer (Fig. 6), the method comprising: collecting measured values of sample wafers among wafers manufactured in a semiconductor process and measuring one or more physical characteristics among a plurality of physical characteristics of the sample wafers (Fig. 6, step 350; paragraphs [0023] and [0037], inline data like metrology results, realtime processing tool sensor data, and WAT results); classifying the collected measured values according to process paths of the sample wafers (Fig. 6, step 352, paragraph [0038], cluster routes are equated to process paths; see also Fig. 2, showing routes, or paths, through semiconductor processing tools); determining predicted values of one or more physical characteristics among the plurality of physical characteristics of the target wafer using a process path of the target wafer, the target wafer not among the sample wafers (Fig. 6, steps 354 and 356, physical characteristics, such as uniformity, of the wafers that are dispatched along different cluster routes are determined based on the models that were determined based on the gathered data); and predicting circuit characteristics of the target wafer using measured values of the sample wafers and predicted values of the target wafer (Fig. 6, steps 354 and 356, paragraphs [0039]-[0040], physical characteristics, which include WAT results, of the wafers that are dispatched along different cluster routes are predicted based on the models; see also Figs. 7-8 and paragraph [0023], which defines WAT results, and includes circuit characteristics).
Regarding Claim 18, Ko teaches a process control system, comprising: a big data collection server (paragraph [0037], computer) configured to collect, from a semiconductor fab, log data including process path information of wafers manufactured in the semiconductor fab and measured values of physical characteristics of sample wafers selected from among the manufactured wafers (Fig. 6, step 350; paragraphs [0023] and [0037], inline data like metrology results, realtime processing tool sensor data, and WAT results); a virtual measurement server (paragraph [0038], computer) configured to obtain the measured values of the sample wafers from the big data collection server (paragraphs [0038] and [0023]), to classify the measured values according to process paths of the sample wafers (Fig. 6, step 352, paragraph [0038], cluster routes are equated to process paths; see also Fig. 2, showing routes, or paths, through semiconductor processing tools), to generate predicted values of physical characteristics of unmeasured target wafers according to the classified measured values and process paths of target wafers, and to store the generated predicted values, the unmeasured target wafers being different from the sample wafers (Fig. 6, steps 354 and 356, paragraph [0039], physical characteristics, such as uniformity, of the wafers that are dispatched along different cluster routes are determined based on the models; uniformity is predicted for future wafers to be dispatched along various routes, which are equated to unmeasured target wafers); and a characteristic prediction server (paragraphs [0038]-[0039], computer) configured to obtain the measured values of the sample wafers from the big data collection server (paragraphs [0038]-[0039] and [0023]), to obtain the predicted values of the target wafers from the virtual measurement server (paragraphs [0038]-[0039]), to predict circuit characteristics of the manufactured wafers using the measured values and predicted values (Fig. 6, steps 354 and 356, paragraphs [0039]-[0040], physical characteristics, which include WAT results, of the wafers that are dispatched along different cluster routes are predicted based on the models; see also Figs. 7-8 and paragraph [0023], which defines WAT results, and includes circuit characteristics), and to feedback a control signal to the semiconductor fab based on the predicted circuit characteristics (dispatching of block 356 of Fig. 6 would include sending controls signals to the semiconductor fab).
Regarding Claim 20, Ko teaches everything that is claimed above with respect to Claim 18. Ko further teaches wherein the virtual measurement server maps the measured values and the process paths based on identifiers of the sample wafers (Fig. 6, blocks 350 and 352 and paragraphs [0037]-[0038], routes are identified based on wafer data from wafers that were processed by particular routes; it being known that a wafer was processed by a particular route may be considered to be an identifier of a wafer).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ko in view of Good (U.S. Pub. No. 2009/0276174).
Regarding Claim 11, Ko teaches everything that is claimed above with respect to Claim 10. Ko does not specifically teach generating a regression analysis equation for predicting the circuit characteristics based on the plurality of physical characteristics by performing multiple regression analysis of measured values of the plurality of physical characteristics of the wafer and measured values of the circuit characteristics. However, Good teaches generating a regression analysis equation for predicting the circuit characteristics based on the plurality of physical characteristics by performing multiple regression analysis of measured values of the plurality of physical characteristics of the wafer and measured values of the circuit characteristics (paragraph [0037], performing multiple least squares regression on measurement data from a semiconductor process in order to determine a prediction model). It would have been obvious to one skilled in the art before the effective filing date for the invention to include the regression analysis of Good in the system of Ko, because such data processing techniques are well-established (see Good, paragraph [0037]).
Regarding Claim 12, Ko in view of Good teaches everything that is claimed above with respect to Claim 11. Ko does not specifically teach wherein the generating a regression analysis equation includes determining a correlation coefficient with a measured value of the circuit characteristic for each of the plurality of physical characteristics. However, Good teaches wherein the generating a regression analysis equation includes determining a correlation coefficient with a measured value of the circuit characteristic for each of the plurality of physical characteristics (paragraph [0037], correlations determined between desired observables from measurement data from semiconductor process). It would have been obvious to one skilled in the art before the effective filing date for the invention to include the correlations of Good in the system of Ko, because such data processing techniques are well-established (see Good, paragraph [0037]).
Regarding Claim 13, Ko in view of Good teaches everything that is claimed above with respect to Claim 11. Ko further teaches wherein the collecting of the measured values of sample wafers includes: collecting measured values of first sample wafers of which a first physical characteristic among the plurality of physical characteristics is measured among the manufactured wafers; and collecting measured values of second sample wafers of which a second physical characteristic among the plurality of physical characteristics are measured among the manufactured wafers, and wherein a portion of the first sample wafers and a portion of the second sample wafers overlap (paragraph [0023], in situ metrology results collected from semiconductor process are equated to claimed collected measured values; Fig. 2, a set of wafers may be processed by a first tool cluster 50 or a second tool cluster 52 in stage 1, and then portions of the set of wafers may be processed by different tool clusters 54, 56, or 58 in stage 2; i.e., wafers processed by different tool clusters in stage 2 may be considered to overlap because they were processed by the same tool cluster in stage 1).
Regarding Claim 14, Ko in view of Good teaches everything that is claimed above with respect to Claim 11. Ko further teaches wherein the determining of the predicted values of physical characteristics of the target wafer includes: determining predicted values for the first physical characteristic of first target wafers excluding the first sample wafers among the manufactured wafers; and determining predicted values for the second physical characteristic of second target wafers excluding the second sample wafers among the manufactured wafers (Fig. 5, paragraphs [0030]-[0032], and Fig. 6, blocks 350 and 352, paragraphs [0037]-[0038], models are built on a per tool cluster basis and then grouped into routes; wafers processed by the same tool cluster in stage 1 that were processed by different tool clusters in stage 2, see Fig. 2, would be split into different route models in in block 352, see paragraph [0033]).
Claim(s) 15-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ko in view of Good and Kim et al (U.S. Pub. No. 2020/0201952, hereinafter “Kim”).
Regarding Claim 15, Ko in view of Good teaches everything that is claimed above with respect to Claim 11. Ko does not specifically teach wherein the target wafer includes a plurality of memory devices, and wherein the plurality of physical characteristics include: a depth of shallow trench isolation (STI) included in the plurality of memory devices; a depth of a buried channel array transistor (BCAT) of gate structures included in the plurality of memory devices; and a height of a fin structure of active regions included in the plurality of memory devices (paragraph [0023], in situ metrology results). However, Ko does teach, in paragraph [0023], in situ metrology results. Further, Kim teaches wherein the target wafer includes a plurality of memory devices (paragraph [0023]), and wherein the plurality of physical characteristics include: a depth of shallow trench isolation (STI) included in the plurality of memory devices (paragraph [0041]); a depth of a buried channel array transistor (BCAT) of gate structures included in the plurality of memory devices (paragraph [0041]); and a height of a fin structure of active regions included in the plurality of memory devices (paragraphs [0040] and [0063]). It would have been obvious to one skilled in the art before the effective fling date of the invention to include the various dimensions of the various features taught in Kim in the in-situ metrology results of Ko, because such features are known aspects of semiconductor devices and may be used to predict the shape of the semiconductor device, which is important for achieving high integration of a semiconductor device (see Kim paragraphs [0002]-[0003]).
Regarding Claim 16, Ko in view of Good and Kim teaches everything that is claimed above with respect to Claim 15. Ko further teaches wherein the circuit characteristics include a threshold voltage of the gate structures (paragraph [0023], threshold voltage uniformity).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ko in view of Good, Kim, and Butt et al (U.S. Pub. No. 2018/0174948, hereinafter “Butt”).
Regarding Claim 17, Ko in view of Good and Kim teaches everything that is claimed above with respect to Claim 15. Ko does not specifically teach wherein the semiconductor process includes a front-end-of-line (FEOL) process, a middle-of-line (MOL) process, and a back-end-of-line (BEOL) process, each of which includes a plurality of unit processes, wherein the FEOL process includes a process of forming the STI, a process of forming the BCAT, and a process of forming the fin structure, and wherein the classifying the collected measured values includes classifying measured values of a depth of the STI, measured values of a depth of the BCAT, and measured values of a height of the fin structure of the sample wafers according to process paths of the FEOL process. However, Ko does teach a plurality of unit processes (Fig. 2), in-situ metrology results (paragraph [0023]), and classifying of collected measured values according to process paths (Fig. 2, and Fig. 6, blocks 350 and 352). Further, Butt teaches wherein the semiconductor process includes a front-end-of-line (FEOL) process, a middle-of-line (MOL) process, and a back-end-of-line (BEOL) process, each of which includes a plurality of unit processes, wherein the FEOL process includes a process of forming the STI, and a process of forming the fin structure (paragraphs [0029]-[0030]; FEOL conventionally includes STI and active device formation, which includes fins). It would have been obvious to one skilled in the art before the effective fling date of the invention to include the FEOL, MOL, and BEOL processing taught in Butt in the system of Ko, because such processing is conventional (see Butt, paragraph [0029]).
Ko in view of Butt does not specifically teach that the FEOL processing includes a process of forming the BCAT. However, Butt does teach that conventional FEOL processing can include formation of many types of devices (paragraph [0029]). Further, Kim teaches a process of forming the BCAT (paragraph [0041]). It would have been obvious to one skilled in the art before the effective filing date of the invention to include the BCAT formation of Kim in the FEOL processing of Ko and Butt, because such processing is conventional (see Butt, paragraph [0029]), and because such features are known aspects of semiconductor devices and may be used to predict the shape of the semiconductor device, which is important for achieving high integration of a semiconductor device (see Kim paragraphs [0002]-[0003]).
Ko in view of Butt does not specifically teach wherein the classifying the collected measured values includes classifying measured values of a depth of the STI, measured values of a depth of the BCAT, and measured values of a height of the fin structure of the sample wafers according to process paths of the FEOL process. However, Ko does teach in-situ metrology results (paragraph [0023]), and classifying of collected measured values according to process paths (Fig. 2, and Fig. 6, blocks 350 and 352). Further, Kim teaches measured values of a depth of the STI, measured values of a depth of the BCAT, and measured values of a height of the fin structure of the sample wafers (paragraphs [0040]-[0041] and [0063]). It would have been obvious to one skilled in the art before the effective fling date of the invention to include the various dimensions of the various features taught in Kim in the in-situ metrology results of Ko, because such features are known aspects of semiconductor devices and may be used to predict the shape of the semiconductor device, which is important for achieving high integration of a semiconductor device (see Kim paragraphs [0002]-[0003]).
Further, Butt teaches that it is conventional to include many types of device processing in a FEOL process (see paragraph [0029]). It would have been obvious to one skilled in the art before the effective filing date of the invention to classify the metrology data of Ko and Kim according to process paths of the FEOL process, as taught in Butt, because such processing is conventional (see Butt, paragraph [0029]).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ko in view of Bennett (U.S. Pub. No. 2002/0007422).
Regarding Claim 19, Ko teaches everything that is claimed above with respect to Claim 18. Ko does not specifically teach wherein the virtual measurement server includes: an input/output device configured to obtain the measured values of the sample wafers from the big data collection server; a working memory into which instructions for virtual measurement are loaded; a processor configured to classify the measured values according to process paths of the sample wafers by executing the instructions, and to generate predicted values of physical characteristics of the target wafers; and an auxiliary storage device configured to store the generated predicted values. However, Ko does teach that the various virtual measurement steps of Claim 18 (i.e., obtain the measured values of the sample wafers from the big data collection server, classify the measured values according to process paths of the sample wafers, and generate predicted values of physical characteristics of the target wafers, see the rejection of Claim 18, above) are performed by computers (paragraphs [0037]-[0039]). Further, Bennett teaches wherein the a server (paragraph [0036], Fig. 2B) includes: an input/output device configured to obtain values (267, 269); a working memory into which instructions are loaded (259); a processor configured to execute the instructions (255); and an auxiliary storage device configured to store values (265). It would have been obvious to one skilled in the art before the effective filing date of the invention to include the conventional server computer of Bennet in the system of Ko, because such a computer is conventional (see paragraph [0036]) and can be used for semiconductor processing and metrology equipment (paragraph [0111]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CYNTHIA L DAVIS whose telephone number is (571)272-1599. The examiner can normally be reached Monday-Friday, 7am to 3pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Shelby A Turner can be reached at (571)272-6334. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CYNTHIA L DAVIS/ Examiner, Art Unit 2857
/SHELBY A TURNER/ Supervisory Patent Examiner, Art Unit 2857
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