DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments
The amendment filed 11/19/2025 has been entered.
Claims 1, 3, 9-10, 13, and 15 are amended.
Claim 17 is cancelled.
Claims 1-16 and 18-20 are pending.
Response to Arguments
Applicant’s arguments, see pg. 9, regarding Claim Objections to Claim 1 have been fully considered and are persuasive. The objection to Claim 1 has been overcome.
Applicant’s arguments, see pg. 9, regarding the rejection of Claims 1, 3, and 9 under 35 USC 112(b) have been fully considered and are persuasive. The rejection of Claims 1, 3, and 9 have been overcome.
Applicant’s arguments, see pg. 9, regarding the rejection of Claims 10 and 15 under 35 USC 112(b) have been fully considered but they are not persuasive. See the 112(b) rejections below.
Applicant’s arguments, see pgs. 10-14, regarding the rejection of Claim 1, 9, and 15 have been fully considered but they are not persuasive.
Regarding Claim 1, Applicant appears to argue that Tong does not teach a follower radar device configured to generate its own (second) clock signal and transmitting the clock signal to a leader radar device upon failure of specific components within the leader radar device (Remarks, pg. 13). Examiner respectfully disagrees and asserts Tong teaches that both the first and second radar ICs are configured to act as either a master or slave, and both are configured to generate their own common clock signals and common LO signals and transmit the signals to the other radar IC upon detection of a fault (e.g., [0052]; [0067]; [0073]; [0075]).
Regarding Claim 1, applicant appear to argue that Tong does not generating a second clock signal in response to “receiving a message from the crystal oscillator operation detection circuit indication a fault in a first clock generation circuit” (Remarks, pg. 14). Applicant’s arguments have been considered but are moot because they do not respond to the specific combination of references used in the current rejection.
Regarding Claim 1, applicant appears to argue that Tong does not teach generating a local oscillator signal in the follower radar device that is transmitted to the leader radar device. Examiner respectfully disagrees and asserts Tong teaches that both the first and second radar ICs are configured to act as either a master or slave, and both are configured to generate their own common clock signals and common LO signals and transmit the signals to the other radar IC upon detection of a fault (e.g., [0052]; [0067]; [0073]; [0075]).
Regarding Claim 1, applicant appears to argue that Tong only teaches using a single crystal oscillator, and does not teach a second crystal oscillator. In response to applicant's arguments against the references individually, one cannot show non-obviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Examiner asserts that Tong teaches a cascaded radar system with multiple clock signal generation circuits, and generally teaches using a crystal oscillator to generate a clock signal. Chen teaches using multiple crystal oscillators to generate clock signals to improve fault tolerance. Examiner asserts that the combined teachings of Tong and Chen suggest to one of ordinary skill in the art that using multiple crystal oscillator, as taught by Chen, could be used in the cascaded radar system taught by Tong to improve fault tolerance and improve the safety of the system.
Regarding Claims 9 and 15, Applicant appears to argue that Tong does not teach a follower radar device configured to generate its own clock signal and transmitting the clock signal to a leader radar device upon failure of specific components within the leader radar device (Remarks, pgs. 11-12). Examiner respectfully disagrees and asserts Tong teaches that both the first and second radar ICs are configured to act as either a master or slave, and both are configured to generate their own common clock signals and common LO signals and transmit the signals to the other radar IC upon detection of a fault (e.g., [0052]; [0067]; [0073]; [0075]).
Regarding Claims 9 and 15, applicant appears to argue that Tong only teaches using a single crystal oscillator, and does not teach a second crystal oscillator. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., multiple crystal oscillators) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Regarding Claims 9 and 15, applicant appear to argue that Tong does not teach generating a second clock signal in response to “receiving a message from the crystal oscillator operation detection circuit indication a fault in a first clock generation circuit” (Remarks, pg. 12). Applicant’s arguments have been considered but are moot because they do not respond to the specific combination of references used in the current rejection.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims
particularly pointing out and distinctly claiming the subject matter which the
inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out
and distinctly claiming the subject matter which the applicant regards as his
invention.
Claims 10 and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 10, the claim recites the limitation “a second local oscillator signal” in line a. It is unclear if this limitation refers to the second local oscillator signal in Claim 9 or to an additional local oscillator signal. For examination purposes, the limitation is interpreted as “the second local oscillator signal.”
Regarding Claim 15, the claim recites the limitation “the leader radar device is configured to generate a first clock signal and distribute the first clock signal to the follower radar device by receiving a message from a crystal oscillator operation detection circuit indicating a fault in a first clock generation circuit of the leader radar device” (emphasis added) in lines 2-7. It is unclear if the leader or follow radar device is supposed to receive a message from the crystal oscillator operation detection circuit. For example, Claim 9 and Applicant’s Remarks (pg. 12) indicate that the follower radar device receives the message from the crystal oscillator operation detection circuit.
Regarding Claim 15, the claim recites the limitation “the second local oscillator signal” in lines 15 and 17-18. There is insufficient antecedent basis for this limitation in the claim. There is no “first oscillator signal” in Claim 15, and the only oscillator signal appears to be “a local oscillator signal” introduced in line 10. For examination purposes, the limitation is interpreted as referring to the “local oscillator signal” in line 10.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C.
102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the
statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a
new ground of rejection if the prior art relied upon, and the rationale supporting the rejection,
would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness
rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the
claimed invention is not identically disclosed as set forth in section 102, if the
differences between the claimed invention and the prior art are such that the
claimed invention as a whole would have been obvious before the effective filing
date of the claimed invention to a person having ordinary skill in the art to which
the claimed invention pertains. Patentability shall not be negated by the manner in
which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Tong (US 2019/0187273) in view of Chen (US 2021/0006344) and Reuter (US 2019/0204846).
Regarding Claim 1, Tong teaches:
An automotive radar system, comprising:
a first crystal oscillator ([0067]: "a crystal oscillator for providing a reference clock signal");
a leader radar device electrically connected to the first crystal oscillator ([0063]: "the first transceiver 210 is configured as master IC"), the leader radar device including:
a first clock generation circuit, including a first crystal-controlled clock oscillator unit configured to generate a first clock signal based upon a first input signal from the first crystal oscillator ([0067]: "...master IC, may also transmit other signals (not shown) to the slave IC, such as a common clock signal"),
…
a first local oscillator signal generator including a first phase locked loop circuit and local oscillator interface configured to generate a first local oscillator signal using the first clock signal ([0063]: "the first transceiver 210 is configured as master IC, such that it generates a first common local oscillator (LO) signal"; [0065]: "PLL"), and
first transmitters and receivers configured to transmit and receive first radar signals using the first local oscillator signal ([0054]: "multiple operational transmit (TX) ports and multiple receiver (RX) ports (not shown)");
a … crystal oscillator ([0067]: "a crystal oscillator for providing a reference clock signal");
a follower radar device electrically connected to the … crystal oscillator, wherein the follower radar device is configured to receive the first clock signal and the first local oscillator signal from the leader radar device ([0063]: "the second transceiver 220 is configured as slave IC"; "the second transceiver uses the common LO signal received via the coupling device 230 from the first transceiver 210"; [0067]: "Each of the first and second transceivers 210, 220, when configured as master IC, may also transmit other signals (not shown) to the slave IC, such as a common clock signal"), the follower radar device including:
a second clock generation circuit, including a second crystal-controlled clock oscillator unit configured to generate a second clock signal based upon a second input signal from the … crystal oscillator ([0067]: "Each of the first and second transceivers 210, 220, when configured as master IC, may also transmit other signals (not shown) to the slave IC, such as a common clock signal"),
a second local oscillator signal generator including a second phase locked loop circuit configured to generate a second local oscillator signal using the second clock signal ([0064]: "In a second configuration of the radar system 200, the second transceiver 220 is configured as master IC such that it generates a second common local oscillator (LO) signal."; [0065]: "PLL"), and
second transmitters and receivers configured to transmit and receive second radar signals using the second local oscillator signal and/or the first local oscillator signal received from the leader radar device ([0054]: "multiple operational transmit (TX) ports and multiple receiver (RX) ports (not shown)"; [0064]: "the second transceiver 220 is configured as slave IC, such that ... the second transceiver uses the common LO signal"), wherein, when the automotive radar system operates in a default mode:
the follower radar device is configured to bypass the second clock generation circuit so that an input signal to the second clock generation circuit is equal in phase to an output signal of the second clock generation circuit ([0030]: "phase compensation circuitry for compensating a phase difference between the outputs of the coupling device"; [0063]: "In this first configuration of the radar system 200, the second transceiver 220 is configured as slave IC, such that the LO output port 222 of the second transceiver 220 is disabled"), and
the follower radar device is configured to by the local oscillator signal generator so that an input signal to the second local oscillator signal generator is equal in phase to an output signal of the second local oscillator signal generator ([0030]: "phase compensation circuitry for compensating a phase difference between the outputs of the coupling device"; [0063]: "In this first configuration of the radar system 200, the second transceiver 220 is configured as slave IC, such that the LO output port 222 of the second transceiver 220 is disabled"); and
a central processor ([0067]: "a controller for controlling the data acquisition process for the radar system 200 and receiving data from the master and slave ICs."), configured to perform steps including:
… indicating a fault in the first clock generation circuit leader radar device ([0053]: “a functional failure in the VCO/PLL (voltage controlled oscillator/phase locked loop) block of the master IC 110”; [0075]: “in response to a fault occurring in the first IC 210”; Examiner note: VCOs and PLLs are used in both clock signal generation and LO signal generation),
causing the follower radar device to enable operation of the second clock generation circuit to generate the second clock signal, wherein the second clock signal is transmitted to the first clock generation circuit, ([0067]: "Each of the first and second transceivers 210, 220, when configured as master IC, may also transmit other signals (not shown) to the slave IC, such as a common clock signal"; [0075]: "The second IC 220 may then take over the function of master IC"),
detecting a fault in the first local oscillator signal generator of the leader radar device ([0053]: “a functional failure in the VCO/PLL (voltage controlled oscillator/phase locked loop) block of the master IC 110”; [0075]: “in response to a fault occurring in the first IC 210”; Examiner note: VCOs and PLLs are used in both clock signal generation and LO signal generation),
causing the follower radar device to enable operation of the second local oscillator signal generator, wherein the second local oscillator signal is transmitted to the first local oscillator signal generator of the leader radar device ([0073]: “any one of the plurality of transceivers may be configured as master, for outputting the common LO signal, with the other transceivers being configured as slaves and receiving the common LO signal”; [0075]: "with the second IC 220 providing the common LO signal"), and
causing the follower radar device to transmit and receive radar signals using the second local oscillator signal ([0075]: “with the second IC 220 providing the common LO signal for the system 200”; "This enables the system 200 to continue to function").
Tong does not explicitly teach – but Chen teaches: a second crystal oscillator (Chen [0116]: "backup grandmaster clocks (bGMs)"; [0130]: "Reference clock source 940 and 980 may be a crystal oscillator").
It would have been obvious to one of ordinary skill in the art to modify Tong and use a second crystal oscillator, as taught by Chen. Additional crystal oscillators are considered ordinary and well-known for use in cascaded radar systems. Using a second crystal oscillator is beneficial for making the radar system fault-tolerant, which improves vehicle safety.
Tong does not explicitly teach a crystal oscillator operation detection circuit or receiving a message from the crystal oscillator operation detection circuit indicating a fault in the first clock generation circuit. However, Reuter teaches using specific circuitry that is able to detect faults in clock and oscillator circuits, and sends an error signal indicating a fault (Reuter [0053]: “each transceiver 310, 320, 330, 340 may be configured to perform a self-test (e.g. to check if the PLL is locked and/or if a transmitted frequency is correct) and to forward an error signal or interrupt signal to the MCU 350 if the self-test results in a fail”; [0055-0056]: teaching reconfiguring the transceiver to switch to using an internal PLL, an internally-generated LO signal, or an internally-generated clock signal based on the error signal.).
It would have been obvious to one of ordinary skill in the art to modify Tong and use specific circuitry to detect faults and receiving a message from the circuitry indicating a fault in a clock generation circuit, as taught by Reuter. Tong is already configured to detect and react to faults, and using specific circuitry to detect and indicate faults is considered ordinary and well-known in the art. Using the specific circuitry to detect and indicate faults is beneficial for detecting faults in specific components and improving the fault tolerance of the system.
Regarding Claim 2, Tong teaches: wherein, after detecting the fault in the leader radar device, the central processor is further configured to perform the step of bypassing at least a portion of the first crystal-controlled clock oscillator unit and wherein the follower radar device is configured to transmit the second clock signal to the leader radar device to enable the leader radar device to continue operating using the second clock signal ([0075]: "the system 200 may be reconfigured from the first to the second configurations described above in response to a fault occurring in the first IC 210"; [0064]: "In this second configuration of the radar system 200, the first transceiver 210 is configured as slave IC, such that the LO output port 212 of the first transceiver 210 is disabled"; [0067]: "Each of the first and second transceivers 210, 220, when configured as master IC, may also transmit other signals (not shown) to the slave IC, such as a common clock signal").
Regarding Claim 3, Tong teaches: wherein the leader radar device includes a fault collection and control circuit that is connected to the first clock generation circuit and the central processor is configured to perform the step of detecting the fault in the leader radar device … ([0075]: "…in response to a fault occurring in the first IC 210, for example a fault in a VCO block of the first IC while configured as master.").
Tong does not explicitly teach – but Yousuf teaches: detecting the fault in the leader radar device by receiving a flag signal from the fault collection and control circuit (Reuter [0054]: “receiving an error signal”).
It would have been obvious to one of ordinary skill in the art to modify Tong and detect the fault in the leader radar device by receiving a flag signal from the fault condition and control circuit, as taught by Reuter. Error flags/signals are considered ordinary and well-known for use in radar systems. Using flag signals is beneficial for making the radar system fault-tolerant, which improves vehicle safety.
Regarding Claim 4, Tong teaches: … including a first input terminal configured to receive the first clock signal from the first clock generation circuit, a first output terminal electrically connected to the first clock generation circuit and a second output terminal electrically connected to the second clock generation circuit ([0055-0056]: teaching a coupling device, including input and output terminals, for distributing a local oscillator (LO) signal to the LO inputs of the first and second transceivers; [0067]: teaching distributing clock signals).
Tong does not explicitly teach: the system further comprising a first signal splitter.
However, in that Tong teaches using power dividers to distribute signals ([0002]: "The LO signal is generated from the master IC and distributed to all the master and slave ICs through one or more T-junction power dividers."), it would have been obvious to one of ordinary skill in the art to modify Tong and use a first signal splitter to distribute the first clock signal to the leader and follower radar devices. Signal splitters are considered ordinary and well-known for use in radar systems. Modifying Tong to use a signal splitter is a matter of simple substitution of one known element for another to obtain predictable results.
Regarding Claim 5, Tong teaches: … including a first input terminal configured to receive the second clock signal from the second clock generation circuit, a first output terminal electrically connected to the first clock generation circuit and a second output terminal electrically connected to the second clock generation circuit ([0055-0056]: teaching a coupling device, including input and output terminals, for distributing a local oscillator (LO) signal to the LO inputs of the first and second transceivers; [0067]: teaching distributing clock signals).
Tong does not explicitly teach: the system further comprising a second signal splitter.
However, in that Tong teaches using power dividers to distribute signals ([0002]: "The LO signal is generated from the master IC and distributed to all the master and slave ICs through one or more T-junction power dividers."), it would have been obvious to one of ordinary skill in the art to modify Tong and use a second signal splitter to distribute the second clock signal to the leader and follower radar devices. Signal splitters are considered ordinary and well-known for use in radar systems. Modifying Tong to use a signal splitter is a matter of simple substitution of one known element for another to obtain predictable results.
Regarding Claim 6, Tong teaches: … including:
an input terminal electrically connected to the first local oscillator signal generator by a first transmission line and to the second local oscillator signal generator by a second transmission line ([0055-0056]: teaching a coupling device, including input and output terminals, for distributing a local oscillator (LO) signal to the LO inputs of the first and second transceivers; [0067]: teaching distributing clock signals);
a first output terminal electrically connected to a first local oscillator signal input of the leader radar device by a third transmission line ([0055-0056]; [0067]); and
a second output terminal electrically connected to a second local oscillator signal input of the follower radar device by a fourth transmission line ([0055-0056]; [0067]).
Tong does not explicitly teach: the system further comprising a splitter.
However, in that Tong teaches using power dividers to distribute signals ([0002]: "The LO signal is generated from the master IC and distributed to all the master and slave ICs through one or more T-junction power dividers."), it would have been obvious to one of ordinary skill in the art to modify Tong and use a splitter. Signal splitters are considered ordinary and well-known for use in radar systems. Modifying Tong to use a signal splitter is a matter of simple substitution of one known element for another to obtain predictable results.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Tong (US 2019/0187273) in view of Chen (US 2021/0006344) and Reuter (US 2019/0204846), as applied to Claim 6 above, and further in view of Pavao (US 2020/0007310).
Regarding Claim 7, Tong does not explicitly teach – but Pavao teaches: wherein a first electrical length of the third transmission line is equal to a second electrical length of the fourth transmission line (Pavao [0009]: "Typically, in master-slave arrangements, the LO signal 140 is routed with symmetrical PCB lengths in order to ensure that all receivers ... in each master device 110 and slave device(s) 120, 123 of the system receive the same LO with same phase. Phase coherence is mandatory for cascaded systems.").
It would have been obvious to one of ordinary skill in the art to modify Tong and make the electrical length of the third transmission line is equal to a second electrical length of the fourth transmission line, as taught by Pavao. Making the electrical lengths equal is beneficial for ensuring phase coherence across radar devices so that the system can function properly.
Regarding Claim 8, Tong does not explicitly teach – but Pavao teaches: wherein a third electrical length of the first transmission line is equal to a fourth electrical length of the second transmission line (Pavao [0009]: "Typically, in master-slave arrangements, the LO signal 140 is routed with symmetrical PCB lengths in order to ensure that all receivers ... in each master device 110 and slave device(s) 120, 123 of the system receive the same LO with same phase. Phase coherence is mandatory for cascaded systems.").
The rational to modify Tong with the teachings of Pavao would persist from Claim 7.
Claims 9-16 and 18-20 rejected under 35 U.S.C. 103 as being unpatentable over Tong (US 2019/0187273) in view of Reuter (US 2019/0204846).
Regarding Claim 9, Tong teaches:
A radar system, comprising:
a leader radar device ([0054]: "first IC 210 in the form of a first transceiver"; [0063]: "the first transceiver 210 is configured as master IC"), including:
a first clock generation circuit configured to generate a first clock signal ([0067]: "...master IC, may also transmit other signals (not shown) to the slave IC, such as a common clock signal"), using a first crystal-controlled clock oscillator unit ([0067]: “crystal oscillator”),
…
a first local oscillator signal generator including a first phase locked loop circuit configured to generate a first local oscillator signal using the first clock signal ([0063]: "the first transceiver 210 is configured as master IC, such that it generates a first common local oscillator (LO) signal"; [0065]: "PLL"), and
a first transmitter and receiver configured to transmit and receive first radar signals using the first local oscillator signal ([0054]: "each IC 210, 220 includes multiple operational transmit (TX) ports and multiple receiver (RX) ports (not shown)"; [0063]: "the first transceiver 210 is configured as master IC, such that it generates a first common local oscillator (LO) signal");
a follower radar device, wherein the follower radar device is configured to receive the first clock signal and the first local oscillator signal from the leader radar device ([0054]: "a second IC 220 in the form of second transceiver"; [0063]: "the second transceiver 220 is configured as slave IC"; "the second transceiver uses the common LO signal received via the coupling device 230 from the first transceiver 210"; [0067]: "...master IC, may also transmit other signals (not shown) to the slave IC, such as a common clock signal"), the follower radar device including:
a second clock generation circuit configured to generate a second clock signal, wherein, in a default operational mode of the radar system at least a portion of the second clock generation circuit is disabled ([0065]: "The LO output port of the other transceiver (i.e. the slave) of the first and second transceivers 110, 120 is disabled"; [0067]: "Each of the first and second transceivers 210, 220, when configured as master IC, may also transmit other signals (not shown) to the slave IC, such as a common clock signal"), and in a first fault mode of operation … indicating that the first clock generation circuit is not operational ([0053]: “a functional failure in the VCO/PLL (voltage controlled oscillator/phase locked loop) block of the master IC 110”; [0075]: “in response to a fault occurring in the first IC 210”; Examiner note: VCOs and PLLs are used in both clock signal generation and LO signal generation), the follower radar device is configured to transmit the second clock signal to the first clock generation circuit of the leader radar device ([0067]: "Each of the first and second transceivers 210, 220, when configured as master IC, may also transmit other signals (not shown) to the slave IC, such as a common clock signal"; [0075]: "The second IC 220 may then take over the function of master IC"),
a second local oscillator signal generator including a second phase locked loop circuit configured to generate a second local oscillator signal using the first clock signal ([0064]: "In a second configuration of the radar system 200, the second transceiver 220 is configured as master IC such that it generates a second common local oscillator (LO) signal."; [0065]: "PLL"), wherein, in a default operational mode of the radar system at least a portion of the second local oscillator signal generator is disabled ([0063]: "In this first configuration of the radar system 200, the second transceiver 220 is configured as slave IC, such that the LO output port 222 of the second transceiver 220 is disabled"), and in a second fault mode of operation in which the first local oscillator signal generator is not operational, the second local oscillator signal generator is configured to transmit the second local oscillator signal to the first local oscillator signal generator of the leader radar device ([0073]: “any one of the plurality of transceivers may be configured as master, for outputting the common LO signal, with the other transceivers being configured as slaves and receiving the common LO signal”; [0075]: "with the second IC 220 providing the common LO signal") and
a second transmitter and receiver configured to transmit and receive second radar signals ([0054]: "each IC 210, 220 includes multiple operational transmit (TX) ports and multiple receiver (RX) ports (not shown)").
Tong does not explicitly teach a crystal oscillator operation detection circuit or receiving a message from the crystal oscillator operation detection circuit indicating a fault in the first clock generation circuit. However, Reuter teaches using specific circuitry that is able to detect faults in clock and oscillator circuits, and sends an error signal indicating a fault (Reuter [0053]: “each transceiver 310, 320, 330, 340 may be configured to perform a self-test (e.g. to check if the PLL is locked and/or if a transmitted frequency is correct) and to forward an error signal or interrupt signal to the MCU 350 if the self-test results in a fail”; [0055-0056]: teaching reconfiguring the transceiver to switch to using an internal PLL, an internally-generated LO signal, or an internally-generated clock signal based on the error signal.).
It would have been obvious to one of ordinary skill in the art to modify Tong and use specific circuitry to detect faults and receiving a message from the circuitry indicating a fault in a clock generation circuit, as taught by Reuter. Tong is already configured to detect and react to faults, and using specific circuitry to detect and indicate faults is considered ordinary and well-known in the art. Using the specific circuitry to detect and indicate faults is beneficial for detecting faults in specific components and improving fault tolerance of the system.
Regarding Claim 10, Tong teaches: the system further comprising:
a central processor electrically connected to the leader radar device and the follower radar device ([0067]: "a controller for controlling the data acquisition process for the radar system 200 and receiving data from the master and slave ICs."), the central processor being configured to perform steps including:
detecting a fault in the leader radar device ([0075]: "...in response to a fault occurring in the first IC 210"),
causing the follower radar device to enable operation of the second clock generation circuit to generate the second clock signal ([0075]: "The second IC 220 may then take over the function of master IC for the system 200. This enables the system 200 to continue to function, with the second IC 220 providing the common LO signal for the system 200."), and
causing the follower radar device to transmit and receive second radar signals using the second local oscillator signal ([0075]: "This enables the system 200 to continue to function").
Regarding Claim 11, Tong teaches: wherein, after detecting the fault in the leader radar device, the central processor is further configured to perform the step of disabling at least a portion of the first clock generation circuit in the leader radar device ([0075]: "the system 200 may be reconfigured from the first to the second configurations described above in response to a fault occurring in the first IC 210"; [0064]: "In this second configuration of the radar system 200, the first transceiver 210 is configured as slave IC, such that the LO output port 212 of the first transceiver 210 is disabled").
Regarding Claim 12, Tong teaches: wherein the follower radar device is configured to transmit the second clock signal to the leader radar device ([0067]: "Each of the first and second transceivers 210, 220, when configured as master IC, may also transmit other signals (not shown) to the slave IC, such as a common clock signal").
Regarding Claim 13, Tong teaches: … including a first input terminal configured to receive the first clock signal from the leader radar device, a first output terminal electrically connected to a first local oscillator signal generator in the leader radar device and a second output terminal electrically connected to a second local oscillator signal generator in the follower radar device ([0055-0056]: teaching a coupling device, including input and output terminals, for distributing a local oscillator (LO) signal to LO inputs of the first and second transceivers; [0067]: teaching distributing clock signals).
Tong does not explicitly teach: the system further comprising a first signal splitter.
However, in that Tong teaches using power dividers to distribute signals ([0002]: "The LO signal is generated from the master IC and distributed to all the master and slave ICs through one or more T-junction power dividers."), it would have been obvious to one of ordinary skill in the art to modify Tong and use a first signal splitter to distribute the first clock signal to the leader and follower radar devices. Signal splitters are considered ordinary and well-known for use in radar systems. Modifying Tong to use a signal splitter is a matter of simple substitution of one known element for another to obtain predictable results.
Regarding Claim 14, Tong teaches: … including a first input terminal configured to receive the second clock signal from the follower radar device, a first output terminal electrically connected to the first local oscillator signal generator and a second output terminal electrically connected to the second local oscillator signal generator ([0055-0056] teaching a coupling device, including input and output terminals, for distributing a local oscillator (LO) signal to the LO inputs of the first and second transceivers; [0067] teaching distributing clock signals).
Tong does not explicitly teach: the system further comprising a second signal splitter.
However, in that Tong teaches using power dividers to distribute signals ([0002]: "The LO signal is generated from the master IC and distributed to all the master and slave ICs through one or more T-junction power dividers."), it would have been obvious to one of ordinary skill in the art to modify Tong and use a second signal splitter to distribute the second clock signal to the leader and follower radar devices. Signal splitters are considered ordinary and well-known for use in radar systems. Modifying Tong to use a signal splitter is a matter of simple substitution of one known element for another to obtain predictable results.
Regarding Claim 15, Tong teaches:
A method, comprising:
detecting a fault in a clock signal generation component of a leader radar device of a cascaded-configuration automotive radar system ([0002]: "automotive radar systems"; "cascading multiple radar transceiver chips"; [0063]: "master IC"; [0075]: "...in response to a fault occurring in the first IC 210"), wherein the automotive radar system includes a follower radar device and the leader radar device is configured to generate a first clock signal and distribute the first clock signal to the follower radar device … indicating a fault in a first clock generation ([0053]: “a functional failure in the VCO/PLL (voltage controlled oscillator/phase locked loop) block of the master IC 110”; [0075]: “in response to a fault occurring in the first IC 210”; Examiner note: VCOs and PLLs are used in both clock signal generation and LO signal generation; [0063]: "slave IC"; [0067]: "Each of the first and second transceivers 210, 220, when configured as master IC, may also transmit other signals (not shown) to the slave IC, such as a common clock signal");
causing the follower radar device to generate a second clock signal ([0067]: "Each of the first and second transceivers 210, 220, when configured as master IC, may also transmit other signals (not shown) to the slave IC, such as a common clock signal"; [0075]: "The second IC 220 may then take over the function of master IC");
causing the follower radar device to enable operation of a local oscillator signal generator configured to generate a local oscillator signal using the second clock signal ([0075]: "with the second IC 220 providing the common LO signal for the system 200"),
causing the follower radar device to transmit the second clock signal to the leader radar device ([0067]: "Each of the first and second transceivers 210, 220, when configured as master IC, may also transmit other signals (not shown) to the slave IC, such as a common clock signal"; [0075]: "The second IC 220 may then take over the function of master IC"), and wherein the leader radar device is configured to use the second clock signal to transmit and receive second radar signals ([0075]: “This enables the system 200 to continue to function”);
causing the follower radar device to transmit the local oscillator signal to the leader radar device ([0075]: “with the second IC 220 providing the common LO signal for the system 200”), and wherein the leader radar device is configured to use the second oscillator signal to transmit and receive the second radar signals ([0075]: “This enables the system 200 to continue to function”); and
causing the follower radar device to transmit and receive radar signals using the second local oscillator signal ([0075]: "This enables the system 200 to continue to function").
Tong does not explicitly teach receiving a message from a crystal oscillator operation detection circuit indicating a fault in a first clock generation. However, Reuter teaches using specific circuitry that is able to detect faults in clock and oscillator circuits, and sends an error signal indicating a fault (Reuter [0053]: “each transceiver 310, 320, 330, 340 may be configured to perform a self-test (e.g. to check if the PLL is locked and/or if a transmitted frequency is correct) and to forward an error signal or interrupt signal to the MCU 350 if the self-test results in a fail”; [0055-0056]: teaching reconfiguring the transceiver to switch to using an internal PLL, an internally-generated LO signal, or an internally-generated clock signal based on the error signal.).
It would have been obvious to one of ordinary skill in the art to modify Tong and use specific circuitry to detect faults and receiving a message from the circuitry indicating a fault in a clock generation circuit, as taught by Reuter. Tong is already configured to detect and react to faults, and using specific circuitry to detect and indicate faults is considered ordinary and well-known in the art. Using the specific circuitry to detect and indicate faults is beneficial for detecting faults in specific components and improving fault tolerance of the system.
Regarding Claim 16, Tong teaches: the method further comprising, after detecting the fault in the clock signal generation component of the leader radar device, preventing the leader radar device from generating the first clock signal ([0075]: "the system 200 may be reconfigured from the first to the second configurations described above in response to a fault occurring in the first IC 210"; [0064]: "In this second configuration of the radar system 200, the first transceiver 210 is configured as slave IC, such that the LO output port 212 of the first transceiver 210 is disabled").
Regarding Claim 18, Tong teaches: wherein the leader radar device includes a fault condition and control circuit that is connected to a first local oscillator signal generator and further comprising detecting the fault in the leader radar device … ([0075]: "…in response to a fault occurring in the first IC 210, for example a fault in a VCO block of the first IC while configured as master.").
Tong does not explicitly teach – but Yousuf teaches: detecting the fault in the leader radar device by receiving a flag signal from the fault condition and control circuit (Reuter [0054]: “receiving an error signal”).
It would have been obvious to one of ordinary skill in the art to modify Tong and detect the fault in the leader radar device by receiving a flag signal from the fault condition and control circuit, as taught by Reuter. Error flags/signals are considered ordinary and well-known for use in radar systems. Using error flags/signals is beneficial for making the radar system fault-tolerant, which improves vehicle safety.
Regarding Claim 19, Tong teaches: the method further comprising, after detecting the fault in the leader radar device, transmitting the second clock signal to the leader radar device to enable the leader radar device to continue operating using the second clock signal ([0067]: "Each of the first and second transceivers 210, 220, when configured as master IC, may also transmit other signals (not shown) to the slave IC, such as a common clock signal"; [0075]: "It may still be possible for the first IC 210 to function as a slave").
Regarding Claim 20, Tong teaches: the method further comprising, after detecting the fault in the leader radar device, disabling at least a portion of the clock signal generation component of the leader radar device by way of a central processor ([0075]: "the system 200 may be reconfigured from the first to the second configurations described above in response to a fault occurring in the first IC 210"; [0064]: "In this second configuration of the radar system 200, the first transceiver 210 is configured as slave IC, such that the LO output port 212 of the first transceiver 210 is disabled").
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/NOAH YI MIN ZHU/Examiner, Art Unit 3648
/William Kelleher/Supervisory Patent Examiner, Art Unit 3648