Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This communication is responsive to Amendment filed 3/18/2026.
In Amendment, claims 3 and 13 are cancelled and no claims are added. Thus, claims 1, 2, 4-12, and 14-20 are pending in this application. This Office Action is made final.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-12, and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Verma (US 2013/0318538) in view of Rhee (US 20150/106794).
As per claim 1, Verma discloses a process-implemented method, the method comprising:
based on obtaining a job description on an application, determining a wall clock time of the application according to processes of a corresponding candidate count for each of a plurality of candidate counts (Paragraph 23 “Receiving the job profile can refer to a given node (such as the master node 110) receiving the job profile that was created at another node. Alternatively, receiving the job profile can involve the given node creating the job profile, such as by the job profiler 120 in FIG. 1.”);
determining parallelization efficiency for each of the candidate counts based on the determined wall clock time and a wall clock time of the application according to a single process (Paragraph 30 “Next, a performance model is produced (at 304) based on the job profile and allocated amount of resources for the job (e.g., allocated number of map slots and allocated number of reduce slots). Using the performance model, a performance characteristic of the job is estimated (at 306). For example, this estimation can be performed by the performance characteristic estimator 116 in FIG. 1. In some implementations, the estimated performance characteristic is an estimated completion time of the job (an amount of time for the job to complete execution) given the allocated resources (e.g., number of map slots and number of reduce slots). Alternatively, in other implementations, other performance characteristics of the job on a given set of resources can be estimated. “); and
executing the application with processes of a target count selected based on the determined parallelization efficiency among the plurality of candidate counts (Paragraph 31 “In some implementations, the particular job is executed in a given environment (including a system having a specific arrangement of physical machines and respective map and reduce slots in the physical machines), and the job profile and performance model are applied with respect to the particular job in this given environment.”)
Verma does not expressly disclose but Rhee discloses wherein the determining of the wall clock time comprises, for a call of a function in the application, determining a cumulative latency of a function call context using a unit latency of the function call context and a number of repetitions of the function call context, based on repetition of the function call context (Paragraphs 38-39 “Referring now to FIG. 10, ranking based on total cost is illustrated. Individual call paths are extracted from the calling context tree and the total cost of each path is determined. This example shows a simple scheme that uses the accumulated inferred latency in each node. For example, in the top path (ID 1), the functions D, B, and A respectively have the latency (T4-T1)-(T2-T1)-T4-T3) for A, (T2-T1)-(T2-T1) for B, and (T2-T1) for D. After summing the three latencies, the total for the path becomes T3-T1.
[0039] After the total cost for each path is calculated, the paths are ranked according to the cost. For example, if the first, second and third paths have respective costs of 10, 9, and 9, then the paths are ranked according to the matrix of FIG. 10. Paths are listed from the bottom in the order of their total costs. The path with the highest cost, for example path ID 1, is placed at the bottom of the matrix having the highest rank.”).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Verma to include the teachings of Rhee because it would help a person of ordinary skill in the art determining to total amount of latency occurring across nodes. In this way, the combination benefits from the increased ability to manage the latency of the system.
As per claim 2, Verma further discloses wherein the function call context comprises any one or any combination of any two or more of the application, a parameter of the application, the function, an argument of the function, a call stack of the function, hardware allocated to the function, a mapping relationship between a process and hardware, and a global variable (Paragraph 22).
As per claim 3, Verma further discloses wherein the determining of the latency of the function call context comprises a cumulative latency of the function call context using a unit latency of the function call context and a number of repetitions of the function call context, based on repetition of the function call context (Paragraph 22).
As per claim 4, Verma further discloses wherein the determining of the latency of the function call context comprises determining a number of repetitions of the function call context based on the function call context (Paragraph 22).
As per claim 5, Verma further discloses wherein the determining of the latency of the function call context comprises, in response to a difference between a first function call context and a second function call context being less than or equal to a threshold, determining that one of the first function call context and the second function call context is repeatedly performed (Paragraph 30).
As per claim 6, Verma further discloses wherein the determining of the latency of the function call context comprises, based on the function comprising a plurality of types of operations, determining the latency of the function call context using a coefficient of variation (CV) of a ratio of an operation execution time for each operation type for an operation execution time of the operations (Paragraph 42).
As per claim 7, Verma further discloses further comprising:
obtaining a job description on other applications (Fig. 3, step 302); and
determining latency of a function context called by the other applications using a latency model corresponding to a function in the application, based on the application and the other applications comprising the same function (Fig. 3, step 304).
As per claim 8, Verma further discloses further comprising training a wall clock time model corresponding to the application based on the target count and a wall clock time of the application obtained as a result of executing the application with processes of the target count (Paragraph 30).
As per claim 9, Verma further discloses wherein the training of the wall clock time model comprises, based on other applications comprising a function in the application, training a latency model corresponding to the function using the target count and latency of a function call context obtained as a result of executing a call of the function in the application with processes of the target count (Paragraph 30 and Fig. 3, step 304).
As per claim 10, Verma further discloses wherein the executing of the application comprises selecting a candidate count having a minimum wall clock time as the target count among candidate counts having parallelization efficiency greater than or equal to threshold parallelization efficiency (Paragraph 7 and Fig. 3, step 304).
As per claims 11, 12 and 14-20, they are device claims having similar limitations as cited in claims 1, 2, and 4-10 and are rejected under the same rationale.
Response to Arguments
Applicant's arguments with respect to claims 1, 2, 4-12, and 14-20 have been considered but are moot in view of the new ground(s) of rejection necessitated by Amendment.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY A MUDRICK whose telephone number is (571)270-3374. The examiner can normally be reached 9am-5pm Central Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Pierre Vital can be reached at (571)272-4215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TIMOTHY A MUDRICK/Primary Examiner, Art Unit 2198 4/09/2026
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