DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. JP 2022-168506 filed on 10/20/2022.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/06/2023 was filed in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
[0048]: As written it reads “The amplifier 12 is able to set an amplification factor to any one of multiple amplification factors in accordance with a gain adjustment value GCNT1 […]”. However, this is the first instance of the term “GCNT1”, therefore, the term should be spelled out to provide clarity.
[0050]: As written it reads “The digital shifter 14 can set a shift amount to any one of multiple shift amounts in accordance with a shift adjustment value SCNT”. However, this is the first instance of the term “SCNT”, therefore, the term should be spelled out to provide clarity.
[0055]: As written it reads “The amplitude adjuster 17 adjusts the amplification factor by converting the full scale (full swing amplitude) of the voltage output from the DA converter 16 into any one of multiple full scales in accordance with a full-scale adjustment value FSCNT”. However, this is the first instance of the term “FSCNT”, therefore, the term should be spelled out to provide clarity.
[0121]: As written it reads “The digital multiplier 21 multiplies the multiplier corresponding to a multiplier adjustment value MUL by the digital voltage magnitude […]”. However, this is the first instance of the term “MUL”, therefore, the term should be spelled out to provide clarity.
Appropriate correction is required.
Claim Objections
Claims 7, 15-16 are objected to because of the following informalities:
Regarding claim 7, as written it reads “an analog-to-digital (AD) converter configured to convert the voltage signal amplified by the second amplifier into a digital signa”. However, to correct the typo “signa” should be “signal”.
Regarding claims 15 and 16, as written it reads “An full locked loop (FLL) unit for measuring a biomagnetic field in accordance with a voltage signal output from a SQUID sensor, the FLL unit comprising:” (Claim 15) and “An FLL unit for measuring a biomagnetic field according to a voltage signal output from a SQUID sensor, the FLL unit comprising:”. However, to be grammatically correct “An full locked loop unit” should be “A full locked loop unit” and “An FLL unit” should be “A FLL unit”.
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: a flux locked loop (FLL) unit in claims 1-13, 15 and 16.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. That being said, the FLL unit is describe in the specification when it states “A digital FLL circuit 10 is an example of an FLL unit” [0042]; “A digital FLL circuit 20 is an example of an FLL unit” [0117]; “A digital FLL circuit 10 is an example of an FLL unit” [0137]. Additionally, the Applicant notes that the digital FLL circuit 10 is shown in FIG. 3, digital FLL circuit 20 is shown in FIG. 14 and digital FLL circuit 30 is shown in FIG. 16. Therefore, the examiner is interpreting the FLL unit to be a circuit which includes the components shown in FIGS. 3, 14 or 16. Thus, claims 1-13, 15 and 16 are not subject to further rejection under 35 U.S.C. 112(a)/112(b) with respect to the FLL unit.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f).
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 6-7, 14 and 16 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Regarding claims 6, as written it reads “wherein the second amplifier, the digital shifter, and the amplitude adjuster are each configured to function as the adjustment devices” (Claim 6); “wherein the second amplifier and the digital shifter are configured to function as the adjustment devices” (Claim 7).. However, there is a lack of antecedent basis for the term “the adjustment devices”. Therefore, it is unclear whether this is supposed to be the same as or different from “the adjustment device” recited in claim 2 on which these claims depend.
Regarding claim 14, as written it reads “wherein one or both of the analog integrator and the voltage-to-current converter include an amplification function, wherein the amplification function of the analog integrator is a function of changing an amplification factor of a current signal in accordance with an adjustment value that can be set from outside, wherein the amplification function of the voltage-to-current converter is a function of changing a conversion ratio of a current signal with respect to a voltage signal in accordance with an adjustment value that can be set from outside, and wherein the adjustment device includes the analog integrator having a first amplification function, the voltage-to-current converter having a second amplification function, or both the analog integrator having the first amplification function and the voltage-to-current converter having the second amplification function”.
However, the examiner notes that claim 13, on which this claim depends, recites “a first adjustment value”. Therefore, it is unclear whether “an adjustment value” recited in claim 14 is the same as or different from “a first adjustment value” recited in claim 13. The examiner would recommend amending the claim to further specify which adjustment value is being referred to within the claim.
Regarding claim 16, as written it reads “wherein the second amplifier, the digital shifter, and the amplitude adjuster are each configured to function as the adjustment device configured to adjust a loop gain of the FLL unit”. However, there is a lack of antecedent basis for the term “the adjustment device”. Therefore, it is unclear what is being referred to by this term.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 15 and 16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yasui et al. US 2021/0132161 A1 “Yasui”.
Regarding claim 1, Yasui teaches “A biomagnetic field measurement device to measure a biomagnetic field, the biomagnetic field measurement device comprising:” (“FIG. 1 is a block diagram illustrating an example of a magnetic field measuring apparatus according to a first embodiment of the present invention. For example, a magnetic field measuring apparatus 100 (i.e., a biomagnetic field measuring apparatus) illustrated in FIG. 1 employs a digital FLL system and is applicable to magnetoencephalography, magnetospinography, and magnetocardiography. The magnetic field measuring apparatus 100 illustrated in FIG. 1 may also be applied to the measurement of a neuromagnetic or muscle magnetic field” [0017]. Therefore, the magnetic field measuring apparatus 100 represents a biomagnetic field measurement device to measure a biomagnetic field.);
“a superconducting quantum interference device (SQUID) sensor” (“In biomagnetic field measurement using superconducting quantum interference devices (SQUIDs), which are superconducting rings having Josephson junctions, the measurement characteristics are nonlinear. Thus, a flux locked loop (FLL) circuit is used to linearize and measure the magnetic field” [0003]; “The magnetic field measuring apparatus 100 illustrated in FIG. 1 includes a SQUID 10 and a digital FLL circuit 30 that are provided for each channel, and a data processing device 40 common to multiple digital FLL circuits 30“ [0019]; “The SQUID 10 is a highly sensitive magnetic sensor that detects a magnetic field (i.e., a magnetic flux) that is generated from a living body and that passes through a superconducting ring having a Josephson junction. For example, the SQUID 10 is made by providing Josephson junctions at two positions of the superconducting ring” [0023]. Therefore, the magnetic field measuring apparatus 100 includes a superconducting quantum interference device (SQUID) sensor.); and
“a flux locked loop (FLL) unit including an adjustment device configured to adjust a loop gain of the FLL unit” (See [0003] above, and “The digital FLL circuit 30 includes an amplifier 31, a signal switcher 32, an analog-to-digital (AD) converter 33, a digital integrator 34, a digital-to-analog (DA) converter 35, a voltage current converter 36, a feedback coil 37, and an amplifier 38” [0020]; “During the correction mode, the amplifier 38 amplifies the voltage received from the DA converter 35 by an integer multiple, and outputs the amplified voltage to the AD converter 33 through the signal switcher 32.” [0038]; “For example, a gain of the amplifier 38 is determined such that voltage input to the AD converter 33 in accordance with voltage corresponding to 1 least significant bit (LSB) (i.e., a quantization unit) of the DA converter 35 is greater than or equal to voltage corresponding to 1 LSB of the AD converter 33. In other words, the gain of the amplifier 38 is determined to be 2 to the power (DAn−ADn) or greater based on the difference (DAn−ADn) between a bit number DAn of the DA converter 35 and a bit number ADn of the AD converter 33. In the present embodiment, the gain of the amplifier 38 is set to a scale-factor of 128.” [0039]. Therefore, since the digital FLL circuit 30 includes amplifier 38 which is set to a scale-factor of 128, the magnetic field measuring apparatus 100 includes a flux locked loop (FLL) unit (i.e. digital FLL circuit 30) including an adjustment device (i.e. amplifier 38) configured to adjust a loop gain of the FLL unit.).
Regarding claim 15, Yasui teaches “An full locked loop (FLL) unit for measuring a biomagnetic field in accordance with a voltage signal output from a SQUID sensor, the FLL unit comprising:” (See digital FLL circuit 30 as discussed in [0020], FIG. 1 and “The SQUID 10 generates a voltage that varies periodically with respect to a change of the magnetic flux passing through the superconducting ring” [0024]. As shown in FIG. 1, the SQUID 10 is connected to the amplifier 31 of the digital FLL circuit 30. Therefore, Yasui discloses a full locked loop (FLL) unit for measuring a biomagnetic field in accordance with a voltage signal output from a SQUID sensor.);
“an amplifier configured to amplify a voltage signal output from the SQUID sensor” (“The amplifier 31 amplifies the output voltage generated by the SQUID 10 using the magnetic flux passing through the SQUID 10 in accordance with the strength of the magnetic field during the normal measurement mode, and outputs the amplified output voltage to the AD converter 33 through the signal switcher 32. Additionally, the amplifier 31 has a function to adjust a bias current and adjust offset voltage of the SQUID 10. This enables the amplifier 31 to correct the characteristics of the SQUID 10, which varies among individual devices. The SQUID 10 and the amplifier 31 may be controlled by the CPU 50 to stop an operation during the correction mode” [0028]. Therefore the FLL unit includes an amplifier configured to amplify a voltage signal output from the SQUID sensor.);
“an analog-to-digital (AD) converter configured to convert the voltage signal amplified by the amplifier into a digital signal” (“The AD converter 33 converts an analog signal received through the signal switcher 32 into a digital signal (i.e., a voltage value) and outputs the digital value generated by the conversion to the digital integrator 34. In the normal measurement mode, the AD converter 33 converts the voltage that is output from the SQUID 10 and that is amplified by the amplifier 31 into a digital value, and in the correction mode, the AD converter 33 converts the voltage amplified by the amplifier 38 (for adjusting the offset value) into a digital value. The digital value output by the AD converter 33 is an example of a first digital value” [0029]. Therefore, the FLL unit includes an analog-to-digital converter configured to convert the voltage signal amplified by the amplifier into a digital signal.);
“a digital multiplier configured to multiply, in accordance with an adjustment value, a signal value of the digital signal converted by the AD converter by a multiplier, the multiplier corresponding to the adjustment value to be set from outside” (“During the correction mode, the amplifier 38 amplifies the voltage received from the DA converter 35 by an integer multiple, and outputs the amplified voltage to the AD converter 33 through the signal switcher 32. The voltage output by the DA converter 35 is amplified by the amplifier 38 by the integer multiple to facilitate corresponding the original voltage output by the DA converter 35 to the voltage output by the amplifier 38” [0038]. As shown in FIG. 1, the amplifier 38 only receives a signal after it has been passed through the AD converter 33, the digital integrator 34, and the DA converter. Therefore, since the amplifier 38 amplifies the voltage received from the DA converter by using an integer multiplier to facilitate corresponding the original voltage output by the DA converter 35 to the voltage output by the amplifier 38, the amplifier 38 represents a digital multiplier configured to multiply, in accordance with an adjustment value (i.e. integer multiplier), a signal value of the digital signal converted by the AD converter by a multiplier, the multiplier corresponding to the adjustment value to be set from outside.);
“a digital integrator configured to integrate the signal value of the digital signal multiplied by the digital multiplier to generate integrated data” (“The digital integrator 34 includes a setting value storage unit 34a and an offset value storage unit 34b. For example, the setting value storage unit 34a and the offset value storage unit 34b are volatile and lose stored information when a power supply to the digital FLL circuit 30 is stopped” [0020]. Therefore, the FLL unit includes a digital integrator configured to integrate the signal value of the digital signal multiplied by the digital multiplier to generate integrated data.).;
“a digital-to-analog (DA) converter configured to convert the integrated data generated by the digital integrator into a voltage signal” (“The digital integrator 34 outputs, to the DA converter 35, a digital value obtained by adding an offset value (i.e., a positive value or a negative value) stored in the offset value storage unit 34b to an integral value, which is an integrated voltage value” [0030]; “The DA converter 35 converts the digital value output from the digital integrator 34 to voltage, and outputs the converted voltage to the voltage current converter 36 and the amplifier 38. The digital value that is output from the digital integrator 34 and that is input to the DA converter 35 is an example of a second digital value” [0034]. Therefore, the FLL unit includes a digital-to-analog (DA) converter configured to convert the integrated data generated by the digital integrator into a voltage signal.);
“a voltage-to-current converter configured to convert the voltage signal converted by the DA converter into a current signal” (“The voltage current converter 36 converts the voltage received from the DA converter 35 into a current, and outputs the converted current to the feedback coil 37. During the correction mode, the voltage supply to the voltage current converter 36 may be stopped” [0035]. Therefore, the FLL unit includes a voltage-to-current converter configured to convert the voltage signal converted by the DA converter into a current signal.); and
“a coil configured to feed back the current signal converted by the voltage-to-current converter to the SQUID sensor as a magnetic field” (“The feedback coil 37 generates magnetic flux from the current received from the voltage current converter 36 and feeds back the generated magnetic flux to the SQUID 10 as feedback magnetic flux. That is, the feedback coil 37 generates the magnetic field to be received by the SQUID 10 in accordance with the current from the voltage current converter 36. Feedback of the magnetic flux by the feedback coil 37 enables the voltage generated by the SQUID 10 during the normal measurement mode to be maintained near the working point (i.e., in a linear region) of the Φ-V characteristic, thereby accurately obtaining the biomagnetic field signal” [0037]. Therefore, the FLL unit includes a coil (i.e. feedback coil 37) configured to feed back the current signal converted by the voltage-to-current converter to the SQUID sensor as a magnetic field.), and
“wherein the digital multiplier is configured to function as an adjustment device configured to adjust a loop gain of the FLL unit” (See [0038] above and [0039] as discussed in claim 1 above. Therefore the digital multiplier (i.e. amplifier 38) is configured to function as an adjustment device configured to adjust a loop gain of the FLL unit.).
Regarding claim 16, Yasui teaches “An FLL unit for measuring a biomagnetic field according to a voltage signal output from a SQUID sensor, the FLL unit comprising:” (See digital FLL circuit 30 as discussed in [0020], FIG. 1 and “The SQUID 10 generates a voltage that varies periodically with respect to a change of the magnetic flux passing through the superconducting ring” [0024]. As shown in FIG. 1, the SQUID 10 is connected to the amplifier 31 of the digital FLL circuit 30. Therefore, Yasui discloses a full locked loop (FLL) unit for measuring a biomagnetic field in accordance with a voltage signal output from a SQUID sensor.);
“a first amplifier configured to amplify a voltage signal output from the SQUID sensor” (“The amplifier 31 amplifies the output voltage generated by the SQUID 10 using the magnetic flux passing through the SQUID 10 in accordance with the strength of the magnetic field during the normal measurement mode, and outputs the amplified output voltage to the AD converter 33 through the signal switcher 32. Additionally, the amplifier 31 has a function to adjust a bias current and adjust offset voltage of the SQUID 10. This enables the amplifier 31 to correct the characteristics of the SQUID 10, which varies among individual devices. The SQUID 10 and the amplifier 31 may be controlled by the CPU 50 to stop an operation during the correction mode” [0028]. Therefore the FLL unit includes a first amplifier configured to amplify a voltage signal output from the SQUID sensor.);
“a second amplifier configured to amplify the voltage signal amplified by the first amplifier at any one of a plurality of amplification factors corresponding to a first adjustment value that can be set from outside” (“During the correction mode, the amplifier 38 amplifies the voltage received from the DA converter 35 by an integer multiple, and outputs the amplified voltage to the AD converter 33 through the signal switcher 32. The voltage output by the DA converter 35 is amplified by the amplifier 38 by the integer multiple to facilitate corresponding the original voltage output by the DA converter 35 to the voltage output by the amplifier 38” [0038] and [0039] as discussed in claim 1 above. Therefore, the FLL unit includes a second amplifier configured to amplify the voltage signal amplified by the first amplifier at any one of a plurality of amplification factors corresponding to a first adjustment value that can be set from outside.);
“an analog-to-digital (AD) converter configured to convert the voltage signal amplified by the second amplifier into a digital signal” (“The AD converter 33 converts an analog signal received through the signal switcher 32 into a digital signal (i.e., a voltage value) and outputs the digital value generated by the conversion to the digital integrator 34. In the normal measurement mode, the AD converter 33 converts the voltage that is output from the SQUID 10 and that is amplified by the amplifier 31 into a digital value, and in the correction mode, the AD converter 33 converts the voltage amplified by the amplifier 38 (for adjusting the offset value) into a digital value. The digital value output by the AD converter 33 is an example of a first digital value” [0029]. Therefore, the FLL unit includes an analog-to-digital converter configured to convert the voltage signal amplified by the second amplifier (i.e. amplifier 38) into a digital signal.);
“a digital shifter configured to perform shift processing on a signal value of the digital signal converted by the AD converter by any one of a plurality of shift amounts, the plurality of shift amounts corresponding to a second adjustment value to be set from outside” (“When the number of input bits of the DA converter 35 is greater than the number of output bits of the AD converter 33, error due to the quantization unit of the AD converter 33 in obtaining the offset value can be reduced by providing the amplifier 38. The gain of the amplifier 38 is set to a power of 2, so that, for example, the digital value (binary number) output from the AD converter 33 is shifted to the right only by the number of the power to easily calculate the digital value output from the DA converter 35 before the amplification. That is, the gain of the amplifier 38 is set to a power of 2 so as to facilitate data processing of the data processing device 40 relative to a case in which the gain is not a power of 2” [0043]. Therefore, since the gain of the amplifier 38 is set to a power of 2 (i.e. when the number of input bits of the DA converter 35 is greater than the number of output bits of the AD converter 33), so that the digital value (binary number) output from the AD converter 33 is shifted to the right, amplifier 38 in combination with the AD converter 33 act as a digital shifter configured to perform shift processing on a signal value of the digital signal converted by the AD converter by any one of a plurality of shift amounts, the plurality of shift amounts corresponding to a second adjustment value to be set from outside.);
“a digital integrator configured to integrate the signal value of the digital signal subjected to the shift processing by the digital shifter to generate integrated data” (“The digital integrator 34 includes a setting value storage unit 34a and an offset value storage unit 34b. For example, the setting value storage unit 34a and the offset value storage unit 34b are volatile and lose stored information when a power supply to the digital FLL circuit 30 is stopped” [0020]. Therefore, the FLL unit includes a digital integrator configured to integrate the signal value of the digital signal subjected to the shift processing by the digital shifter to generate integrated data.);
“a digital-to-analog (DA) converter configured to convert the integrated data generated by the digital integrator into a voltage signal” (“The digital integrator 34 outputs, to the DA converter 35, a digital value obtained by adding an offset value (i.e., a positive value or a negative value) stored in the offset value storage unit 34b to an integral value, which is an integrated voltage value” [0030]; “The DA converter 35 converts the digital value output from the digital integrator 34 to voltage, and outputs the converted voltage to the voltage current converter 36 and the amplifier 38. The digital value that is output from the digital integrator 34 and that is input to the DA converter 35 is an example of a second digital value” [0034]. Therefore, the FLL unit includes a digital-to-analog (DA) converter configured to convert the integrated data generated by the digital integrator into a voltage signal.);
“an amplitude adjuster configured to convert a full scale of an output of the DA converter to any one of a plurality of full scales corresponding to a third adjustment value that can be set from outside to adjust to any one of a plurality of amplitudes” (“For example, a gain of the amplifier 38 is determined such that voltage input to the AD converter 33 in accordance with voltage corresponding to 1 least significant bit (LSB) (i.e., a quantization unit) of the DA converter 35 is greater than or equal to voltage corresponding to 1 LSB of the AD converter 33. In other words, the gain of the amplifier 38 is determined to be 2 to the power (DAn−ADn) or greater based on the difference (DAn−ADn) between a bit number DAn of the DA converter 35 and a bit number ADn of the AD converter 33. In the present embodiment, the gain of the amplifier 38 is set to a scale-factor of 128” [0039]. Therefore, since the gain of the amplifier 38 is determined to be 2 to the power (Dan-ADn) or greater, such as setting it to a scale-factor of 128, the amplifier 38 represents an amplitude adjuster configured to convert a full scale of an output of the DA converter to any one of a plurality of full scales corresponding to a third adjustment value that can be set from outside to adjust to any one of a plurality of amplitudes.);
“a voltage-to-current converter configured to convert the voltage signal whose voltage magnitude is changed by converting the full scale by the amplitude adjuster into a current signal” (“The voltage current converter 36 converts the voltage received from the DA converter 35 into a current, and outputs the converted current to the feedback coil 37. During the correction mode, the voltage supply to the voltage current converter 36 may be stopped” [0035]. Therefore, the FLL unit includes a voltage-to-current converter configured to convert the voltage signal whose magnitude is changed by converting the full scale by the amplitude adjuster into a current signal.); and
“a coil configured to feed back the current signal converted by the voltage-to-current converter to the SQUID sensor as a magnetic field” (“The feedback coil 37 generates magnetic flux from the current received from the voltage current converter 36 and feeds back the generated magnetic flux to the SQUID 10 as feedback magnetic flux. That is, the feedback coil 37 generates the magnetic field to be received by the SQUID 10 in accordance with the current from the voltage current converter 36. Feedback of the magnetic flux by the feedback coil 37 enables the voltage generated by the SQUID 10 during the normal measurement mode to be maintained near the working point (i.e., in a linear region) of the Φ-V characteristic, thereby accurately obtaining the biomagnetic field signal” [0037]. Therefore, the FLL unit includes a coil (i.e. feedback coil 37) configured to feed back the current signal converted by the voltage-to-current converter to the SQUID sensor as a magnetic field.), and
“wherein the second amplifier, the digital shifter, and the amplitude adjuster are each configured to function as the adjustment device configured to adjust a loop gain of the FLL unit” (See amplifier 38, in combination with the AD converter 33 as discussed in paragraphs [0038], [0039] and [0043] above. Therefore, the second amplifier, the digital shifter, and the amplitude adjuster are each configured to function as the adjustment device configured to adjust a loop gain of the FLL unit.).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2-14 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yasui US 2021/0132161 A1 “Yasui” as applied to claim 1 above, and further in view of Yasui et al. US 2021/0103012 A1 “Yasui-2”.
Regarding claim 2, Yasui discloses all features of the claimed invention as discussed with respect to claim 1 above, and Yasui further teaches "wherein the SQUID sensor and the FLL unit are configured to measure an induced magnetic field generated by applying electrical stimulation to a living body […]” (See [0003] and [0023] as discussed in claim 1 above. In this case, since the magnetic field measuring apparatus 100 measures a magnetic field and includes the SQUID 10 and the FLL circuit 30, the SQUID sensor and the FLL unit are configured to measure an induced magnetic field generated by applying electrical stimulation to a living body.), and
“wherein the adjustment device is configured to adjust the loop gain of the FLL unit in accordance with an adjustment value settable from outside the biomagnetic field measurement device” (“The CPU 50 controls an overall operation of the magnetic field measuring apparatus 100. The CPU 50 controls each digital FLL circuit 30 to obtain the offset value for the digital FLL circuit 30 itself during the correction mode. For example, the CPU 50 successively stores the setting value within a predetermined range including “0” in the setting value storage unit 34a and successively inputs the setting value stored in the setting value storage unit 34a to the DA converter 35” [0044]. As shown in FIG. 1, the data processing device 40 (i.e. containing the CPU 50) is located separately from the SQUID 10 and the digital FLL circuit 30. Therefore, since the CPU 50 controls each digital FLL circuit 30 (i.e. which includes the amplifier 38, see [0038]-[0039]), stores the setting value within the setting value storage unit, and inputs those values to the DA converter 35, the adjustment device is configured to adjust the loop gain of the FLL unit in accordance with an adjustment value settable from outside the biomagnetic field measurement device.).
Although Yasui discloses “FIG. 1 employs a digital FLL system and is applicable to magnetoencephalography, magnetospinography, and magnetocardiography” [0017], Yasui does not explicitly teach “an electrical stimulation input device”.
Yasui-2 teaches “an electrical stimulation input device” (“In recent years, the magnetic field measuring apparatus 100A is applied not only to the magnetocardiograph (MCG) and the magnetoencephalograph (MEG), but also popularly applied to the magnetospinograph (MSG). The magnetospinograph (MSG) inputs an external electrical stimulation, and measures the biomagnetic field induced by the electrical stimulation” [0040]; “Because the large artifact also occurs when measuring the biomagnetic field by the magnetoencephalograph (MEG) in a state where the electrical stimulation is applied to the vagus nerve, the wide dynamic range is required to measure the biomagnetic field” [0041].
Therefore, an electrical stimulation input device is present to provide electrical stimulation (i.e. to perform a magnetospinograph).).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the biomagnetic field measurement device of Yasui such that it includes an electrical stimulation input device as disclosed in Yasui-2 in order to effectively provide an electrical stimulus to a living body to induce a magnetic field for performing an assessment. An electrical stimulation input device (i.e. for magnetospinography) is one of a finite number of devices which can be used to induce a magnetic field with a reasonable expectation of success. Thus, modifying the biomagnetic field measurement device od Yasui such that it includes an electrical stimulation input device as disclosed in Yasui-2 would yield the predictable result of effectively providing an electrical stimulus to a living body to induce a magnetic field for performing an assessment.
Regarding claim 3, Yasui in view of Yasui-2 discloses all features of the claimed invention as discussed with respect to claim 2 above, and Yasui further teaches "wherein the adjustment value is set in accordance with a location or a measurement site of the living body to which the electrical stimulation is applied […]” (“Table 1 indicates an example of the magnetic sensitivity (T), the signal bandwidth (Hz), and the number of channels for measuring biomagnetic signals for each application (i.e., each object to be measured). As shown in Table 1, the magnetic sensitivity, the signal bandwidth, and number of channels that are required for measuring the biomagnetic field differ in magnetospinography (MSG), magnetocardiography (MCG), and magnetoencephalography (MEG). The number of channels differs according to a location of the measurement and a shape, and tends to increase in the future with the advance in the technology of analyzing biomagnetic signals” [0018]; “The offset value obtained for each digital FLL circuit 30 is stored in the offset value storage unit 34b of the digital FLL circuit 30 itself. The offset value is used to correct the variation in the characteristics of the digital FLL circuits 30 that is generated in accordance with the circuit characteristics of the AD converters 33, the DA converters 35, or the like mounted in the digital FLL circuits 30 in the normal measurement mode” [0033]; “The CPU 50 writes the determined offset value to the non-volatile memory 70. Subsequently, when the magnetic field measuring apparatus 100 is started, the CPU 50 reads out the offset value for each digital FLL circuit 30 from the non-volatile memory 70 and stores the read offset value in the offset value storage unit 34b of the corresponding digital FLL circuit 30.” [0047]; “This enables the magnetic field measuring apparatus 100 to accurately measure the biomagnetic field in the normal measurement mode by using an appropriate offset value obtained in the correction mode. In other words, even when there is variation in the characteristics of the digital FLL circuits 30, the variation can be corrected by the offset value, thereby suppressing the degradation of the magnetic flux measurement performance of the magnetic field measuring apparatus 100” [0048].
Therefore, since the number of channels that are required for measuring the biomagnetic field differ in magnetospinography (MSG), magnetocardiography (MCG), and magnetoencephalography (MEG), the number of channels differs according to a location of the measurement and a shape, and the CPU reads out the offset value for each digital FLL circuit 30 (i.e. containing amplifier 38) such that variation can be corrected by the offset value stored in the memory, the adjustment value is set in accordance with a location or a measurement site of the living body to which the electrical stimulation is applied.);
Yasui-2 further teaches “the electrical stimulation input device” (See Yasui-2 [0040] and [0041] as discussed in claim 2 above.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the biomagnetic field measurement device of Yasui such that it includes an electrical stimulation input device as disclosed in Yasui-2 in order to effectively provide an electrical stimulus to a living body to induce a magnetic field for performing an assessment. An electrical stimulation input device (i.e. for magnetospinography) is one of a finite number of devices which can be used to induce a magnetic field with a reasonable expectation of success. Thus, modifying the biomagnetic field measurement device od Yasui such that it includes an electrical stimulation input device as disclosed in Yasui-2 would yield the predictable result of effectively providing an electrical stimulus to a living body to induce a magnetic field for performing an assessment.
Regarding claim 4, Yasui in view of Yasui-2 discloses all features of the claimed invention as discussed with respect to claim 2 above, and Yasui further teaches "further comprising: a second biomagnetic field measurement device including the SQUID sensor and the FLL unit” (“The magnetic field measuring apparatus 100 illustrated in FIG. 1 includes a SQUID 10 and a digital FLL circuit 30 that are provided for each channel, and a data processing device 40 common to multiple digital FLL circuits 30. The magnetic field measuring apparatus 100 may have tens or hundreds of channels, for example, but the number of channels is not limited to this” [0019]. As shown in FIG. 1, there are multiple SQUID 10 sensors and multiple digital FLL circuits 30. Therefore, the biomagnetic field measurement device further comprises a second biomagnetic field measurement device including a SQUID sensor and a FLL unit.);
“wherein, in each of the biomagnetic field measurement device and the second biomagnetic field measurement device, the adjustment device is configured to set the adjustment value corresponding to a characteristic of the SQUID sensor that is included in a corresponding biomagnetic field measurement device” (See [0039] as discussed in claim 1 above and [0044] as discussed in claim 2 above. In this case, each of the digital FLL circuits includes an amplifier 38 which adjusts the gain of the signal it receives from the DA converter 35 (see FIG. 1). Therefore, in each of the biomagnetic field measurement device and the second biomagnetic field measurement device, the adjustment device is configured to set the adjustment value corresponding to a characteristic of the SQUID sensor that is included in a corresponding biomagnetic field measurement device.).
Regarding claim 5, Yasui in view of Yasui-2 discloses all features of the claimed invention as discussed with respect to claim 2 above, and Yasui further teaches "wherein the FLL unit includes: an amplifier configured to amplify a voltage signal output from the SQUID sensor” (“The amplifier 31 amplifies the output voltage generated by the SQUID 10 using the magnetic flux passing through the SQUID 10 in accordance with the strength of the magnetic field during the normal measurement mode, and outputs the amplified output voltage to the AD converter 33 through the signal switcher 32. Additionally, the amplifier 31 has a function to adjust a bias current and adjust offset voltage of the SQUID 10. This enables the amplifier 31 to correct the characteristics of the SQUID 10, which varies among individual devices. The SQUID 10 and the amplifier 31 may be controlled by the CPU 50 to stop an operation during the correction mode” [0028]. Therefore, the FLL unit includes: an amplifier configured to amplify a voltage signal output from the SQUID sensor.);
“an analog-to-digital (AD) converter configured to convert the voltage signal amplified by the amplifier into a digital signal” (“The AD converter 33 converts an analog signal received through the signal switcher 32 into a digital signal (i.e., a voltage value) and outputs the digital value generated by the conversion to the digital integrator 34. In the normal measurement mode, the AD converter 33 converts the voltage that is output from the SQUID 10 and that is amplified by the amplifier 31 into a digital value, and in the correction mode, the AD converter 33 converts the voltage amplified by the amplifier 38 (for adjusting the offset value) into a digital value” [0029]. Therefore, the FLL unit includes an analog-to-digital (AD) converter configured to convert the voltage signal amplified by the amplifier into a digital signal.),
“a digital multiplier configured to multiply a signal value of the digital signal converted by the AD converter, by a multiplier corresponding to the adjustment value” (“During the correction mode, the amplifier 38 amplifies the voltage received from the DA converter 35 by an integer multiple, and outputs the amplified voltage to the AD converter 33 through the signal switcher 32. The voltage output by the DA converter 35 is amplified by the amplifier 38 by the integer multiple to facilitate corresponding the original voltage output by the DA converter 35 to the voltage output by the amplifier 38” [0038]. As shown in FIG. 1, the amplifier 38 receives the signal once it has passed through the AD converter 33, the digital integrator 34 and the DA converter 35. Therefore, since the amplifier 38 amplifies the voltage received from the DA converter 35 by an integer multiple during the correction mode, the amplifier 38 represents a digital multiplier configured to multiply a signal value of the digital signal converted by the AD converter, by a multiplier corresponding to the adjustment value.),
“a digital integrator configured to integrate the signal value of the digital signal multiplied by the digital multiplier to generate integrated data” (See [0029] and [0038] above, and “The digital integrator 34 integrates changes in the voltage of the SQUID 10 (precisely, the amplified voltage output from the amplifier 31) from a working point (or a locking point), which is a starting point of each period of the Φ-V characteristic, during normal measurement mode. The digital integrator 34 outputs, to the DA converter 35, a digital value obtained by adding an offset value (i.e., a positive value or a negative value) stored in the offset value storage unit 34b to an integral value, which is an integrated voltage value. Because the offset value is set to suppress the variation in accordance with the variation in characteristics of the digital FLL circuit 30, the variation in characteristics between channels can be reduced” [0030]. Therefore, the FLL unit includes a digital integrator configured to integrate the signal value of the digital signal multiplied by the digital multiplier to generate integrated data.),
“a digital-to-analog (DA) converter configured to convert the integrated data generated by the digital integrator into a voltage signal” (“The DA converter 35 converts the digital value output from the digital integrator 34 to voltage, and outputs the converted voltage to the voltage current converter 36 and the amplifier 38. The digital value that is output from the digital integrator 34 and that is input to the DA converter 35 is an example of a second digital value” [0034]. Therefore, the FLL unit includes a digital-to-analog (DA) converter configured to convert the integrated data generated by the digital integrator into a voltage signal.),
“a voltage-to-current converter configured to convert the voltage signal converted by the DA converter into a current signal” (“The voltage current converter 36 converts the voltage received from the DA converter 35 into a current, and outputs the converted current to the feedback coil 37. During the correction mode, the voltage supply to the voltage current converter 36 may be stopped” [0035]. Therefore, the FLL unit includes a voltage-to-current converter configured to convert the voltage signal converted by the DA converter into a current signal.), and
“a coil configured to feed back the current signal converted by the voltage-to-current converter to the SQUID sensor as a magnetic field” (“The feedback coil 37 generates magnetic flux from the current received from the voltage current converter 36 and feeds back the generated magnetic flux to the SQUID 10 as feedback magnetic flux. That is, the feedback coil 37 generates the magnetic field to be received by the SQUID 10 in accordance with the current from the voltage current converter 36. Feedback of the magnetic flux by the feedback coil 37 enables the voltage generated by the SQUID10 during the normal measurement mode to be maintained near the working point (i.e., in a linear region) of the Φ-V characteristic, thereby accurately obtaining the biomagnetic field signal” [0037]. Therefore, the FLL unit includes a coil (i.e. feedback coil 37) configured to feed back the current signal converted by the voltage-to-current converter to the SQUID sensor as a magnetic field.), and
“wherein the digital multiplier is configured to function as the adjustment device” (See [0038] as discussed above. Therefore, the digital multiplier (i.e. amplifier 38) is configured to function as the adjustment device.).
Regarding claim 6, Yasui in view of Yasui-2 discloses all features of the claimed invention as discussed with respect to claim 1 above, and Yasui further teaches "wherein the FLL unit includes: a first amplifier configured to amplify a voltage signal output from the SQUID sensor” (See digital FLL circuit 30 as discussed in [0020], FIG. 1 and [0028] as discussed in claim 16 above. Therefore, the FLL unit includes a first amplifier (i.e. amplifier 31) configured to amplify a voltage signal output from the SQUID sensor.);
“a second amplifier configured to amplify the voltage signal amplified by the first amplifier at any one of a plurality of amplification factors, the plurality of amplification factors corresponding to a first adjustment value to be set from outside” (See [0038] as discussed in claim 16 above and [0039] as discussed in claim 1 above. Therefore, the FLL unit includes a second amplifier (i.e. amplifier 38) configured to amplify the voltage signal amplified by the first amplifier at any one of a plurality of amplification factors, the plurality of amplification factors corresponding to a first adjustment value to be set from outside.),
“an analog-to-digital (AD) converter configured to convert the voltage signal amplified by the second amplifier into a digital signal” (See [0029] as discussed in claim 16 above. Therefore, the FLL unit includes an analog-to-digital (AD) converter configured to convert the voltage signal amplified by the second amplifier into a digital signal.),
“a digital shifter configured to perform shift processing on a signal value of the digital signal converted by the AD converter, by any one of a plurality of shift amounts, the plurality of shift amounts corresponding to a second adjustment value to be set from outside” (See [0043] as discussed in claim 16 above. Therefore, since the gain of the amplifier 38 is set to a power of 2 (i.e. when the number of input bits of the DA converter 35 is greater than the number of output bits of the AD converter 33), so that the digital value (binary number) output from the AD converter 33 is shifted to the right, amplifier 38 in combination with the AD converter 33 act as a digital shifter configured to perform shift processing on a signal value of the digital signal converted by the AD converter by any one of a plurality of shift amounts, the plurality of shift amounts corresponding to a second adjustment value to be set from outside.),
“a digital integrator configured to integrate the signal value of the digital signal subjected to the shift processing by the digital shifter to generate integrated data” (See [0020] as discussed in claim 16 above. Therefore, the FLL unit includes a digital integrator (i.e. 34) configured to integrate the signal value of the digital signal subjected to the shift processing by the digital shifter (i.e. amplifier 38 in combination with AD converter 33) to generate integrated data.),
“a digital-to-analog (DA) converter configured to convert the integrated data generated by the digital integrator into a voltage signal” (See [0030] and [0034] as discussed in claim 16 above. Therefore, the FLL unit includes a digital-to-analog (DA) converter configured to convert the integrated data generated by the digital integrator into a voltage signal.),
“an amplitude adjuster configured to convert a full scale of an output of the DA converter to any one of a plurality of full scales to adjust to any one of a plurality of amplitudes, the plurality of full scales corresponding to a third adjustment value to be set from outside” (See [0039] as discussed in claim 16 above. Therefore, since the gain of the amplifier 38 is determined to be 2 to the power (Dan-ADn) or greater, such as setting it to a scale-factor of 128, the amplifier 38 represents an amplitude adjuster configured to convert a full scale of an output of the DA converter to any one of a plurality of full scales to adjust to any one of a plurality of amplitudes, the plurality of full scales corresponding to a third adjustment value to be set from outside.);
“a voltage-to-current converter configured to convert the voltage signal whose voltage magnitude is changed by converting the full scale by the amplitude adjuster into a current signal” (See [0035] as discussed in claim 16 above. Therefore, the FLL unit includes a voltage-to-current converter (i.e. 36) configured to convert the voltage signal whose magnitude is changed by converting the full scale by the amplitude adjuster into a current signal.), and
“a coil configured to feed back the current signal converted by the voltage-to-current converter to the SQUID sensor as a magnetic field” (See [0037] as discussed in claim 16 above. Therefore, the FLL unit includes a coil (i.e. feedback coil 37) configured to feed back the current signal converted by the voltage-to-current converter to the SQUID sensor as a magnetic field.), and
“wherein the second amplifier, the digital shifter, and the amplitude adjuster are each configured to function as the adjustment devices” (See amplifier 38, in combination with the AD converter 33 as discussed in paragraphs [0038], [0039] and [0043] above. Therefore, the second amplifier, the digital shifter, and the amplitude adjuster are each configured to function as the adjustment device configured to adjust a loop gain of the FLL unit.).
Regarding claim 7, Yasui in view of Yasui-2 discloses all features of the claimed invention as discussed with respect to claim 2 above, and Yasui further teaches "wherein the FLL unit includes: a first amplifier configured to amplify a voltage signal output from the SQUID sensor” (See digital FLL circuit 30 as discussed in [0020], FIG. 1 and [0028] as discussed in claim 16 above. Therefore, the FLL unit includes a first amplifier (i.e. amplifier 31) configured to amplify a voltage signal output from the SQUID sensor.);
“a second amplifier configured to amplify the voltage signal amplified by the first amplifier at any one of a plurality of amplification factors, the plurality of amplification factors corresponding to a first adjustment value to be set from outside” (See [0038] as discussed in claim 16 above and [0039] as discussed in claim 1 above. Therefore, the FLL unit includes a second amplifier (i.e. amplifier 38) configured to amplify the voltage signal amplified by the first amplifier at any one of a plurality of amplification factors, the plurality of amplification factors corresponding to a first adjustment value to be set from outside.),
“an analog-to-digital (AD) converter configured to convert the voltage signal amplified by the second amplifier into a digital signal” (See [0029] as discussed in claim 16 above. As shown in FIG. 1, the amplifiers 31 and 38 both output to the AD converter 33 via the signal switcher 32. Therefore, the FLL unit includes an analog-to-digital (AD) converter (i.e. 33) configured to convert the voltage signal amplified by the second amplifier (i.e. 38) into a digital signal.),
“a digital shifter configured to perform shift processing on a signal value of the digital signal converted by the AD converter by any one of a plurality of shift amounts, the plurality of shift amounts corresponding to a second adjustment value to be set from outside” (See [0043] as discussed in claim 16 above. Therefore, since the gain of the amplifier 38 is set to a power of 2 (i.e. when the number of input bits of the DA converter 35 is greater than the number of output bits of the AD converter 33), so that the digital value (binary number) output from the AD converter 33 is shifted to the right, amplifier 38 in combination with the AD converter 33 act as a digital shifter configured to perform shift processing on a signal value of the digital signal converted by the AD converter by any one of a plurality of shift amounts, the plurality of shift amounts corresponding to a second adjustment value to be set from outside.),
“a digital integrator configured to integrate the signal value of the digital signal subjected to the shift processing by the digital shifter to generate integrated data” (See [0020] as discussed in claim 16 above. Therefore, the FLL unit includes a digital integrator (i.e. 34) configured to integrate the signal value of the digital signal subjected to the shift processing by the digital shifter (i.e. amplifier 38 in combination with AD converter 33) to generate integrated data.),
“a digital-to-analog (DA) converter configured to convert the integrated data generated by the digital integrator into a voltage signal” (See [0030] and [0034] as discussed in claim 16 above. Therefore, the FLL unit includes a digital-to-analog (DA) converter (i.e. 35) configured to convert the integrated data generated by the digital integrator into a voltage signal.),
“a voltage-to-current converter configured to convert the voltage signal converted by the DA converter into a current signal” (See [0035] as discussed in claim 16 above. Therefore, the FLL unit includes a voltage-to-current converter (i.e. 36) configured to convert the voltage signal whose magnitude is changed by converting the full scale by the amplitude adjuster into a current signal.), and
“a coil configured to feed back the current signal converted by the voltage-to-current converter to the SQUID sensor as a magnetic field” (See [0037] as discussed in claim 16 above. Therefore, the FLL unit includes a coil (i.e. feedback coil 37) configured to feed back the current signal converted by the voltage-to-current converter to the SQUID sensor as a magnetic field.), and
“wherein the second amplifier and the digital shifter are configured to function as the adjustment devices” (See amplifier 38, in combination with the AD converter 33 as discussed in paragraphs [0038], [0039] and [0043] above. Therefore, the second amplifier, and the digital shifter (i.e. amplifier 38 in combination with the AD converter 33) and are each configured to function as the adjustment device configured to adjust a loop gain of the FLL unit.).
Regarding claim 8, Yasui in view of Yasui-2 discloses all features of the claimed invention as discussed with respect to claim 2 above, and Yasui further teaches "wherein the FLL unit includes: a first amplifier configured to amplify a voltage signal output from the SQUID sensor” (See digital FLL circuit 30 as discussed in [0020], FIG. 1 and [0028] as discussed in claim 16 above. Therefore, the FLL unit includes a first amplifier (i.e. amplifier 31) configured to amplify a voltage signal output from the SQUID sensor.),
“an analog-to-digital (AD) converter configured to convert the voltage signal amplified by the first amplifier into a digital signal” (See [0029] as discussed in claim 16 above. As shown in FIG. 1, the amplifiers 31 and 38 both output to the AD converter 33 via the signal switcher 32. Therefore, the FLL unit includes an analog-to-digital (AD) converter (i.e. 33) configured to convert the voltage signal amplified by the first amplifier (i.e. 31) into a digital signal.),
“a digital shifter configured to perform shift processing on a signal value of the digital signal converted by the AD converter by any one of a plurality of shift amounts, the plurality of shift amounts corresponding to a first adjustment value to be set from outside” (See [0043] as discussed in claim 16 above. Therefore, since the gain of the amplifier 38 is set to a power of 2 (i.e. when the number of input bits of the DA converter 35 is greater than the number of output bits of the AD converter 33), so that the digital value (binary number) output from the AD converter 33 is shifted to the right, amplifier 38 in combination with the AD converter 33 act as a digital shifter configured to perform shift processing on a signal value of the digital signal converted by the AD converter by any one of a plurality of shift amounts, the plurality of shift amounts corresponding to a first adjustment value to be set from outside.);
“a digital integrator configured to integrate the signal value of the digital signal subjected to the shift processing by the digital shifter to generate integrated data” (See [0020] as discussed in claim 16 above. Therefore, the FLL unit includes a digital integrator (i.e. 34) configured to integrate the signal value of the digital signal subjected to the shift processing by the digital shifter (i.e. amplifier 38 in combination with AD converter 33) to generate integrated data.),
“a digital-to-analog (DA) converter configured to convert the integrated data generated by the digital integrator into a voltage signal” (See [0030] and [0034] as discussed in claim 16 above. Therefore, the FLL unit includes a digital-to-analog (DA) converter (i.e. 35) configured to convert the integrated data generated by the digital integrator into a voltage signal.),
“an amplitude adjuster configured to convert a full scale of an output of the DA converter to any one of a plurality of full scales to adjust to any one of a plurality of amplitudes, the plurality of full scales corresponding to a second adjustment value to be set from outside” (See [0039] as discussed in claim 16 above. Therefore, since the gain of the amplifier 38 is determined to be 2 to the power (Dan-ADn) or greater, such as setting it to a scale-factor of 128, the amplifier 38 represents an amplitude adjuster configured to convert a full scale of an output of the DA converter to any one of a plurality of full scales to adjust to any one of a plurality of amplitudes, the plurality of full scales corresponding to a second adjustment value to be set from outside.),
“a voltage-to-current converter configured to convert the voltage signal whose voltage magnitude is changed by converting the full scale by the amplitude adjuster into a current signal” (See [0035] as discussed in claim 16 above. Therefore, the FLL unit includes a voltage-to-current converter (i.e. 36) configured to convert the voltage signal whose magnitude is changed by converting the full scale by the amplitude adjuster into a current signal.), and
“a coil configured to feed back the current signal converted by the voltage-to-current converter to the SQUID sensor as a magnetic field” (See [0037] as discussed in claim 16 above. Therefore, the FLL unit includes a coil (i.e. feedback coil 37) configured to feed back the current signal converted by the voltage-to-current converter to the SQUID sensor as a magnetic field.), and
“wherein the digital shifter and the amplitude adjuster are each configured to function as the adjustment device” (See [0043] and [0039] as discussed above. Therefore the digital shifter (i.e. amplifier 38 in combination with the AD converter 33) and the amplitude adjuster (i.e. 38) are each configured to function as the adjustment device.).
Regarding claim 9, Yasui in view of Yasui-2 discloses all features of the claimed invention as discussed with respect to claim 2 above, and Yasui further teaches "wherein the FLL unit includes: a first amplifier configured to amplify a voltage signal output from the SQUID sensor” (See digital FLL circuit 30 as discussed in [0020], FIG. 1 and [0028] as discussed in claim 16 above. Therefore, the FLL unit includes a first amplifier (i.e. amplifier 31) configured to amplify a voltage signal output from the SQUID sensor.),
“a second amplifier configured to amplify the voltage signal amplified by the first amplifier at any one of a plurality of amplification factors, the plurality of amplification factors corresponding to a first adjustment value to be set from outside” (See [0038] as discussed in claim 16 above and [0039] as discussed in claim 1 above. Therefore, the FLL unit includes a second amplifier (i.e. amplifier 38) configured to amplify the voltage signal amplified by the first amplifier at any one of a plurality of amplification factors, the plurality of amplification factors corresponding to a first adjustment value to be set from outside.),
“an analog-to-digital (AD) converter configured to convert the voltage signal amplified by the second amplifier into a digital signal” (See [0029] as discussed in claim 16 above. As shown in FIG. 1, the amplifiers 31 and 38 both output to the AD converter 33 via the signal switcher 32. Therefore, the FLL unit includes an analog-to-digital (AD) converter (i.e. 33) configured to convert the voltage signal amplified by the second amplifier (i.e. 38) into a digital signal.),
“a digital integrator configured to integrate a signal value of the digital signal converted by the AD converter to generate integrated data” (See [0020] as discussed in claim 16 above. Therefore, the FLL unit includes a digital integrator (i.e. 34) configured to integrate a signal value of the digital signal converted by the AD converter (i.e. 33) to generate integrated data.),
“a digital-to-analog (DA) converter configured to convert the integrated data generated by the digital integrator into a voltage signal” (See [0030] and [0034] as discussed in claim 16 above. Therefore, the FLL unit includes a digital-to-analog (DA) converter (i.e. 35) configured to convert the integrated data generated by the digital integrator into a voltage signal.),
“an amplitude adjuster configured to convert a full scale of an output of the DA converter to any one of a plurality of full scales to adjust to any one of a plurality of amplitudes, the plurality of full scales corresponding to a second adjustment value to be set from outside” (See [0039] as discussed in claim 16 above. Therefore, since the gain of the amplifier 38 is determined to be 2 to the power (Dan-ADn) or greater, such as setting it to a scale-factor of 128, the amplifier 38 represents an amplitude adjuster configured to convert a full scale of an output of the DA converter to any one of a plurality of full scales to adjust to any one of a plurality of amplitudes, the plurality of full scales corresponding to a second adjustment value to be set from outside.),
“a voltage-to-current converter configured to convert the voltage signal whose voltage magnitude is changed by converting the full scale by the amplitude adjuster into a current signal” (See [0035] as discussed in claim 16 above. Therefore, the FLL unit includes a voltage-to-current converter (i.e. 36) configured to convert the voltage signal whose magnitude is changed by converting the full scale by the amplitude adjuster into a current signal.), and
“a coil configured to feed back the current signal converted by the voltage-to-current converter to the SQUID sensor as a magnetic field” (See [0037] as discussed in claim 16 above. Therefore, the FLL unit includes a coil (i.e. feedback coil 37) configured to feed back the current signal converted by the voltage-to-current converter to the SQUID sensor as a magnetic field.), and
“wherein the second amplifier and the amplitude adjuster are each configured to function as the adjustment device” (See [0038] and [0039] above. Therefore, the second amplifier (i.e. amplifier 38) see [0038]) and the amplitude adjuster (i.e. amplifier 38, see [0039]) are each configured to function as the adjustment device.).
Regarding claim 10, Yasui in view of Yasui-2 discloses all features of the claimed invention as discussed with respect to claim 2 above, and Yasui further teaches "wherein the FLL unit includes: a first amplifier configured to amplify a voltage signal output from the SQUID sensor” (See digital FLL circuit 30 as discussed in [0020], FIG. 1 and [0028] as discussed in claim 16 above. Therefore, the FLL unit includes a first amplifier (i.e. amplifier 31) configured to amplify a voltage signal output from the SQUID sensor.),
“a second amplifier configured to amplify the voltage signal amplified by the first amplifier at any one of a plurality of amplification factors, the plurality of amplification factors corresponding to the adjustment value to be set from outside” (See [0038] as discussed in claim 16 above and [0039] as discussed in claim 1 above. Therefore, the FLL unit includes a second amplifier (i.e. amplifier 38) configured to amplify the voltage signal amplified by the first amplifier at any one of a plurality of amplification factors, the plurality of amplification factors corresponding to the adjustment value to be set from outside.),
“an analog-to-digital (AD) converter configured to convert the voltage signal amplified by the second amplifier into a digital signal” (See [0029] as discussed in claim 16 above. As shown in FIG. 1, the amplifiers 31 and 38 both output to the AD converter 33 via the signal switcher 32. Therefore, the FLL unit includes an analog-to-digital (AD) converter (i.e. 33) configured to convert the voltage signal amplified by the second amplifier (i.e. 38) into a digital signal.),
“a digital integrator configured to integrate a signal value of the digital signal converted by the AD converter to generate integrated data” (See [0020] as discussed in claim 16 above. Therefore, the FLL unit includes a digital integrator (i.e. 34) configured to integrate a signal value of the digital signal converted by the AD converter (i.e. 33) to generate integrated data.),
“a digital-to-analog (DA) converter configured to convert the integrated data generated by the digital integrator into a voltage signal” (See [0030] and [0034] as discussed in claim 16 above. Therefore, the FLL unit includes a digital-to-analog (DA) converter (i.e. 35) configured to convert the integrated data generated by the digital integrator into a voltage signal.),
“a voltage-to-current converter configured to convert the voltage signal converted by the DA converter into a current signal” (See [0035] as discussed in claim 16 above. Therefore, the FLL unit includes a voltage-to-current converter (i.e. 36) configured to convert the voltage signal converted by the DA converter (i.e. 35) into a current signal.), and
“a coil configured to feed back the current signal converted by the voltage-to-current converter to the SQUID sensor as a magnetic field” (See [0037] as discussed in claim 16 above. Therefore, the FLL unit includes a coil (i.e. feedback coil 37) configured to feed back the current signal converted by the voltage-to-current converter to the SQUID sensor as a magnetic field.), and
“wherein the second amplifier is configured to function as the adjustment device” (See [0038] and [0039] above. Therefore, the second amplifier is configured to function as the adjustment device.).
Regarding claim 11, Yasui in view of Yasui-2 discloses all features of the claimed invention as discussed with respect to claim 2 above, and Yasui further teaches "wherein the FLL unit includes: a first amplifier configured to amplify a voltage signal output from the SQUID sensor” (See digital FLL circuit 30 as discussed in [0020], FIG. 1 and [0028] as discussed in claim 16 above. Therefore, the FLL unit includes a first amplifier (i.e. amplifier 31) configured to amplify a voltage signal output from the SQUID sensor.),
“an analog-to-digital (AD) converter configured to convert the voltage signal amplified by the first amplifier into a digital signal” (See [0029] as discussed in claim 16 above. As shown in FIG. 1, the amplifiers 31 and 38 both output to the AD converter 33 via the signal switcher 32. Therefore, the FLL unit includes an analog-to-digital (AD) converter (i.e. 33) configured to convert the voltage signal amplified by the first amplifier (i.e. 31) into a digital signal.),
“a digital shifter configured to perform shift processing on a signal value of the digital signal converted by the AD converter by any one of a plurality of shift amounts, the plurality of shift amounts corresponding to the adjustment value to be set from outside” (See [0043] as discussed in claim 16 above. Therefore, since the gain of the amplifier 38 is set to a power of 2 (i.e. when the number of input bits of the DA converter 35 is greater than the number of output bits of the AD converter 33), so that the digital value (binary number) output from the AD converter 33 is shifted to the right, amplifier 38 in combination with the AD converter 33 act as a digital shifter configured to perform shift processing on a signal value of the digital signal converted by the AD converter (i.e. 33) by any one of a plurality of shift amounts, the plurality of shift amounts corresponding to the adjustment value to be set from outside.),
“a digital integrator configured to integrate the signal value of the digital signal subjected to the shift processing by the digital shifter to generate integrated data” (See [0020] as discussed in claim 16 above. Therefore, the FLL unit includes a digital integrator (i.e. 34) configured to integrate the signal value of the digital signal subjected to the shift processing (See [0043]) by the digital shifter (i.e. amplifier 38 in combination with the AD converter 33) to generate integrated data.),
“a digital-to-analog (DA) converter configured to convert the integrated data generated by the digital integrator into a voltage signal” (See [0030] and [0034] as discussed in claim 16 above. Therefore, the FLL unit includes a digital-to-analog (DA) converter (i.e. 35) configured to convert the integrated data generated by the digital integrator into a voltage signal.),
“a voltage-to-current converter configured to convert the voltage signal converted by the DA converter into a current signal” (See [0035] as discussed in claim 16 above. Therefore, the FLL unit includes a voltage-to-current converter (i.e. 36) configured to convert the voltage signal converted by the DA converter (i.e. 35) into a current signal.), and
“a coil configured to feed back the current signal converted by the voltage-to-current converter to the SQUID sensor as a magnetic field” (See [0037] as discussed in claim 16 above. Therefore, the FLL unit includes a coil (i.e. feedback coil 37) configured to feed back the current signal converted by the voltage-to-current converter to the SQUID sensor as a magnetic field.), and
“wherein the digital shifter is configured to function as the adjustment device” (See [0043] above. Therefore, the digital shifter (i.e. amplifier 38 in combination with the AD converter 33) is configured to function as the adjustment device.).
Regarding claim 12, Yasui in view of Yasui-2 discloses all features of the claimed invention as discussed with respect to claim 2 above, and Yasui further teaches "wherein the FLL unit includes: a first amplifier configured to amplify a voltage signal output from the SQUID sensor” (See digital FLL circuit 30 as discussed in [0020], FIG. 1 and [0028] as discussed in claim 16 above. Therefore, the FLL unit includes a first amplifier (i.e. amplifier 31) configured to amplify a voltage signal output from the SQUID sensor.),
“an analog-to-digital (AD) converter configured to convert the voltage signal amplified by the first amplifier into a digital signal” (See [0029] as discussed in claim 16 above. As shown in FIG. 1, the amplifiers 31 and 38 both output to the AD converter 33 via the signal switcher 32. Therefore, the FLL unit includes an analog-to-digital (AD) converter (i.e. 33) configured to convert the voltage signal amplified by the first amplifier (i.e. 31) into a digital signal.),
“a digital integrator configured to integrate a signal value of the digital signal converted by the AD converter to generate integrated data” (“See [0020] as discussed in claim 16 above. Therefore, the FLL unit includes a digital integrator (i.e. 34) configured to integrate a signal value of the digital signal converted by the AD converter to generate integrated data.),
“a digital-to-analog (DA) converter configured to convert the integrated data generated by the digital integrator into a voltage signal” (See [0030] and [0034] as discussed in claim 16 above. Therefore, the FLL unit includes a digital-to-analog (DA) converter (i.e. 35) configured to convert the integrated data generated by the digital integrator into a voltage signal.),
“an amplitude adjuster configured to convert a full scale of an output of the DA converter to any one of a plurality of full scales to adjust to any one of a plurality of amplitudes, the plurality of full scales corresponding to the adjustment value to be set from outside” (See [0039] as discussed in claim 16 above. Therefore, since the gain of the amplifier 38 is determined to be 2 to the power (Dan-ADn) or greater, such as setting it to a scale-factor of 128, the amplifier 38 represents an amplitude adjuster configured to convert a full scale of an output of the DA converter to any one of a plurality of full scales to adjust to any one of a plurality of amplitudes, the plurality of full scales corresponding to the adjustment value to be set from outside.);
“a voltage-to-current converter configured to convert the voltage signal whose voltage magnitude is changed by converting the full scale by the amplitude adjuster into a current signal” (See [0035] as discussed in claim 16 above. Therefore, the FLL unit includes a voltage-to-current converter (i.e. 36) configured to convert the voltage signal whose voltage magnitude is changed by converting the full scale by the amplitude adjuster (i.e. amplifier 38) into a current signal.), and
“a coil configured to feed back the current signal converted by the voltage-to-current converter to the SQUID sensor as a magnetic field” (See [0037] as discussed in claim 16 above. Therefore, the FLL unit includes a coil (i.e. feedback coil 37) configured to feed back the current signal converted by the voltage-to-current converter to the SQUID sensor as a magnetic field.), and
“wherein the amplitude adjuster is configured to function as the adjustment device” (See [0039] as discussed above. Therefore the amplitude adjuster (i.e. amplifier 38) is configured to function as the adjustment device.).
Regarding claim 13, Yasui in view of Yasui-2 discloses all features of the claimed invention as discussed with respect to claim 2 above, and Yasui further teaches "wherein the FLL unit includes: a first amplifier configured to amplify a voltage signal output from the SQUID sensor” (See digital FLL circuit 30 as discussed in [0020], FIG. 1 and [0028] as discussed in claim 16 above. Therefore, the FLL unit includes a first amplifier (i.e. amplifier 31) configured to amplify a voltage signal output from the SQUID sensor.,
“a second amplifier configured to amplify the voltage signal amplified by the first amplifier at any one of a plurality of amplification factors, the plurality of amplification factors corresponding to a first adjustment value to be set from outside” (See [0038] as discussed in claim 16 above and [0039] as discussed in claim 1 above. Therefore, the FLL unit includes a second amplifier (i.e. amplifier 38) configured to amplify the voltage signal amplified by the first amplifier (i.e. 31) at any one of a plurality of amplification factors, the plurality of amplification factors corresponding to a first adjustment value to be set from outside.),
“an analog integrator configured to integrate the voltage signal amplified by the second amplifier” (“The signal switcher 32 is controlled, for example, by the CPU 50 to connect the output of the amplifier 31 to the input of the AD converter 33 during a normal measurement mode and to connect the output of the amplifier 38 to the input of the AD converter 33 during a correction mode” [0025]; “The AD converter 33 converts an analog signal received through the signal switcher 32 into a digital signal (i.e., a voltage value) and outputs the digital value generated by the conversion to the digital integrator 34” [0029]. As shown in FIG. 1, the signal switcher receives input from both the amplifier 31 and the amplifier 38 (i.e. second amplifier). Since the AD converter receives an analog signal from the signal switcher 32 and the signal switcher 32 receives a voltage signal from the amplifier 31 or the amplifier 32 depending on the mode, the signal switcher represents an analog integrator configured to integrate the voltage signal amplified by the second amplifier (i.e. amplifier 38).),
“a voltage-to-current converter configured to convert the voltage signal integrated by the analog integrator into a current signal” (See [0035] as discussed in claim 16 above. Therefore, the FLL unit includes a voltage-to-current converter (i.e. 36) configured to convert the voltage signal integrated by the analog integrator into a current signal.), and
“a coil configured to feed back the current signal converted by the voltage-to-current converter to the SQUID sensor as a magnetic field” (See [0037] as discussed in claim 16 above. Therefore, the FLL unit includes a coil (i.e. feedback coil 37) configured to feed back the current signal converted by the voltage-to-current converter to the SQUID sensor as a magnetic field.), and
“wherein the second amplifier is configured to function as the adjustment device” (See [0038] and [0039] above. Therefore, the second amplifier (i.e. 38) is configured to function as the adjustment device.).
Regarding claim 14, Yasui in view of Yasui-2 discloses all features of the claimed invention as discussed with respect to claim 13 above, and Yasui further teaches "wherein one or both of the analog integrator and the voltage-to-current converter include an amplification function, wherein the amplification function of the analog integrator is a function of changing an amplification factor of a current signal in accordance with an adjustment value that can be set from outside, wherein the amplification function of the voltage-to-current converter is a function of changing a conversion ratio of a current signal with respect to a voltage signal in accordance with an adjustment value that can be set from outside” (“During the correction mode, the amplifier 38 amplifies the voltage received from the DA converter 35 by an integer multiple, and outputs the amplified voltage to the AD converter 33 through the signal switcher 32. The voltage output by the DA converter 35 is amplified by the amplifier 38 by the integer multiple to facilitate corresponding the original voltage output by the DA converter 35 to the voltage output by the amplifier 38” [0038], “For example, the CPU 50 successively stores the setting value common to all the digital FLL circuits 30 included in the magnetic field measuring apparatus 100 in the respective setting value storage units 34a” [0045], “The DA converter 35 successively outputs the voltage corresponding to the received setting value to the amplifier 38, the amplifier 38 amplifies the voltage corresponding to the setting value, and the AD converter 33 outputs the digital value corresponding to the voltage amplified by the amplifier 38” [0046]. As established in claim 13 above, the signal switcher 32 represents the analog integrator. By definition voltage, is equal to current times resistance (i.e. V = IR), thus, an amplification of voltage is necessitated by an increase in current (i.e. assuming resistance (i.e. corresponding to resistors) in the FLL circuit remains constant. Therefore, since the amplifier 38 amplifies the voltage received from the DA converter 35 by an integer multiple and the signal switcher 32 provides the amplified voltage signal (i.e. caused by increased current) to the AD converter 33, the analog integrator (i.e. signal switcher 32), by virtue of its connection with the amplifier 38 during the correction mode) performs an amplification function which is a function of changing an amplification factor of a current signal in accordance with an adjustment value that can be set from outside (i.e. through the setting stored in the CPU and received by the DA converter, see [0045], [0046])., and
“wherein the adjustment device includes the analog integrator having a first amplification function, the voltage-to-current converter having a second amplification function, or both the analog integrator having the first amplification function and the voltage-to-current converter having the second amplification function” (See [0038]. Therefore, the adjustment device includes the analog integrator (i.e. signal switcher 32) having a first amplification function (i.e. by virtue of its connection with the amplifier 38, see [0038]).
Regarding claim 17, Yasui discloses all features of the claimed invention as discussed with respect to claim 1 above, and Yasui teaches “A biomagnetic field measurement system comprising: […] the biomagnetic field measurement device of claim 1” (See FIG. 1 and [0003], [0017], [0019], [0020], [0023], [0038], and [0039] as discussed in claim 1 above. Therefore, the magnetic field measuring apparatus 100 (see FIG. 1) represents a biomagnetic field measurement system which includes a biomagnetic field measurement device.).
However, Yasui does not teach “an electrical stimulation input device configured to generate an induced magnetic field in a living body by applying electrical stimulation to the living body”.
Yasui-2 teaches “an electrical stimulation input device configured to generate an induced magnetic field in a living body by applying electrical stimulation to the living body” (“In recent years, the magnetic field measuring apparatus 100A is applied not only to the magnetocardiograph (MCG) and the magnetoencephalograph (MEG), but also popularly applied to the magnetospinograph (MSG). The magnetospinograph (MSG) inputs an external electrical stimulation, and measures the biomagnetic field induced by the electrical stimulation” [0040]; “Because the large artifact also occurs when measuring the biomagnetic field by the magnetoencephalograph (MEG) in a state where the electrical stimulation is applied to the vagus nerve, the wide dynamic range is required to measure the biomagnetic field” [0041].
Therefore, an electrical stimulation input device is present to provide electrical stimulation (i.e. to perform a magnetospinograph).).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the biomagnetic field measurement system of Yasui such that it includes an electrical stimulation input device as disclosed in Yasui-2 in order to effectively provide an electrical stimulus to a living body to induce a magnetic field for performing an assessment. An electrical stimulation input device (i.e. for magnetospinography) is one of a finite number of devices which can be used to induce a magnetic field with a reasonable expectation of success. Thus, modifying the biomagnetic field measurement device od Yasui such that it includes an electrical stimulation input device as disclosed in Yasui-2 would yield the predictable result of effectively providing an electrical stimulus to a living body to induce a magnetic field for performing an assessment.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kawabata et al. US 7,656,154 B2 “Kawabata” is pertinent to the applicant’s disclosure because it discloses “FIG. 1 is a diagram showing a configuration example of a biomagnetic measurement system of the present invention configured by combining a superconducting quantum interference device (SQUID) magnetometer and an optical pumping magnetometer” [Column 7, Lines 22-26].
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/KAITLYN E SEBASTIAN/Examiner, Art Unit 3797
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