DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 6-13, 15, 16 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by [Hayes et al (Fig. 2); 10,148,228).
Regarding claims 1 and 15, Hayes et al discloses an amplifier circuit comprising an input splitting circuit (236) configured to split a RF input signal (206) into a plurality of RF input signals (202) including a first RF input signal (upper input signal of 226) and a second RF input signal (upper input signal of 232) and a third RF input signal (upper input signal of 234), a plurality of amplifiers (226, 228, 232, 234) including a main amplifier (226) configured to amplify the first RF input signal (upper input signal of 226) to generate a first RF output signal (RF CARRIER AMP_1), a first auxiliary amplifier (232) configured to amplify the second RF input signal (upper input signal of 232) to generate a second RF output signal (RF PEAKING AMP_1), a second auxiliary amplifier (234) configured to amplify the third RF input signal (upper input signal of 234) to generate a third RF output signal (RF PEAKING AMP_2), and a bias circuit (220, 222) configured to receive an envelope signal (210) indicating an envelope of the RF input signals (202) and to control both a first biasing signal (260) of the first auxiliary amplifier (232) and a second biasing signal (262) of the second auxiliary amplifier (234) based on the envelope signal (210).
Regarding claims 2 and 16, wherein the bias circuit (220, 222) controls the first biasing signal (260) and the second biasing signal (262) to set a state of the Doherty power amplifier system.
Regarding claim 6, wherein the main amplifier (226) and the first auxiliary amplifier (232), and the second auxiliary amplifier (234) have a common amplifier topology.
Regarding claim 7, wherein the main amplifier (226) and the first auxiliary amplifier (232), and the second auxiliary amplifier (234) have about equal size.
Regarding claim 8, wherein the main amplifier (226) and the first auxiliary amplifier (232), and the second auxiliary amplifier (234) are powered by a common power supply voltage (VCC).
Regarding claim 9, wherein the common power supply voltage (VCC) is fixed.
Regarding claim 10, wherein the envelope signal (210) can be a differential analog signal.
Regarding claim 11, wherein the envelope signal (210) is outputted from a discrete look-up table (discrete look up table in 208).
Regarding claim 12, Hayes et al further comprising an output combining circuit (lower terminal of the element 244) configured to generate a RF output signal (RF OUT) based on combining the first RF output signal (RF CARRIER AMP_1) and the second RF output signal (RF PEAKING AMP_1), and the third RF output signal (RF PEAKING AMP_2).
Regarding claim 13, wherein the first RF input signal (upper input signal of 226) is phase delayed by about 90 degrees (90o) relative to the second RF input signal (upper input signal of 232).
Regarding claim 20, Hayes et al discloses an amplifier circuit comprising a transceiver (Fig. 2) configured to generate a RF input signal (202) and an envelope signal (210) indicating an envelope of the RF input signals (202), and a front end system (224, 230, 236, 208, 212, 214, 220, 222) including a Doherty power amplifier system (224, 230) configured to amplify the RF input signal (202) and the Doherty power amplifier system (224, 230, 236, 220, 222) including an input splitting circuit (236) configured to split the RF input signals (202) into first RF input signal (upper input signal of 226) and a second RF input signal (upper input signal of 232) and a third RF input signal (upper input signal of 234) and the Doherty power amplifier system (224, 230, 236, 220, 222) further includes a main amplifier (226) configured to amplify the first RF input signal (upper input signal of 226) to generate a first RF output signal (RF CARRIER AMP_1), a first auxiliary amplifier (232) configured to amplify the second RF input signal (upper input signal of 232) to generate a second RF output signal (RF PEAKING AMP_1), a second auxiliary amplifier (234) configured to amplify the third RF input signal (upper input signal of 234) to generate a third RF output signal (RF PEAKING AMP_2), and a bias circuit (220, 222) configured to control both a first biasing signal (260) of the first auxiliary amplifier (232) and a second biasing signal (262) of the second auxiliary amplifier (234) based on the envelope signal (210).
Allowable Subject Matter
Claims 3-5, 14 and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Choe whose telephone number is (703)774-4614. The examiner can normally be reached Mon-Fri 6:00 AM- 6:00 PM EST. Examiner interviews are available via telephone, in person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interview practice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea J Lindgren Baltzell can be reached on (571)272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
/HENRY CHOE/ Primary Examiner, Art Unit 2843
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