DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “the first second conductor layer” must be shown or the features canceled from the claims. Moreover the “the second conductor layer” must be shown or the features canceled from the claims. Furthermore, the “the third second conductor layer” must be shown or the features canceled from the claims. In addition, “the first semiconductor layer” and “the second semiconductor layer” must be shown or the features canceled from the claims.
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-30 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Drawings as filed do not show “the first semiconductor layer”, “the second semiconductor layer”, “the first second conductor layer”, “the second conductor layer”, “the third second conductor layer”.
Claims 1-30 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claims contain a subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Drawings as filed do not show “the first semiconductor layer”, “the second semiconductor layer”, “the first second conductor layer”, “the second conductor layer”, “the third second conductor layer”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 9-10, 14, 19, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hideo, US 2020/0295952 (corresponding to US 10,998,342)
In re Claim 1, Hideo discloses a semiconductor apparatus comprising: a substrate 11 (Fig. 3); a first semiconductor layer 131 that is of a first transistor T1 and disposed above the substrate 11; a first conductor layer 135 disposed above the substrate 11 and overlapping the first semiconductor layer 131; a second semiconductor layer 153 that is of a second transistor T2 and disposed above the substrate 11; and a second conductor layer 151 disposed above the substrate 11 and overlapping the second semiconductor layer 153, wherein a first element (silicon, Si) ([0037]) with a highest concentration in the first semiconductor layer 131 among elements of Groups 12 to 16 included in the first semiconductor layer 131 differs from a second element (Gallium, [0039]) with a highest concentration in the second semiconductor layer 153 among elements of Groups 12 to 16 included in the second semiconductor layer 153, wherein a third element (Titanium, [0040]) with a highest concentration in the first conductor layer 135 among metal elements or metalloid elements included in the first conductor layer 135 is same as a fourth element (Titanium, [0040]) with a highest concentration in the second conductor layer 151 among metal elements or metalloid elements included in the second conductor layer 151, wherein the first conductor layer 135 is in contact with the first semiconductor layer 131, wherein the second conductor layer 151 is insulated from the second semiconductor layer 153, wherein the second conductor layer 151 is disposed between the second semiconductor layer 153 and the substrate 11, and wherein the second conductor layer 151 is contiguous to the first conductor layer 135. (Figs. 1- 4; [0023 – 0063]).
In re Claim 9, Hideo discloses the semiconductor apparatus according to Claim 1, wherein a gate electrode 151 of the second transistor T2 is disposed between the substrate 11 and the second semiconductor layer 153 (Fig. 3).
In re Claim 14, Hideo discloses the semiconductor apparatus according to Claim 1, wherein the second semiconductor layer 153 is thinner than the gate electrode 151 of the second transistor T2 (Fig. 3).
In re Claim 21, Hideo discloses the semiconductor apparatus according to Claim 1, further comprising an organic electroluminescence (EL) element ([0026-0027]; Figs. 1 and 2) disposed above the substrate 11, wherein the first element (silicon, [0037]) is an element of Group 14, and wherein the second element (Gallium, [0039]) is an element of Group 12, 13, 15, or 16 .
In re Claim 3, Hideo discloses a semiconductor apparatus comprising: a substrate 11 (Fig. 3); a first semiconductor layer 153 that is of an N-type first transistor T2 ([0041]) and disposed above the substrate 11; a first conductor layer 135 disposed above the substrate 11 and overlapping the first semiconductor layer 131; a second semiconductor layer 153 that is of a P-type second transistor T1 ([0041]) and disposed above the substrate 11; and a second conductor layer 151 disposed above the substrate 11 and overlapping the second semiconductor layer 153, wherein a first element (silicon, Si [0037]) with a highest concentration in the first semiconductor layer 131 among elements of Groups 12 to 16 included in the first semiconductor layer 131 differs from a second element with a highest concentration in the second semiconductor layer 153 among elements of Groups 12 to 16 included in the second semiconductor layer 153, wherein a third element (Titanium, [0040]) with a highest concentration in the first conductor layer 135 among metal elements or metalloid elements included in the first conductor layer 135 is same as a fourth element (Titanium, [0040]) with a highest concentration in the second conductor layer 151 among metal elements or metalloid elements included in the second conductor layer 151, wherein the first conductor layer 135 is in contact with the first semiconductor layer 131, and wherein the second conductor layer 151 is insulated from the second semiconductor layer 153 (Figs. 1- 4; [0023 – 0063]).
In re Claim 10, Hideo discloses the semiconductor apparatus according to Claim 3, wherein the gate electrode 151 of the second transistor T2 includes the second conductor layer 151 (Fig. 3).
In re Claim 19, Hideo discloses the semiconductor apparatus according to Claim 3, wherein the first transistor T1 and the second transistor T2 are electrically connected to each other (Fig. 2; [0028-0029]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 22 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Hideo as applied to claim 1 above.
In re Claim 22, Hideo discloses all limitations of Claim 22 including that one of the first semiconductor layer 131 and the second semiconductor layer is a polycrystalline layer ([0037]), and the other of the first semiconductor layer and the second semiconductor layer 153 is an oxide semiconductor layer ([0039]), and wherein a distance between the polycrystalline layer 131 and the substrate 11 is less than a distance between the oxide semiconductor layer 153 and the substrate 11 (Fig. 3), except for that a diagonal length of the substrate 11 is more than or equal to 5 centimeters (cm). The only difference between the Applicant’s Claim 22 and Hideo’s reference is in the specified size of the substrate. It is known in the art that the diagonal length of the substrate is a result effective variable – because its volume depends on it. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to use the diagonal length of the substrate 11 is more than or equal to 5 centimeters (cm), since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (MPEP2144.05.I).
In re Claim 25, Regarding claim 25 the phrase “Equipment comprising: the semiconductor apparatus according to Claim 1; and a control apparatus connected to the semiconductor apparatus” merely represents an intended use or a manner in which a claimed apparatus is intended to be employed and does not differentiate the claimed apparatus from a prior art apparatus of Hideo. See MPEP 2114. II. MANNER OF OPERATING THE DEVICE DOES NOT DIFFERENTIATE APPARATUS CLAIM FROM THE PRIOR ART. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987)
Claims 17 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Hideo as applied to claim 3 above.
In re Claim 17, Hideo discloses all limitations if Claim 17 including a gate electrode 133 of the first transistor T1 (Fig. 3) except for that the gate electrode of the first transistor includes a same element as the third element (i.e. Titanium). The difference between the Applicant’s Claim 17 and Hideo’s reference is in the specified material used as the gate electrode 133 of the first transistor T1. Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, it would have been an obvious matter of design choice of one of ordinary skill in the semiconductor art to use Titanium as the gate electrode of the first transistor since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416 (See MPEP2144.07).
In re Claim 27, Hideo discloses Equipment comprising: an imaging apparatus; and a display apparatus, wherein the display apparatus includes the semiconductor apparatus according to Claim 3, wherein the display apparatus is able to switch a rate at which display is performed, between a first rate and a second rate higher than the first rate, and wherein the imaging apparatus performs image capturing at a third rate between the first rate and the second rate.
Regarding claim 27, the phrase “Equipment comprising: an imaging apparatus; and a display apparatus, wherein the display apparatus includes the semiconductor apparatus according to Claim 3, wherein the display apparatus is able to switch a rate at which display is performed, between a first rate and a second rate higher than the first rate, and wherein the imaging apparatus performs image capturing at a third rate between the first rate and the second rate.” merely represents an intended use or a manner in which a claimed apparatus is intended to be employed and does not differentiate the claimed apparatus from a prior art apparatus of Hideo. See MPEP 2114. II. MANNER OF OPERATING THE DEVICE DOES NOT DIFFERENTIATE APPARATUS CLAIM FROM THE PRIOR ART. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987)
Claims 2, 8, 12, 20, 26 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi et al., US 2018/0040640 (corresponding to US 10,373,983), in view of Hideo, US 2020/0295952 (corresponding to US 10,998,341).
In re Claim 2, Takahashi discloses a semiconductor apparatus comprising: a substrate 31 (Fig. 2); a first semiconductor layer 35 that is of a first transistor M2 and disposed above the substrate 31; a first conductor layer (43A, 43B) disposed above the substrate 31 and overlapping the first semiconductor layer 35; a second semiconductor layer 45 that is of a second transistor M1 and disposed above the substrate 31; a second conductor layer 43C disposed above the substrate 31 and overlapping the second semiconductor layer 45; and a third conductor layer 50 disposed above the substrate 31 and overlapping the second conductor layer 45, , wherein the first conductor layer (43A, 43B) is in contact with the first semiconductor layer 35, wherein the second conductor layer 43C is insulated from the second semiconductor layer 45, wherein the third conductor layer 50 is not in contact with the second semiconductor layer 45, and wherein the third conductor layer 50 is insulated from the second conductor layer 43C (Figs. 1, 2, and 10; [0039 – 0165]).
Takahashi does not specify that a first element with a highest concentration in the first semiconductor layer 35 among elements of Groups 12 to 16 included in the first semiconductor layer 45 differs from a second element with a highest concentration in the second semiconductor layer 45 among elements of Groups 12 to 16 included in the second semiconductor layer 45, wherein a third element with a highest concentration in the first conductor layer among metal elements or metalloid elements included in the first conductor layer is same as a fourth element with a highest concentration in the second conductor layer among metal elements or metalloid elements included in the second conductor layer.
Hideo discloses a semiconductor apparatus comprising: a substrate 11 (Fig. 3); a first semiconductor layer 131 that is of a first transistor T1 and disposed above the substrate 11; a first conductor layer 135 disposed above the substrate 11 and overlapping the first semiconductor layer 131; a second semiconductor layer 153 that is of a second transistor T2 and disposed above the substrate 11; and a second conductor layer 151 disposed above the substrate 11 and overlapping the second semiconductor layer 153, wherein a first element (Silicon, [0037]) with a highest concentration in the first semiconductor layer 131 among elements of Groups 12 to 16 included in the first semiconductor layer 131 differs from a second element (Gallium, [0039]) with a highest concentration in the second semiconductor layer 153 among elements of Groups 12 to 16 included in the second semiconductor layer 153, wherein a third element (Titanium, [0040]) with a highest concentration in the first conductor layer 135 among metal elements or metalloid elements included in the first conductor layer 135 is same as a fourth element (Titanium, [0040]) with a highest concentration in the second conductor layer 151 among metal elements or metalloid elements included in the second conductor layer 151, wherein the first conductor layer 135 is in contact with the first semiconductor layer 131, wherein the second conductor layer 151 is insulated from the second semiconductor layer 153, and wherein the first conductor layer 135 is disposed between the first semiconductor layer 131 and the substrate 11. It would have been obvious to one of ordinary skill in the art at the time of the invention to combine teachings of Takahashi and Hideo, and to use the specified composition of the first semiconductor layer and first conductive layer to significantly improve overall displaying performance as taught by Hideo ([0004]).
In re Claim 8, Takahashi taken with Hideo discloses the semiconductor apparatus according to Claim 2, wherein the second semiconductor layer 153 is disposed between the substrate 11 and a gate electrode 151 of the second transistor T2 (Hideo: Fig. 3).
In re Claim 12, Takahashi taken with Hideo discloses the semiconductor apparatus according to Claim 2, wherein a source electrode 43A of the first transistor M2 includes the first conductor layer (43A, 43B), and wherein a source electrode 46A of the second transistor M1 and the gate electrode 43C of the second transistor M1 are disposed on one of a side facing the substrate 31 with respect to the second semiconductor layer 45 and an opposite side of the side facing the substrate 31 (Takahashi: Fig. 2).
In re Claim 20, Takahashi taken with Hideo discloses the semiconductor apparatus according to Claim 2, further comprising a capacitor C1 ([0079 – 0083], Figs. 1 - 4) in which a dielectric layer 49 is disposed between the second conductor layer (46A, 46B) and the third conductor layer 50.
In re Claim 26, Takahashi taken with Hideo discloses Equipment comprising: the semiconductor apparatus according to Claim 2; and an optical member ((50, 52, 53) = the light-emitting element EL (Takahashi: Fig. 2, [0065]) disposed above the semiconductor apparatus, wherein the second semiconductor layer 45 is disposed between the substrate 31 and the optical member (50, 52, 53).
Claims 4, 7, 11, 13, 16 , 18, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi et al., US 2018/0040640 (corresponding to US 10,373,983), in view of Hideo, US 2020/0295952 (corresponding to US 10,998,341).,and in view of Yamazaki et al., US 2015/0364477 (corresponding to US 9,978,757).
In re Claim 4, Takahashi discloses a semiconductor apparatus comprising: a substrate 31 (Fig. 2); a first semiconductor layer 35 that is of a first transistor M2 and disposed above the substrate 31; a first conductor layer (43A, 43B) disposed above the substrate 31 and overlapping the first semiconductor layer 35; a second semiconductor layer 45 that is of a second transistor M1 and disposed above the substrate 31; and a second conductor layer 50 disposed above the substrate 31 and overlapping the second semiconductor layer 45 (Figs. 1, 2, and 10; [0039 – 0165]).
Takahashi does not specify that a first element with a highest concentration in the first semiconductor layer 35 among elements of Groups 12 to 16 included in the first semiconductor layer 35 differs from a second element with a highest concentration in the second semiconductor layer 45 among elements of Groups 12 to 16 included in the second semiconductor layer 45, wherein a third element with a highest concentration in the first conductor layer (43A, 43B) among metal elements or metalloid elements included in the first conductor layer (43A, 43B) is same as a fourth element with a highest concentration in the second conductor layer 45 among metal elements or metalloid elements included in the second conductor layer 43C, wherein the first conductor layer (43A, 43B) is in contact with the first semiconductor layer 35, wherein the second conductor layer 43C is insulated from the second semiconductor layer 45, and wherein the first conductor layer (43A, 43B) is disposed between the first semiconductor layer 35 and the substrate 31.
Hideo teaches a semiconductor apparatus comprising: a substrate 11 (Fig. 3); a first semiconductor layer 131 that is of a first transistor T1 and disposed above the substrate 11; a first conductor layer 135 disposed above the substrate 11 and overlapping the first semiconductor layer 131; a second semiconductor layer 153 that is of a second transistor T2 and disposed above the substrate 11; and a second conductor layer 151 disposed above the substrate 11 and overlapping the second semiconductor layer 153, wherein a first element (silicon, Si) ([0037]) with a highest concentration in the first semiconductor layer 131 among elements of Groups 12 to 16 included in the first semiconductor layer 131 differs from a second element (Gallium, [0039]) with a highest concentration in the second semiconductor layer 153 among elements of Groups 12 to 16 included in the second semiconductor layer 153, wherein a third element (Titanium, [0040]) with a highest concentration in the first conductor layer 135 among metal elements or metalloid elements included in the first conductor layer 135 is same as a fourth element Titanium, [0040]) with a highest concentration in the second conductor layer 155 among metal elements or metalloid elements included in the second conductor layer 155, wherein the first conductor layer 135 is in contact with the first semiconductor layer 131, wherein the second conductor layer 151 is insulated from the second semiconductor layer 153 (Figs. 1- 4; [0023 – 0063]).
To reject a claim based on this rationale set forth in MPEP 2143 (B), Office personnel must resolve the Graham factual inquiries. Then, Office personnel must articulate the following:
(1) a finding that the prior art contained a device (method, product, etc.) which differed from the claimed device by the substitution of some components (step, element, etc.) with other components;
(2) a finding that the substituted components and their functions were known in the art;
(3) a finding that one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have been predictable; and
(4) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness.
In the instant case, examiner articulates the following:
(1) Takahashi’s reference contains a semiconductor apparatus which differed from the claimed device by the substitution of some components (semiconductor and conductive layers) with Hideo’s layers;
(2) Hideo’s semiconductor apparatus with layers, wherein a first element with a highest concentration in the first semiconductor layer among elements of Groups 12 to 16 included in the first semiconductor layer differs from a second element with a highest concentration in the second semiconductor layer among elements of Groups 12 to 16 included in the second semiconductor layer, wherein a third element with a highest concentration in the first conductor layer among metal elements or metalloid elements included in the first conductor layer is same as a fourth element with a highest concentration in the second conductor layer among metal elements or metalloid elements included in the second conductor layer, wherein the first conductor layer is in contact with the first semiconductor layer and its functions were known in the art;
(3) Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, one of ordinary skill in the semiconductor art could have substituted one known element (semiconductor and conductive layers) for another (semiconductor and conductive layers of specified compositions), and the results of the substitution would have been predictable, because Hideo’s device successfully functions;
(4) In view of the facts of the case under consideration, there appear to be no additional findings (re, e.g. long-felt need, unexpected results, commercial success, etc.) needed, based on the Graham factual inquiries.
However, Takahashi taken with Hideo does not specify that the first conductor layer 135 is disposed between the first semiconductor layer 131 and the substrate 11.
The difference between the Applicant’s Claim 6 and Takahashi – Hideo’ references is in the specified position of the first conductor layer 135 between the first semiconductor layer 131 and the substrate 11.
Yamazaki teaches a semiconductor apparatus wherein a first conductive layer (142a, 142b) is between a first semiconductor layer 140 and the substrate 100 (shown in a bottom portion of Fig. 1A) (Figs. 1 and 2; [0045 – 0068]).
It would have been obvious to one of ordinary skill in the art at the time of the invention to combine teachings of Takahashi, Hideo and Yamazaki, and to use the specified position of the first conductive layer to drastically improve reliability as taught by Yamazaki ([0023]).
In re Claim 7, Takahashi taken with Hideo Yamazaki discloses the semiconductor apparatus according to Claim 4, wherein the first conductor layer (43A, 43B) and the second conductor layer (46A, 46B) are of a same layer (Takahashi: Fig. 2).
In re Claim 11, Takahashi taken with Hideo and Yamazaki discloses the semiconductor apparatus according to Claim 4, wherein the second semiconductor layer 45 is disposed between the gate electrode 43C of the second transistor M1 and the second conductor layer 50 (Takahashi: Fig. 2).
In re Claim 13, Takahashi taken with Hideo and Yamazaki discloses the semiconductor apparatus according to Claim 4, wherein a source electrode 43A of the first transistor M2 includes the first conductor layer (43A, 43B), and wherein the second semiconductor layer 45 is disposed between the gate electrode 43C of the second transistor M1 and a source electrode 46B of the second transistor M1 (Takahashi: Fig. 2).
In re Claim 16, Takahashi taken with Hideo and Yamazaki discloses all limitations of Claim 16 except for that a drain electrode 46A of the second transistor M1 includes a same element as the fourth element (titanium, Hideo: [0040]).
In re Claim 18, Takahashi taken with Hideo and Yamazaki discloses the semiconductor apparatus according to Claim 4, wherein for a distance between the first semiconductor layer 131 (Hideo: Fig. 3) and the substrate 11 differs from a distance between the second semiconductor layer 153 and the substrate 11, wherein a distance between the first semiconductor layer 131 and a first gate electrode 133 of the first transistor T1 differs from a distance between the second semiconductor layer 153 and a second gate electrode 151of the second transistor T2, wherein a distance between the substrate 11 and the first gate electrode 133 differs from a distance between the substrate 11 and the second gate electrode 151, and wherein the second conductor layer 153 is noncontiguous to the first conductor layer 131.
In re Claim 28, Takahashi taken with Hideo and Yamazaki discloses the equipment comprising: an imaging apparatus; and a display apparatus, wherein the display apparatus includes the semiconductor apparatus according to Claim 4, wherein the display apparatus is inherently able to switch a rate at which display is performed, between a first rate and a second rate higher than the first rate, and wherein the imaging apparatus performs image capturing at a third rate between the first rate and the second rate, wherein the first rate is less than or equal to 10 frames per second (fps) and the second rate is more than or equal to 100 fps.
It is inherently because according to MPEP2112.01 [R-3] Composition, Product, and Apparatus Claims I. PRODUCT AND APPARATUS CLAIMS — WHEN THE STRUCTURE RECITED IN THE REFERENCE IS SUBSTANTIALLY IDENTICAL TO THAT OF THE CLAIMS, CLAIMED PROPERTIES OR FUNCTIONS ARE PRESUMED TO BE INHERENT. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). In the instant case, Takahashi – Hideo’s structure being SUBSTANTIALLY IDENTICAL TO THAT OF THE CLAIMS inherently possesses property to switch a rate at which display is performed, between a first rate and a second rate higher than the first rate, and wherein the imaging apparatus performs image capturing at a third rate between the first rate and the second rate, wherein the first rate is less than or equal to 10 frames per second (fps) and the second rate is more than or equal to 100 fps.
Claims 5, 24, 29 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi et al., US 2018/0040640 (corresponding to US 10,373,983), in view of Hideo, US 2020/0295952 (corresponding to US 10,998,341).
In re Claim 5, Takahashi discloses a semiconductor apparatus comprising: a substrate 31 (Fig. 2); a first semiconductor layer 35 that is of a first transistor M2 and disposed above the substrate 31; a first conductor layer (43A, 43B) disposed above the substrate 31 and overlapping the first semiconductor layer 35; a second semiconductor layer 45 that is of a second transistor M1 and disposed above the substrate 31; and a second conductor layer 50 disposed above the substrate 31 and overlapping the second semiconductor layer 45, wherein the first conductor layer (43A, 43B) is in contact with the first semiconductor layer 35, wherein the second conductor layer 50 is insulated from the second semiconductor layer 45, and wherein the second semiconductor layer 45 is disposed between the second conductor layer 50 and the substrate 31, and wherein the second transistor M1 is a switch transistor (Figs. 1-2, 7-10; [0010 – 0174]).
Takahashi does not disclose that a first element with a highest concentration in the first semiconductor layer among elements of Groups 12 to 16 included in the first semiconductor layer differs from a second element with a highest concentration in the second semiconductor layer among elements of Groups 12 to 16 included in the second semiconductor layer, wherein a third element with a highest concentration in the first conductor layer among metal elements or metalloid elements included in the first conductor layer is same as a fourth element with a highest concentration in the second conductor layer among metal elements or metalloid elements included in the second conductor layer,
Hideo teaches a semiconductor apparatus comprising: a substrate 11 (Fig. 3); a first semiconductor layer 131 that is of a first transistor T1 and disposed above the substrate 11; a first conductor layer 135 disposed above the substrate 11 and overlapping the first semiconductor layer 131; a second semiconductor layer 153 that is of a second transistor T2 and disposed above the substrate 11; and a second conductor layer 151 disposed above the substrate 11 and overlapping the second semiconductor layer 153, wherein a first element (silicon, Si) ([0037]) with a highest concentration in the first semiconductor layer 131 among elements of Groups 12 to 16 included in the first semiconductor layer 131 differs from a second element (Gallium, [0039]) with a highest concentration in the second semiconductor layer 153 among elements of Groups 12 to 16 included in the second semiconductor layer 153, wherein a third element (Titanium, [0040]) with a highest concentration in the first conductor layer 135 among metal elements or metalloid elements included in the first conductor layer 135 is same as a fourth element Titanium, [0040]) with a highest concentration in the second conductor layer 155 among metal elements or metalloid elements included in the second conductor layer 155, wherein the first conductor layer 135 is in contact with the first semiconductor layer 131, wherein the second conductor layer 151 is insulated from the second semiconductor layer 153 (Figs. 1- 4; [0023 – 0063]).
To reject a claim based on this rationale set forth in MPEP 2143 (B), Office personnel must resolve the Graham factual inquiries. Then, Office personnel must articulate the following:
(1) a finding that the prior art contained a device (method, product, etc.) which differed from the claimed device by the substitution of some components (step, element, etc.) with other components;
(2) a finding that the substituted components and their functions were known in the art;
(3) a finding that one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have been predictable; and
(4) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness.
In the instant case, examiner articulates the following:
(1) Takahashi’s reference contains a semiconductor apparatus which differed from the claimed device by the substitution of some components (semiconductor and conductive layers) with Hideo’s layers;
(2) Hideo’s semiconductor apparatus with layers, wherein a first element with a highest concentration in the first semiconductor layer among elements of Groups 12 to 16 included in the first semiconductor layer differs from a second element with a highest concentration in the second semiconductor layer among elements of Groups 12 to 16 included in the second semiconductor layer, wherein a third element with a highest concentration in the first conductor layer among metal elements or metalloid elements included in the first conductor layer is same as a fourth element with a highest concentration in the second conductor layer among metal elements or metalloid elements included in the second conductor layer, wherein the first conductor layer is in contact with the first semiconductor layer and its functions were known in the art;
(3) Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, one of ordinary skill in the semiconductor art could have substituted one known element (semiconductor and conductive layers) for another (semiconductor and conductive layers of specified compositions), and the results of the substitution would have been predictable, because Hideo’s device successfully functions;
(4) In view of the facts of the case under consideration, there appear to be no additional findings (re, e.g. long-felt need, unexpected results, commercial success, etc.) needed, based on the Graham factual inquiries.
In re Claim 24, Takahashi taken with Hideo discloses the semiconductor apparatus according to Claim 5, wherein the third element (Titanium) differs from the second element (Gallium), and the fourth element (Titanium) differs from the first element (Silicon).
In re Claim 28, Takahashi taken with Hideo discloses Equipment comprising: an imaging apparatus; and a display apparatus, wherein the display apparatus includes the semiconductor apparatus according to Claim 5, wherein the display apparatus is inherently able to switch a rate at which display is performed, between a first rate and a second rate higher than the first rate, and wherein the imaging apparatus performs image capturing at a third rate between the first rate and the second rate wherein the first rate is less than or equal to 5 hertz (Hz) and the third rate is from 20 to 80 fps.
It is inherently because according to MPEP2112.01 [R-3] Composition, Product, and Apparatus Claims I. PRODUCT AND APPARATUS CLAIMS — WHEN THE STRUCTURE RECITED IN THE REFERENCE IS SUBSTANTIALLY IDENTICAL TO THAT OF THE CLAIMS, CLAIMED PROPERTIES OR FUNCTIONS ARE PRESUMED TO BE INHERENT. Where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). In the instant case, Takahashi – Hideo’s structure being SUBSTANTIALLY IDENTICAL TO THAT OF THE CLAIMS inherently possesses property to switch a rate at which display is performed, between a first rate and a second rate higher than the first rate, and wherein the imaging apparatus performs image capturing at a third rate between the first rate and the second rate wherein the first rate is less than or equal to 5 hertz (Hz) and the third rate is from 20 to 80 fps.
Claims 6, 15, 23, 30 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi et al., US 2018/0040640 (corresponding to US 10,373,983), in view of Hideo, US 2020/0295952 (corresponding to US 10,998,341).
In re Claim 6, Takahashi discloses a semiconductor apparatus comprising: a substrate 31 (Fig. 2); a first semiconductor layer 45 that is of a first transistor M1 and disposed above the substrate 31; a first conductor layer 43C disposed above the substrate 31 and overlapping the first semiconductor layer 45; a second semiconductor layer 35 that is of a second transistor M2 and disposed above the substrate 31; and a second conductor layer 50 disposed above the substrate 31 and overlapping the second semiconductor layer 45, wherein the first conductor layer (43A, 43B) is in contact with the first semiconductor layer 35, wherein the second conductor layer 50 is insulated from the second semiconductor layer 45, and wherein the first semiconductor layer 45 ([0072]) is an oxide semiconductor layer (Figs. 1-2, 7-10; [0010 – 0174]).
Takahashi does not disclose that a first element (Silicon) with a highest concentration in the first semiconductor layer 35 among elements of Groups 12 to 16 included in the first semiconductor layer 35 differs from a second element with a highest concentration in the second semiconductor layer among elements of Groups 12 to 16 included in the second semiconductor layer, wherein a third element with a highest concentration in the first conductor layer among metal elements or metalloid elements included in the first conductor layer is same as a fourth element with a highest concentration in the second conductor layer among metal elements or metalloid elements included in the second conductor layer,
Hideo teaches a semiconductor apparatus comprising: a substrate 11 (Fig. 3); a first semiconductor layer 131 that is of a first transistor T1 and disposed above the substrate 11; a first conductor layer 135 disposed above the substrate 11 and overlapping the first semiconductor layer 131; a second semiconductor layer 153 that is of a second transistor T2 and disposed above the substrate 11; and a second conductor layer 151 disposed above the substrate 11 and overlapping the second semiconductor layer 153, wherein a first element (silicon, Si) ([0037]) with a highest concentration in the first semiconductor layer 131 among elements of Groups 12 to 16 included in the first semiconductor layer 131 differs from a second element (Gallium, [0039]) with a highest concentration in the second semiconductor layer 153 among elements of Groups 12 to 16 included in the second semiconductor layer 153, wherein a third element (Titanium, [0040]) with a highest concentration in the first conductor layer 135 among metal elements or metalloid elements included in the first conductor layer 135 is same as a fourth element Titanium, [0040]) with a highest concentration in the second conductor layer 155 among metal elements or metalloid elements included in the second conductor layer 155, wherein the first conductor layer 135 is in contact with the first semiconductor layer 131, wherein the second conductor layer 151 is insulated from the second semiconductor layer 153 (Figs. 1- 4; [0023 – 0063]).
To reject a claim based on this rationale set forth in MPEP 2143 (B), Office personnel must resolve the Graham factual inquiries. Then, Office personnel must articulate the following:
(1) a finding that the prior art contained a device (method, product, etc.) which differed from the claimed device by the substitution of some components (step, element, etc.) with other components;
(2) a finding that the substituted components and their functions were known in the art;
(3) a finding that one of ordinary skill in the art could have substituted one known element for another, and the results of the substitution would have been predictable; and
(4) whatever additional findings based on the Graham factual inquiries may be necessary, in view of the facts of the case under consideration, to explain a conclusion of obviousness.
In the instant case, examiner articulates the following:
(1) Takahashi’s reference contains a semiconductor apparatus which differed from the claimed device by the substitution of some components (semiconductor and conductive layers) with Hideo’s layers;
(2) Hideo’s semiconductor apparatus with layers, wherein a first element with a highest concentration in the first semiconductor layer among elements of Groups 12 to 16 included in the first semiconductor layer differs from a second element with a highest concentration in the second semiconductor layer among elements of Groups 12 to 16 included in the second semiconductor layer, wherein a third element with a highest concentration in the first conductor layer among metal elements or metalloid elements included in the first conductor layer is same as a fourth element with a highest concentration in the second conductor layer among metal elements or metalloid elements included in the second conductor layer, wherein the first conductor layer is in contact with the first semiconductor layer and its functions were known in the art;
(3) Due to high level of knowledge and skills of personal capable to operate very sophisticated and expensive equipment in semiconductor technology, one of ordinary skill in the semiconductor art could have substituted one known element (semiconductor and conductive layers) for another (semiconductor and conductive layers of specified compositions), and the results of the substitution would have been predictable, because Hideo’s device successfully functions;
(4) In view of the facts of the case under consideration, there appear to be no additional findings (re, e.g. long-felt need, unexpected results, commercial success, etc.) needed, based on the Graham factual inquiries.
In re Claim 15, Takahashi taken with Hideo discloses the semiconductor apparatus according to Claim 6, wherein the third element and the fourth element are copper (Cu) or titanium (Ti) (Hideo: [0040]).
In re Claim 23, Takahashi taken with Hideo discloses the semiconductor apparatus according to Claim 6, wherein the oxide semiconductor layer 45 includes tin (Sn) (Takashi: [Fig. 2; [0071]).
In re Claim 30, the phrase “the equipment comprising at least any of: a semiconductor device manufactured in 1 to 4 nanometers (nm) process; a communication apparatus configured to perform communication using terahertz waves; and a solid-state battery” merely represents an intended use or a manner in which a claimed apparatus is intended to be employed and does not differentiate the claimed apparatus from a prior art apparatus of Takahashi - Hideo. See MPEP 2114. II. MANNER OF OPERATING THE DEVICE DOES NOT DIFFERENTIATE APPARATUS CLAIM FROM THE PRIOR ART. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987)
Conclusion
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/NIKOLAY K YUSHIN/Primary Examiner, Art Unit 2893