Prosecution Insights
Last updated: October 26, 2026
Application No. 18/462,049

INTEGRATED CIRCUIT DEVICES INCLUDING VIA CAPACITORS

Final Rejection §103
Filed
Sep 06, 2023
Priority
Sep 08, 2022 — RE 10-2022-0114461 +1 more
Examiner
CULLEN, PATRICK LAWRENCE
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
2 (Final)
86%
Grant Probability
Favorable
3-4
OA Rounds
4m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
18 granted / 21 resolved
+17.7% vs TC avg
Strong +25% interview lift
Without
With
+25.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
34 currently pending
Career history
82
Total Applications
across all art units

Statute-Specific Performance

§103
73.4%
+33.4% vs TC avg
§102
10.7%
-29.3% vs TC avg
§112
15.9%
-24.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 21 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 Claim(s) 1-2 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Park1 (PGPub No. 20220254872) in further view of Mao (PGPub No. 20080076229). Regarding claim 1, Park1 teaches an integrated circuit device comprising: a dielectric layer (Fig. 2F-2J; 202); a first power delivery network layer on a first surface of the dielectric layer (Id.; 242-1); and a via capacitor between the first surface and the second surface of the dielectric layer (Id.; 234-1 (C1)), wherein the via capacitor includes a first via electrode structure and a second via electrode structure that are physically spaced apart from each other in one of a first horizontal direction and a second horizontal direction that intersects with the first horizontal direction (Id.; 232-1/E1C1, 232-2/E2C1), and a first end portion of the first via electrode structure and the second via electrode structure and a second end portion of the first via electrode structure and the second via electrode structure that is opposite to the first end portion in the vertical direction are electrically connected to the first power delivery network layer and the second power delivery network layer, respectively (Id. points to a decoupling capacitor structure 234-1 (C1) that is electrically connected to decoupling capacitor interconnects 242-1 (first power delivery network layer) and 242-2 (second power delivery network layer). It is considered obvious that this configuration creates a functional circuit that electrically connects all portions of the decoupling capacitor structure 234-1 (C1) to both interconnects 242-1 and 242-2 (first and second power delivery network layers, respectively), including the capacitor electrodes 232-1/E1C1 (first via electrode structure) and 232-2/E2C1 (second via electrode structure), and by extension their corresponding end portions.). Park1 fails to teach a second power delivery network layer on a second surface of the dielectric layer, wherein the second surface of the dielectric layer is opposite to the first surface of the dielectric layer in a vertical direction. Mao teaches a second power delivery network layer on a second surface of the dielectric layer, wherein the second surface of the dielectric layer is opposite to the first surface of the dielectric layer in a vertical direction (Fig. 3; GND). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Park1 and Mao, such that the second power delivery network layer is formed on a second surface opposite to the first surface in the vertical direction in order to create a decoupling capacitor unit that satisfies the metal covering-ratio rules, makes good use of existing space, allows for said unit to be made as largely as possible, and/or betters the obtained effects of obviating power supply noise. Regarding claim 2, Park1 teaches wherein the first via electrode structure (Figs. 2F-2J; 232-1/E1C1) includes a first via electrode between the first surface and the second surface of the dielectric layer (Id.; 208) and a first via insulating layer on opposing sidewalls of the first via electrode (Id.; 206), and wherein the second via electrode structure (Figs. 2F-2J; 232-2/E2C1) includes a second via electrode between the first surface and the second surface of the dielectric layer (Id.; 208) and a second via insulating layer on opposing sidewalls of the second via electrode (Id.; 206). Regarding claim 9, Park1 teaches wherein the dielectric layer includes an insulating material and/or a semiconductor material (Figs. 2F-2J and [0018]; the material of the support structure/substrate 202 (e.g., silicon)). Claim(s) 3-8 are rejected under 35 U.S.C. 103 as being unpatentable over Park1 et al. in further view of Park2 (US Patent No. 9691684). Regarding claim 3, Park2 teaches wherein at least one of the first power delivery network layer and the second power delivery network layer includes a first active connection line that is electrically connected to one of the first via electrode structure and the second via electrode structure and a first active wiring line that is electrically connected to the first active connection line (Figs. 1-2 point to a first wiring structure 92.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Park1 et al. and Park2, such that a connection line and wiring line are formed and electrically connected to at least one of the via electrode structures in order to establish a vertical electrical connection through the device. Regarding claim 4, Park2 teaches wherein the first active wiring line extends in the first horizontal direction on one of the first surface and the second surface of the dielectric layer, and the first active connection line extends in the second horizontal direction on the one of the first surface and the second surface of the dielectric layer (Figs. 1-2 point to a first wiring structure 92.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Park1 et al. and Park2, such that the wiring line and connection line are along the first and second horizontal directions, respectively, in order to establish a vertical electrical connection that maintains adequate contact with a via electrode structure and/or fits within the critical dimensions of the overall structure. Regarding claim 5, Park2 teaches wherein the first active wiring line extends in the second horizontal direction on one of the first surface and the second surface of the dielectric layer, and the first active connection line extends in the first horizontal direction on the one of the first surface and the second surface of the dielectric layer (Figs. 1-2 point to a second wiring structure 94.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Park1 et al. and Park2, such that the wiring line and connection line are along the second and first horizontal directions, respectively, in order to establish a vertical electrical connection that maintains adequate contact with a via electrode structure and/or fits within the critical dimensions of the overall structure. Regarding claim 6, Park2 teaches wherein at least one of the first power delivery network layer and the second power delivery network layer includes a first pad connection line that is electrically connected to one of the first via electrode structure and the second via electrode structure and a first pad wiring line that is electrically connected to the first pad connection line (Figs. 1-2 point to a first wiring structure 92.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Park1 et al. and Park2, such that a connection line and wiring line are formed and electrically connected to at least one of the via electrode structures in order to establish a vertical electrical connection through the device. Regarding claim 7, Park2 teaches wherein the first pad wiring line extends in the first horizontal direction on one of the first surface and the second surface of the dielectric layer, and the first pad connection line extends in the second horizontal direction on the one of the first surface and the second surface of the dielectric layer (Figs. 1-2 point to a first wiring structure 92.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Park1 et al. and Park2, such that the wiring line and connection line are along the first and second horizontal directions, respectively, in order to establish a vertical electrical connection that maintains adequate contact with a via electrode structure and/or fits within the critical dimensions of the overall structure. Regarding claim 8, Park2 teaches wherein the first pad wiring line extends in the second horizontal direction on one of the first surface and the second surface of the dielectric layer, and the first pad connection line extends in the first horizontal direction on the one of the first surface and the second surface of the dielectric layer (Figs. 1-2 point to a second wiring structure 94.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Park1 et al. and Park2, such that the wiring line and connection line are along the second and first horizontal directions, respectively, in order to establish a vertical electrical connection that maintains adequate contact with a via electrode structure and/or fits within the critical dimensions of the overall structure. Response to Arguments Applicant’s arguments, see Remarks, filed 07/29/2026, with respect to the objection(s) of claims 6-8 in view of claims 3-5 have been fully considered and are persuasive. The objections of said claims have been withdrawn. Applicant’s arguments, see Remarks, filed 07/29/2026, with respect to the rejection(s) of claim(s) 1 (and by extension any dependent claims) under 35 U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Park1 (PGPub No. 20220254872) in further view of Mao (PGPub No. 20080076229). Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Patrick L Cullen whose telephone number is (703)756-1221. The examiner can normally be reached Monday - Friday, 8:30AM - 5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at (571)270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICK CULLEN/ Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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Prosecution Timeline

Sep 06, 2023
Application Filed
May 01, 2026
Non-Final Rejection mailed — §103
Jun 04, 2026
Applicant Interview (Telephonic)
Jun 04, 2026
Examiner Interview Summary
Jul 29, 2026
Response Filed
Oct 05, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
86%
Grant Probability
99%
With Interview (+25.0%)
3y 6m (~4m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 21 resolved cases by this examiner. Grant probability derived from career allowance rate.

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