DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings received on 09/06/2023 have been accepted by the examiner.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449, filed 09/06/2023. The information disclosed therein was considered.
Election/Restrictions
Applicant's election with traverse of Invention II claims 10-16 in the reply filed on 10/15/2025 is acknowledged. The traversal is on the ground(s) that “As described above, claims 1, 10, 17, and 22 all share the common technical characteristic of operating in response to the clock synchronization signal (the clock synchronization command or the preliminary command) and the idle signal (the precharge command or the second row command). Therefore, we would like to assert that examining claims 1, 10, 17, and 22 together will not increase the examiner's burden. At the very least, claims 10, 17, and 22, which do not include the delayed idle signal, should be considered together with claim 1”.
This is not found persuasive because clearly, subcombination I. has separate utility such as the limitation and configured to disable the power gating signal responsive to a delayed idle signal”, wherein requires the idle signal to be delayed in order for the device to operate. In the case of invention Il, it is usable/operative without the use of having the idle signal being delayed. The power gating signal can be disable with the idle signal. In the instant case, subcombination Ill has separate utility such as the limitation “a global column control circuit and the preliminary command being received before the receipt of an active command, or a write command, or a read command”, wherein requires a specific circuit design to build the global column control circuit and the power gating control circuit having a different functionality by having the preliminary command being received before the receipt of an active , write or read command. In the case of invention Il, it is usable/operative without the use of having the power gating control to generate a power gating signal that the preliminary command being received before the receipt of the active, write or read command. In the instant case, subcombination Ill has separate utility such as the limitation “the preliminary command being received before the receipt of an active command, or a write command, or a read command”, wherein it requires the power gating control circuit having a different functionality by having the preliminary command being received before the receipt of an active, write or read command. Furthermore, In the case of invention V, it is usable/operative without the use of having the power gating control to generate a power gating signal that the preliminary command being received before the receipt of the active, write or read command. See MPEP § 806.05(d).
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 10-11 & 14-16 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Kwon et al (US20190007031).
Regarding claim 10, Kwon discloses a semiconductor apparatus comprising: a power gating control circuit(FIG 1A; 100A comprising power gating circuit 20A) configured to generate a power gating signal responsive to a clock synchronization signal and an idle signal(FIG 2-3;[0017& 0025-0026] discloses En1, Clk signal and standby mode) and configured to prevent the power gating signal from being enabled when the idle signal is enabled([0025-0026] discloses when the system is in standby mode, EN1 is deactivated to a logic low level e.g.,. from being enabled); and a power gating circuit configured to apply a first operating voltage to an internal circuit of the semiconductor apparatus responsive the power gating signal (Vdd when EN1 is high logic).
Regarding claim 11, Kwon discloses wherein the semiconductor apparatus is configured to receive a first clock signal and a second clock signal; and wherein the clock synchronization signal is generated from a preliminary command (FIG 3; EN1, clock B and A), which causes the second clock signal to be synchronized with the first clock signal (B and A are synchronized).
Regarding claim 14, Kwon discloses wherein, when the idle signal is disabled and the clock synchronization signal is enabled, the power gating control circuit enables the power gating signal (FIG 3; [0025] disclose standby mode is disabled when En1 is high logic state Clk is e.g., enabled), and when the idle signal is enabled, the power gating control circuit disables the power gating signal ([0025] standby mode enabled when EN1 is disabled e.g., logic low level).
Regarding claim 15, Kwon discloses wherein the power gating control circuit is additionally configured to receive a synchronization completion signal generated based on the clock synchronization signal(FIG 5; D T1-T5), and when the idle signal is disabled and at least one of the clock synchronization signal and the synchronization completion signal is enabled([0025] standby mode, EN1 is at low logic level and clock), the power gating control circuit is configured to enable the power gating (EN1 enabled when standby mode is low logic level).
Regarding claim 16, Kwon discloses wherein the power gating control circuit is further configured to provide a second operating voltage to the internal circuit of the semiconductor device, based on the power gating signal (FIG 1-3; high and low-level states).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kwon et al in view of Jang et al (US20070183251).
Regarding claim 12, Kwon discloses wherein, after the preliminary command is received, the gating control circuit (FIG 1-3; 20A and EN1)
However, Kwon does not disclose receives at least one of an active command, a write command, and a read command.
In the same field of endeavor, Jang discloses receives at least one of an active command, a write command, and a read command (FIG 9-11; [0092-0107] discloses an active command, write command, read command).
Kwon and Jang are analogous art because they are all directed to a memory device comprising clocks and power down mode, and one of ordinary skill in the art would have had a reasonable expectation of success by modify Kwon to include Jang because they are from the same field of endeavor.
Therefore, it would be obvious to include the teachings of Jang in the teachings of Kwon for the benefits reducing a power consumption of the memory device ([0021] Jang)
Regarding claim 13, Kwon discloses wherein the semiconductor apparatus is configured to generate an idle signal (FIG 1-3; standby mode).
However, Kwon does not disclose is generated based on an active command and a precharge command.
In the same field of endeavor, Jang discloses is generated based on an active command and a precharge command (FIG 11; Act command and pre-charge command).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Syed et al (US20040158750 FIG 8; discloses Gate power unit 902 and Clk and power control unit 704).
Chen et al (US20050218952 FIG 11; discloses Clks signals and synchronizations).
Yoo et al (US20230104271 FIG 3B-5; discloses clocks and Idle mode e.g., in self-refresh mode)
Tan et al (US20180040273 FIG 1-3B; [0018] discloses power signal terminal outputs).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUNA A TECHANE whose telephone number is (571)272-7856. The examiner can normally be reached 571-272-7856.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MUNA A TECHANE/Primary Examiner, Art Unit 2827