Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/08/2026 has been entered.
Claims 1-19 are presented for Examination.
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 19 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Regarding Claim 19, the limitations “ the pass device and the additional degenerative pass device are connected in series” does not further limit the independent claim 13.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1,2, 4, 6,7,8,10,12 is/are rejected under 35 U.S.C. 102(a) (1) as being anticipated by Lu et.al. (U.S Patent Application Publication 2019/0384337; hereinafter “Lu”; (Reference cited as prior art in previous office action)].
Regarding claims 1, 7, Lu discloses a method for distributed voltage regulation by current sharing, the method comprising:
receiving an input voltage on a chip[ “..The power transistor 116-1 is turned on by the error amplifier signal (e.g., the gate is charged to the particular gate voltage) to pass a supply voltage (e.g., VIN) , 0030; “the first terminals of the power transistor 216-1 and the feedback transistor 217-1 are connected to one another and tied to a common supply voltage (e.g., VIN)..”, 0045]; and
regulating the input voltage using current sharing through a plurality of distributed low voltage dropout micro regulators to produce regulated voltage[“ paralleling of monolithic embedded LDO power rails to provide additional load current, while maintaining accurate current sharing and balancing between paralleled LDOs without additional power consumption in a heavy load”, 0022; “ The control circuit 100 provides several advantages over the prior approaches, among others, the offset voltage produced from the sensed shared current can be added between the input reference voltage signal and output regulated voltage signal to cancel the DC offset of each channel, so the current of each channel is substantially the same…”, 0027],
each low voltage dropout micro regulator[ “..The channels are connected in parallel to one another and respectively drive a regulated voltage to a dynamic load circuit. The control circuit 100 produces an output voltage 113 that is a byproduct of the output voltages produced by the paralleled channels…”, 0027; The first channel 110 includes an offset generator 112-1, an error amplifier 114-1, a power transistor 116-1, and a current sensor 118- 1..”, 0028; (i.e each channel corresponds to a low drop-out (LDO) linear voltage regulator circuit) including a pass device [ “The offset generator circuit as depicted in FIG. 4B differs, in part, from that shown in FIG. 4A. For example, the offset generator (e.g., 452) includes the switch network 448, a current source 456, a pass element 458, and a differential difference amplifier 454”, 0062; Fig.4B; (i.e the offset generator including a pass element corresponds to the pass device) and an additional degenerative pass device provided in series with the pass device [“The first channel 210 includes an amplifier 214-1, a power transistor 216-1, a feedback transistor 217-1, and a resistor 218-1. In some aspects, the current sensor 118-1 includes the feedback transistor 217-1…”, 0039; 0037;( i.e. each channel further including other circuit elements (power transistor, current sensor including feedback transistor etc) in addition to the pass element of the offset generator circuit. The other circuit elements including the power transistor and feedback transistor( including the current sensor with sense transistors) corresponds to the additional degenerative pass device); “ The sources of the sense transistors 418-3 and 418-4 are tied to the drain of the pass element 458. The output signal from the switch network 448 at node 460 drives the gate of the pass element 458 to control the passing of current from the current source 456”, 0064; Fig.4B; (i.e the sense transistors included in the additional degenerative pass device are connected in series with the pass element)].
the additional degenerative pass device providing gain reduction with improved current sharing and local feedback in the low voltage dropout microregulator [ 0027; (i.e., sharing current between the LDO channels equally); 0033-0034; 0037; “The output signal (VOUT) of the first channel 210 is fed back through the ESR network yielding the signal VFB1 (e.g., 215-1) at the non-inverting input of the amplifier 214-1. .. As the amplifier output increases, that output voltage is fed back to the inverting input, thereby acting to decrease the voltage differential between the inputs. When the input differential is reduced, the amplifier output and the system gain are also reduced. In FIG. 2, because the amplifier 214-1 is a dual-stage amplifier, the reference signal 211 is shown connected to the inverting input rather than the non-inverting input. Nevertheless, because the output is fed back in a manner that reduces the system gain, the result is negative feedback, sometimes called degenerative feedback.”, 0041; ( i.e each regulator circuit providing a local feedback via a transistor and resistor and a differential amplifier to reduce the system gain and balance /share the current between the LDO’s)].
the additional degenerative pass device controlling current in the low voltage dropout micro regulator to enable current sharing evenly among the plurality of distributed low voltage dropout micro regulators.[“ an active current sharing method that uses the active current sharing loop to achieve the current balance between the slave and the master LDO regulators. “,0021-0022; lossless current sensing is used to sense the current for each channel and produce corresponding voltages for comparison. .. The offset voltage is added between an input reference voltage (e.g., VREF) and an output regulated voltage (e.g., VOUT) to cancel the DC offset of each channel, so the current of each channel is substantially the same. “, 0023; “ The current sensor 118-1 is configured to measure how much current of the first channel 110 is being drawn at the load by measuring the corresponding voltage for the first channel 110 (e.g., V.sub.SENSE_MASTER). In some aspects, the V.sub.SENSE_MASTER signal facilitates in producing a feedback voltage (e.g., V.sub.FB1) along the feedback loop path. In this respect, the feedback voltage V.sub.FB1 corresponds to the measured current of the first channel 110. The current sensor 118-1 may produce the feedback voltage V.sub.FB1 (or V.sub.SENSE_MASTER signal) with an impedance network along the feedback loop. In some aspects, the impedance network includes an equivalent series resistance element (e.g., a resistor). “, 0031; “ In operation, when the load current increases, the output voltage 113 may decrease. In this respect, the feedback voltage decreases as well. As a result, the error amplifier 114-1 may generate more current into the gate of the power transistor 116-1. This reduces the voltage drop across the source-drain of the power transistor ….”, 0033;( i.e. the current sensor included in the feedback transistor controls the current and enables current sharing between the channels by implementing a feedback path to balance the current and provide a regulated output voltage)];
and the additional degenerative pass device controlling the current in the low voltage dropout micro regulator by using the local feedback to limit current in the low voltage dropout micro regulator[ 0027; 0041;Fig.2; ( i.e . providing a local feedback via a transistor and resistor)] and allow more even current among the plurality of distributed low voltage dropout micro regulators [0021-0023; 0031;0033; ( i.e. the circuit elements including the power transistor, feedback transistor( including the current sensor with sense transistors), controls the current based on the feedback voltage and measured current to balance the current evenly among the regulators )].
Regarding claims 2, 8, Lu discloses, wherein the additional degenerative pass device provides degenerative resistance [ “The ESR network includes a resistor 218-1 (e.g., RESR1).”, 0040, Fig.2].
Regarding claims 4,10, Lu discloses, wherein the additional degenerative pass device is controlled by ground in the low voltage dropout micro regulator [0058; claim 11].
Regarding claims 6, 12, Lu discloses, wherein the distributed low voltage dropout micro regulators are located in multiple locations on the chip [“Paralleling LDO regulators may provide benefits over a single LDO regulator, including distributing the heat and power loss across multiple LDO regulator packages in high loads..”, 0018 ; 0022].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 5, 9, 11 are rejected under 35 U.S.C. 103 as being unpatentable over Lu
Regarding claims 3, 9, 11, Lu discloses, wherein the additional degenerative pass device includes a resistor transistor hat is in addition to a pass transistor in the low voltage dropout micro regulator [ 0040; “drain of the feedback transistor 217-1 connects to the non-inverting input of the amplifier 214-1. The gate of the power transistor 216-1 is connected to the gate of the feedback transistor 217-1, allowing the feedback transistor 217-1 to function as a current mirror that outputs a scaled version of the current flowing through the power transistor 216-1. The current flowing through the feedback transistor 217-1 is supplied to the feedback loop and to the ESR network. The voltage produced at node 208 contributes to signal VFB1”, 0042; “..p-channel transistor..”, 0044].
However, Lu does not expressly disclose a PFET.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Lu to implement a PFET., since it has been held to be within the general skill of a worker in the art to select the component on the basis of its suitability for the intended use as a matter of design choice.
Regarding claim 5, wherein the additional degenerative pass device includes a resistor that is in addition to a pass transistor in the low voltage dropout micro regulator [0040; 0042; 0044; (i.e including a resistor in addition to a p-channel transistor) ].
However, Lu does not expressly disclose a P-type field effect transistor(PFET).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Lu to implement a PFET., since it has been held to be within the general skill of a worker in the art to select the component on the basis of its suitability for the intended use as a matter of design choice.
Claims 13-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lu in view of Rusu et.al. (U.S Patent Application Publication 2022/0302089; hereinafter “Rusu”; (Reference cited as prior art in previous office action))
Regarding claim 13, Lu discloses a system for distributed voltage regulation by current sharing, the system comprising:
a plurality of distributed low voltage dropout micro regulators regulating an input voltage using current sharing to produce regulated voltage [“ paralleling of monolithic embedded LDO power rails to provide additional load current, while maintaining accurate current sharing and balancing between paralleled LDOs without additional power consumption in a heavy load”, 0022; “ The control circuit 100 provides several advantages over the prior approaches, among others, the offset voltage produced from the sensed shared current can be added between the input reference voltage signal and output regulated voltage signal to cancel the DC offset of each channel, so the current of each channel is substantially the same…The control circuit 100 produces an output voltage 113 that is a byproduct of the output voltages produced by the paralleled channels. The control circuit 110 is configured to maintain the output voltage 113 at a target steady voltage (e.g., voltage rail) for the dynamic load circuit. The control circuit 100 is designed to drive a wide variety of load circuits”, 0027],
each low voltage dropout micro regulator[ “..The channels are connected in parallel to one another and respectively drive a regulated voltage to a dynamic load circuit. The control circuit 100 produces an output voltage 113 that is a byproduct of the output voltages produced by the paralleled channels…”, 0027; The first channel 110 includes an offset generator 112-1, an error amplifier 114-1, a power transistor 116-1, and a current sensor 118- 1..”, 0028; (i.e each channel corresponds to a low drop-out (LDO) linear voltage regulator circuit) including a pass device [ “The offset generator circuit as depicted in FIG. 4B differs, in part, from that shown in FIG. 4A. For example, the offset generator (e.g., 452) includes the switch network 448, a current source 456, a pass element 458, and a differential difference amplifier 454”, 0062; Fig.4B; (i.e the offset generator including a pass element corresponds to the pass device) and an additional degenerative pass device provided in series with the pass device [“The first channel 210 includes an amplifier 214-1, a power transistor 216-1, a feedback transistor 217-1, and a resistor 218-1. In some aspects, the current sensor 118-1 includes the feedback transistor 217-1…”, 0039; 0037;( i.e. each channel further including other circuit elements (power transistor, current sensor including feedback transistor etc) in addition to the pass element of the offset generator circuit. The other circuit elements including the power transistor and feedback transistor( including the current sensor with sense transistors) corresponds to the additional degenerative pass device); “ The sources of the sense transistors 418-3 and 418-4 are tied to the drain of the pass element 458. The output signal from the switch network 448 at node 460 drives the gate of the pass element 458 to control the passing of current from the current source 456”, 0064; Fig.4B; (i.e the sense transistors included in the additional degenerative pass device are connected in series with the pass element)].
the additional degenerative pass device providing gain reduction with improved current sharing and local feedback in the low voltage dropout microregulator [ 0027; (i.e., sharing current between the LDO channels equally); 0033-0034; 0037; “The output signal (VOUT) of the first channel 210 is fed back through the ESR network yielding the signal VFB1 (e.g., 215-1) at the non-inverting input of the amplifier 214-1. .. As the amplifier output increases, that output voltage is fed back to the inverting input, thereby acting to decrease the voltage differential between the inputs. When the input differential is reduced, the amplifier output and the system gain are also reduced. In FIG. 2, because the amplifier 214-1 is a dual-stage amplifier, the reference signal 211 is shown connected to the inverting input rather than the non-inverting input. Nevertheless, because the output is fed back in a manner that reduces the system gain, the result is negative feedback, sometimes called degenerative feedback.”, 0041; ( i.e each regulator circuit providing a local feedback via a transistor and resistor and a differential amplifier to reduce the system gain and balance /share the current between the LDO’s)].
the additional degenerative pass device controlling current in the low voltage dropout micro regulator to enable current sharing evenly among the plurality of distributed low voltage dropout micro regulators.[“ an active current sharing method that uses the active current sharing loop to achieve the current balance between the slave and the master LDO regulators. “,0021-0022; lossless current sensing is used to sense the current for each channel and produce corresponding voltages for comparison. .. The offset voltage is added between an input reference voltage (e.g., VREF) and an output regulated voltage (e.g., VOUT) to cancel the DC offset of each channel, so the current of each channel is substantially the same. “, 0023; “ The current sensor 118-1 is configured to measure how much current of the first channel 110 is being drawn at the load by measuring the corresponding voltage for the first channel 110 (e.g., V.sub.SENSE_MASTER). In some aspects, the V.sub.SENSE_MASTER signal facilitates in producing a feedback voltage (e.g., V.sub.FB1) along the feedback loop path. In this respect, the feedback voltage V.sub.FB1 corresponds to the measured current of the first channel 110. The current sensor 118-1 may produce the feedback voltage V.sub.FB1 (or V.sub.SENSE_MASTER signal) with an impedance network along the feedback loop. In some aspects, the impedance network includes an equivalent series resistance element (e.g., a resistor). “, 0031; “ In operation, when the load current increases, the output voltage 113 may decrease. In this respect, the feedback voltage decreases as well. As a result, the error amplifier 114-1 may generate more current into the gate of the power transistor 116-1. This reduces the voltage drop across the source-drain of the power transistor ….”, 0033;( i.e. the current sensor included in the feedback transistor controls the current and enables current sharing between the channels by implementing a feedback path to balance the current and provide a regulated output voltage)];
and the additional degenerative pass device controlling the current in the low voltage dropout micro regulator by using the local feedback to limit current in the low voltage dropout micro regulator[ 0027; 0041;Fig.2; ( i.e . providing a local feedback via a transistor and resistor)] and allow more even current among the plurality of distributed low voltage dropout micro regulators [0021-0023; 0031;0033; ( i.e. the circuit elements including the power transistor, feedback transistor( including the current sensor with sense transistors), controls the current based on the feedback voltage and measured current to balance the current evenly among the regulators )].
Receive regulated voltage from the plurality of distributed low voltage dropout micro regulators[ 0078; (i.e load circuit including plurality of processor cores receives the regulated voltage)]
However, Lu does not expressly disclose a memory; a processor coupled to the memory , wherein the memory and the processor receive voltage from the plurality of distributed low voltage dropout micro regulators. Lu teaches load circuit including plurality of processor cores receiving a regulated voltage. Lu does not expressly disclose memory and the processor receive voltage from the plurality of distributed low voltage dropout micro regulators.
In the same field of endeavor (e.g. a cache die including a low-dropout (LDO) regulator and a cache memory device; the cache die is stacked under the compute die using, for example, hybrid bond (HB) structures, power can be delivered vertically with little lateral distribution to provide lower power consumption, better performance, smaller chip areas, and lower costs), Rusu teaches ,
a memory[ “..The LDO regulators 10-3, 10-4, 10-5, and 10-6 may be built between sub-arrays of the cache memory device in the cache die 204…”, 0031; Fig.6].
a processor coupled to the memory[“ the compute die 206 includes four cores 208-1, 208-2, 208-3, and 208-4, arranged in an array having two rows and two columns..”, 0031; Fig.6 ; “The cache die 204 and the compute die 206 are connected to each other by interconnect structures 210”, 0021].
wherein the memory and the processor receive voltage from the plurality of distributed low voltage dropout micro regulators [ 0021; 0031; Fig.6].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Lu with Rusu. Rusu’s teaching of a cache die including a low-dropout (LDO) regulator and a cache memory device and stacking the cache die under the compute die using, for example, hybrid bond (HB) structures will substantially improve Lu’s system by providing power vertically to the cores with a little lateral distribution will result in shorter sense lines and lower IR drops and the overall power delivery performance is improved [0017, 0022].
Regarding claim 14, Lu discloses, wherein the additional degenerative pass device provides degenerative resistance[ “The ESR network includes a resistor 218-1 (e.g., RESR1).”, 0040, Fig.2].
Regarding claims 15, 17 Lu discloses, wherein the additional degenerative pass device includes a resistor transistor that is in addition to a pass transistor in the low voltage dropout micro regulator [ 0040; “drain of the feedback transistor 217-1 connects to the non-inverting input of the amplifier 214-1. The gate of the power transistor 216-1 is connected to the gate of the feedback transistor 217-1, allowing the feedback transistor 217-1 to function as a current mirror that outputs a scaled version of the current flowing through the power transistor 216-1. The current flowing through the feedback transistor 217-1 is supplied to the feedback loop and to the ESR network. The voltage produced at node 208 contributes to signal VFB1”, 0042; “..p-channel transistor..”, 0044].
However, Lu does not expressly disclose a P-type field effect transistor(PFET).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Lu to implement a PFET., since it has been held to be within the general skill of a worker in the art to select the component on the basis of its suitability for the intended use as a matter of design choice.
Regarding claim 16, Lu discloses, wherein the additional degenerative pass device is controlled by ground in the low voltage dropout micro regulator [0058; claim 11].
Regarding claim 18, Rusu teaches , wherein the distributed low voltage dropout micro regulators are located in multiple locations on the memory and processor [0021; FIG. 6 is a diagram illustrating a 3D IC package 200c in accordance with some embodiments. The 3D IC package 200c is one implementation of the 3D IC package 200 of FIG. 1, and they are similar in many aspects. Thus, like reference numerals indicate like components, and the details thereof are not repeated for simplicity. In the example of FIG. 6, the compute die 206 includes four cores 208-1, 208-2, 208-3, and 208-4, arranged in an array having two rows and two columns. The cache die 204 includes eight LDO regulators 10-1, 10-2, 10-3, 10-4, 10-5, 10-6, 10-7, and 10-8. Each of the four cores has a pair of LDO regulators abutting it in the Y direction. The LDO regulators 10-1 and 10-3 are supplying power to the core 208-1; the LDO regulators 10-2 and 10-4 are supplying power to the core 208-2; the LDO regulators 10-5 and 10-7 are supplying power to the core 208-3; the LDO regulators 10-6 and 10-8 are supplying power to the core 208-4. The LDO regulators 10-3, 10-4, 10-5, and 10-6 may be built between sub-arrays of the cache memory device in the cache die 204”, 0031].
Regarding claim 19, Lu discloses the pass device and the additional degenerative pass device are connected in series[0039; 0037;( i.e. each channel further including other circuit elements (power transistor, current sensor including feedback transistor etc) in addition to the pass element of the offset generator circuit. The other circuit elements including the power transistor and feedback transistor( including the current sensor with sense transistors) corresponds to the additional degenerative pass device); “ The sources of the sense transistors 418-3 and 418-4 are tied to the drain of the pass element 458. The output signal from the switch network 448 at node 460 drives the gate of the pass element 458 to control the passing of current from the current source 456”, 0064; Fig.4B; (i.e the sense transistors included in the additional degenerative pass device are connected in series with the pass element)].
Response to Arguments
a) Applicant’s arguments with respect to the newly amended limitations for claim(s) 1, 7, 13 have been considered but are moot because the arguments do not apply to Lu (claims 1, 7), Lu in view of Rusu (claim13) references as set forth in the above rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Le et al. U.S Patent 9,917,513, teaches An integrated circuit with voltage regulator circuitry is provided. The voltage regulator circuitry may include an adaptive bleeder circuit. The adaptive bleeder circuit may include one or more switchable current leaker paths and an associated bleeder control circuit having current sensing circuitry and voltage comparison circuitry. Adaptive bleeder circuit configured in this way can help maintain stability of the voltage regulator while minimizing dynamic power consumption.
Guan et al. U.S Patent Application Publication 2016/0291619, teaches a low-dropout regulator comprises a pass transistor having a first terminal to receive an input voltage, a second terminal to provide an output voltage, and a gate terminal. A feedback circuit is coupled between the second terminal of the pass transistor and ground to generate a feedback voltage in response to the output voltage.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GAYATHRI SAMPATH whose telephone number is (571)272-5489. The examiner can normally be reached on Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached on 5712701640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GAYATHRI SAMPATH/Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176