Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant's arguments filed 9/9/2026 have been fully considered but they are not persuasive. Applicant makes four arguments: (1) first, that Brayton should not be used when interpreting claim language, (see Response filed 9/9/2026 [page 7 paragraph 4]-[page 9 paragraph 2]); (2) second, using Brayton to help interpret claim language requires Brayton to be part of the obviousness rejection, (see Response filed 9/9/2026 [page 9 paragraphs 3-5]); (3) third, Possani does not teach the first two limitations of claim 1, (Response filed 9/9/2026 [page 10]); and (4) fourth, Machado does not teach the additional limitations of claim 10, (Response filed 9/9/2026 [page 11 paragraph 3]-[page 13]). Examiner disagrees with each argument, but will respond to each accordingly.
In the first argument, Applicant argues:
Here, the Office Action cites and quotes paragraph [0035] of Applicant's specification for "guidance". The Office Action then relies on another document, "MIS: A Multiple-Level Logic Optimization System" by Brayton (hereinafter "Brayton"), to apparently inform the "broadest reasonable interpretation in light of the specification". However, the Office Action seems to have overlooked description of "globally optimize for factored form literals" provided in Applicant's specification.
(Response filed 9/9/2026 [page 8 paragraph 2]).
Examiner disagrees. The rule is:
I. The words of a claim must be given their "plain meaning" unless such meaning is inconsistent with the specification. Under a broadest reasonable interpretation (MPEP), words of the claim must be given their plain meaning, unless such meaning is inconsistent with the specification. The plain meaning of a term means the ordinary and customary meaning given to the term by those of ordinary skill in the art at the relevant time. The ordinary and customary meaning of a term may be evidenced by a variety of sources, including the words of the claims themselves, the specification, drawings, and prior art.
(See MPEP 2111.01(I))(Emphasis added).
Examiner reviewed the entire specification and determined that some of the words in the specification were terms of art. These are specific words that have a plain meaning in the art different from what could be determined from using standard dictionary definitions. Plain meaning refers to the ordinary and customary meaning given to the term by those of ordinary skill in the art (see MPEP 2111(III)).
In addition to the passages already mentioned, the specification has many statements about globally optimize for factored form literals:
“The AIG may use size as a cost function to limit a number of AIG nodes”, (Specification [0007] line 7).
“The methods lead to reduced literal counts, compared to the traditional methods focusing on minimizing the number of AIG nodes”, (Specification [0035] lines 6-7).
Factored form (FF) literals are well correlated with the number of gates in an AIG which is the most used cost function for logic synthesis nowadays, (Specification [0057] lines 1-2).
These excerpts from the specification all give constraints to the BRI based on what is “reasonable in light of the specification”, but they do not provide definitions. Note how the passages somewhat conflict with each other, which is not an issue because they are not definitions.
Brayton has a section labeled “III. Definitions” (see 1987-Brayton [page 1065] and another section labeled “IV. Global Area Optimization” that defines the original optimization technique, (see 1987-Brayton [page 1068]). These two sections were helpful to Examiner in understanding the terms of art used in the claims.
Examiner reviewed the passages given (see Specification [0056] and [0046]) and found no definition in the cited passages (e.g., “x refers to ...”, “x is defined as...”, or simply “x is...” without qualifying language like “in an embodiment”). Therefore, Applicant is not relying on a lexicographic definition. Examiner used the prior art reference to determine the plain meaning of a term of art, which is provided for in the rule as stated above. Therefore, the argument is not persuasive.
In the second argument, Applicant argues:
Moreover, to the extent that Brayton was relied on to interpret features of claim 1, Applicant submits that the instant rejection would necessarily rely on Brayton as well in determining that the claimed technology is purportedly obvious in view of the prior art. However, the instant rejection does not cite or even mention Brayton.
(Response filed 9/9/2026 [page 9 paragraph 5]).
Brayton is not necessary to teach the claims, but instead is used to interpret the claims. The two concepts are different, and governed by different rules. For further help on understanding the difference between claim interpretation and obviousness rejections see MPEP 2111 (claim interpretation) and MPEP 2143 (obviousness rejections).
In the third argument, Applicant argues:
Possani relates to "a new graph-based method able to generate optimized transistor networks" (p.192, col. I, ,i 2). However, the Office Action does not provide any reasoning or rationale as to how or why Possani' s graph-based method relates to the above-quoted features of claim 1. Rather, the Office Action merely provides quotations and citations to Possani. Moreover, Possani (p.191, col.2, ,i,I 2-3) expressly describes this graph-based method as an alternative to Boolean factorization ( emphasis added).
(Response filed 9/9/2026 [page 10 paragraph 1 lines 9-13]).
Examiner disagrees because Applicant’s arguments are not commensurate in scope with the claim language. Applicant must argue what Possani does not teach that is in the claim language. Claim 1 claims
A computer-implemented method for transistor-level synthesis for an integrated circuit element, the method comprising:
generating, by one or more processors of a computer system, single-stage transistor networks from a set of Boolean functions, wherein each single-stage transistor network is composed of a pulldown network and a pullup network;
scaling, by the one or more processors, the single-stage transistor networks to multi-stage transistor networks to globally optimize for factored form literals; and
performing, by the one or more processors, technology mapping based on the factored form literals to generate a circuit design.
As can be seen the major elements of the claim are the input “a set of Boolean functions”, the first intermediate state “single-stage transistor networks”, the second intermediate state “multi-stage transistor networks”, and finally, the output “a circuit design”. Boolean factorization is not claimed in claim 1. The graphs in 2013-Possani correspond to the actual transistor networks that are claimed.
Examiner selected this prior art reference based on guidance provided in the specification, with a specific reference to “Improving Standard-Cell Design Flow using Factored Form Optimization” (2022-Calvino), which was submitted as an Appendix to the provisional application. This paper is part of the specification because the specification incorporates the provisional by reference, and the provisional incorporates the Appendix. The paper summarizes the algorithm at the end:
We implemented a global re-mapping method for AIGs targeting the minimization of FF literals. The method is similar to cost-based mappers applied to graphs [8]. It consists of cost driven mapping, followed by Boolean decomposition of each cut in the cover into an AIG, which can be seen as re-mapping. The algorithm works by computing cuts for each node using the fast cut enumeration procedure [16] and assigning to each cut a cost based on the FF representation. The FF is computed using the irredundant SOP (ISOP) extracted from the Boolean function of the cut. The SOP is then factored using algebraic or Boolean factoring [17]. Next, the technology mapper selects a cover to minimize the number of FF literals in the Boolean functions of the cuts used to cover the AIG.
(see Appendix to the Provisional Specification filed 11/22/2022 [page 5 col 2 paragraph 3])(Emphasis added).
Possani is a cost-base mapper applied to graphs of which switch networks (which is a synonym for transistor networks). To under Possani, one must understand the problem and the solution. First, the problem:
In current VLSI design, the total number of transistors necessary to implement logic gates is strongly related to the signal delay propagation, power consumption and area of integrated circuits (ICs) [1-3]. Transistor netlists are of special interest when designing standard cell libraries [4] or custom gates for IC design improvement [5]. To increase design quality in full-custom methodology, a handcraft generation of transistor netlists for each functional block may be performed. However, this is an extremely time-consuming task for larger ICs, making the adoption of such strategy prohibitive. Thus, it becomes crucial to have available efficient algorithms to automatically generate optimized transistor arrangements.
(2013-Possani [page 191 col 1 paragraph 1])(Emphasis added).
The paragraph above explains they are interested in “designing standard cell libraries [4] or custom gates for IC design improvement”. To achieve this goal, the authors are looking for “efficient algorithms to automatically generate optimized transistor arrangements”. Note both the terms “standard cell libraries” and “custom gates”, means they are using whatever process they disclose as the solution multiple times in order to create the libraries or custom gates. Next, the solution:
The proposed method starts from an ISOP, and tries to combine the cubes of a function to build NSP and SP kernels. These kernels are illustrated in Fig. 4(a) and in Fig. 6(a), respectively. Therefore, the method is divided in four well defined steps. The first three steps aim to build the kernels. The fourth one tries to merge the kernels found in order to deliver an optimized switch network.
(2013-Possani [page 102 col 2 paragraph 2])(Emphasis added).
The paragraph above shows they start from an ISOP, which is a set of Boolean functions. Then they build kernels, which are single-stage transistor networks. Next, they merge the kernels found in order to deliver an optimized switch network which are multi-stage transistor networks (i.e., multiple kernels).
Let’s look at an example. Eq. (8) provides an ISOP.
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(2013-Possani [page 194]). Eq. (8) is a representation of a set of Boolean networks. Note applicant amended to the broadening language “a set of”, which may include an empty set, a set of one, or multiple Boolean networks.
Fig. 11(b) and 12(b) show two kernels found/generated from eq. (8) using the kernel building steps described above.
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Fig. 11(b) shows a single stage transistor network from the second, third, fourth, and fifth term of eq. (8). Specifically, 11(b) is the switch network for !a.b.d + !a.b.c + a.!b.d + a.!b.c, and 12(b) is the switch network for !a.!b.b.c.!d + a.b.!c.!d + b.c.d. Finally, Fig. 13 “merges” or “scales” the two kernels, and then optimizes the circuit.
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You can see FIG. 13(a) has the single stage switch network from FIG. 11(b) on the left side and the single stage switch network from FIG. 12(b) on the right side. Then they globally optimize the factored form literals by minimizing them in FIG. 13(b) and FIG. 13(c), going from 14 down to 12.
The process of 2013-Possani is used to create a cell library, which may have custom gates, such as the one above, that map a gate defined as a set of Boolean expressions to a switch network. Then these custom gates are used in logic synthesis, which is a standard process taught by 2008-Da Rosa, and not argued by Applicant.
Finally, it is important to note that this is a high level example provided for Applicant’s benefit because Applicant’s representative argued they did not understand how Possani’s graph based method related to the quoted features of claim 1, (see Response filed 9/9/2026 [page 10 paragraph 1 line 10). The actual mapping provided in the rejection teaches each and every limitation.
Finally, Applicant argues:
Notwithstanding the deficiencies of the rejections of claims 1 and 14 described above, Applicant submits that the Office Action does not present a prima facie case of obviousness of claims 10 and 19.
(Response filed 9/9/2026 [page 11 paragraph 4 liens 1-3]), and:
Respectfully, neither the cited portions nor any other portions of Machado teach or suggest performing AIG resubstitution as claimed. Moreover, the assertion that "the last step in the process is AIG rewriting if improved, which is a form of resubstitution as shown in FIG. 2" is inaccurate. Applicant submits that AIG rewriting is not merely a form of resubstitution. Rather, AIG rewriting and AIG resubstitution are distinct operations. Indeed, Applicant's specification ( [0057]- [0059]) clearly describes AIG rewriting and AIG resubstitution as distinct operations.
(Response filed 9/9/2026 [page 12 paragraph 2]).
Examiner disagrees that Machado does not teach claim 10. Claim 10 claims:
The method of claim 1, wherein scaling the single-stage transistor networks to multi-stage transistor networks to globally optimize for factored form literals includes And- inverter graph (AIG) resubstitution for the factored form literals.
(see Amended Claims [claim 10]).
The specification uses the term “aims at” rather than “defines”, so the description is non-limiting, but any interpretations must be reasonable in light of the specification. The specification reads:
AIG resubstitution aims at minimizing the number of AND gates in an AIG by trying to replace some nodes by fewer ones starting from some divisors. The advantage of this method is to
be able to exploit local don't cares during the optimization process.
(Specification [0059] lines 1-3).
To understand Machado, one must read the abstract and understand the problem and solution presented.
This paper investigates AIG optimization for area, exploring how far Boolean methods can reduce AIG nodes through local optimization. Boolean division is applied for multi-output functions using two-literal divisors and Boolean decomposition is introduced as a method for AIG optimization.
(Machado [Abstract] lines 5-10).
The problem is to reduce AIG nodes using Boolean methods. The solution is using two-literal divisors. Look at the quoted section of the Specification and compare it with the abstract. The abstract does not talk about exploiting don’t cares, but the actual method is described on page 144. Eq. (1) is divided by the divisor y = a.b, and because of the DC-set (i.e., don’t care set), you can substitute y for all of the first terms to get eq. (2).
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(see Machado [page 144 col 1 paragraph 4]).
The fact that the method is applying the same divisor y = a.b. first to f_1, and then to f_2, and f_3 is what makes this form of decomposition a step within the process of resubstitution. Resubstitution does not happen until the substitutions are rewritten back into the full graph, which is shown by FIG. 2.
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AIG resubstitution as described by Applicant’s specification does not technically happen until the last step of rewriting is complete.
Finally, it is important to note that this is a high level example provided for Applicant’s benefit because Applicant’s representative argued they did not understand how Machado teaches resubstitution given the description provided in the specification, (see Response filed 9/9/2026 [page 13 paragraph 1, which is the excerpt from the specification). The actual mapping provided in the rejection teaches each and every limitation, as claimed.
Claim Interpretation
The term “factored form literals” is used in claim 1 line 7, and claim 1 lines 8-9. The term is also included in corresponding independent claim 14. The term is therefore at least incorporated by reference in all of the claims. The specification gives the following definitions:
...literals (variables complemented or not complemented). Thus, factored forms can be directly represented by an AIG by translating ANDs to ANDs, and ORs to ANDs using De Morgan's law.
(Specification [0039] lines 3-5).
In claim 1 line 7, the limitation “to globally optimize for factored form literals” is not specifically defined in the specification. However, the claim language must be given the broadest reasonable interpretation in light of the specification, which gives the following guidance:
Factored form is a powerful multi-level representation of a Boolean function that readily translates into an implementation of the function in CMOS technology. In particular, the number of literals of a factored form correlates well with the number of transistors in the CMOS implementation. Aspects of the technology involve developing novel methods for minimizing the total number of factored form literals needed to represent combinational logic given as an and inverter graph (AIG). The methods lead to reduced literal counts, compared to the traditional methods focusing on minimizing the number of AIG nodes.
(Specification [0035] lines 1-7).
After reviewing the art, the following excerpt from “MIS: A Multiple-Level Logic Optimization System” (1987-Brayton) seems relevant:
To justify the use of the total number of literals in the factored form as an area complexity measure, consider the implementation of f1 as a CMOS complex gate. It can be implemented as shown in Fig. 3 using nine pairs of n-type and p-type MOS transistors (assuming all signals and their complements are available). Thus, the number of literals in the factored form corresponds to the number of transistors needed to implement the function as a complex gate.
(1987-Brayton [page 1067 col 2 paragraph 7]).
In claim 3, the terms “algebraic or Boolean factoring” are used. No definition is provided in the specification. After reviewing the art, the following excerpt from “MIS: A Multiple-Level Logic Optimization System” (1987-Brayton) seems relevant:
When f and g have disjoint support, fg is an algebraic product (no Boolean operations are needed to obtain the product); otherwise jg is a Boolean product. For example, ( a + b )( c + d ) = ac + ad + be + bd is an algebraic product, and both (a + b)(a + c) = aa + ab + ac + bc = a + bc and ( a + b) ( !b + c) = a!b + ac + b!b + bc = a!b + bc are Boolean products.
(1987-Brayton [page 1067 col 1 paragraph 8]).
The term AIG resubstitution is used in claim 10. AIG resubstitution will be interpreted in light of the following excerpt from the specification:
AIG resubstitution aims at minimizing the number of AND gates in an AIG by trying to replace some nodes by fewer ones starting from some divisors. The advantage of this method is to
be able to exploit local don't cares during the optimization process.
(Specification [0059] lines 1-3).
As a last note regarding claim interpretation, Applicant incorporates by reference the entirety of the provisional application U.S. 63/426,935 (see Specification [0001]). The provisional application includes an Appendix 1 with a paper titled “Improving Standard-Cell Design Flow Using Factored Form Optimization”. The following paragraph from that paper is relevant:
We implemented a global re-mapping method for AIGs targeting the minimization of FF literals. The method is similar to cost-based mappers applied to graphs [8]. It consists of cost driven mapping, followed by Boolean decomposition of each cut in the cover into an AIG, which can be seen as re-mapping. The algorithm works by computing cuts for each node using the fast cut enumeration procedure [16] and assigning to each cut a cost based on the FF representation. The FF is computed using the irredundant SOP (ISOP) extracted from the Boolean function of the cut. The SOP is then factored using algebraic or Boolean factoring [17]. Next, the technology mapper selects a cover to minimize the number of FF literals in the Boolean functions of the cuts used to cover the AIG.
(see “Improving Standard-Cell Design Flow Using Factored Form Optimization”, [page 5 col 2 paragraph 3 lines 8-13]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 and 14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over “Efficient Transistor-Level Design of CMOS Gates” (2013-Possani) in view of “Automatic Generation and Evaluation of Transistor Networks in Different Logic Styles” (2008-daRosa)
With respect to claim 1, Possani teaches A computer-implemented method for transistor-level synthesis for an integrated circuit element, the method comprising (“the method is divided in four well defined steps. The first three steps aim to build the kernels. The fourth one tries to
merge the kernels found in order to deliver an optimized switch network”, [page 192 col 2 paragraph 2 lines 4-7]; and computer-implemented: “Intel Core i5 at 2.8GHz with 4Gb of RAM”, [page 196 col 1 paragraph 1 lines 2-3]) generating, by one or more processors of a computer system (Intel Core i5, [page 192 paragraph 1 lines 2-3]), single-stage transistor networks from a set of Boolean functions (The proposed method starts from an ISOP, and tries to combine the cubes of a function to build NSP and SP kernels, [page 192 col 2 paragraph 2 lines 1-2]; definition of ISOP is irredundant sum of products, which refers to a Boolean expression, [page 192 col 2 paragraph 1]; and applied to 53 functions, [page 195 col 1 paragraph 1 line 6]; in this stage, the kernels are mapped to switch networks as shown in FIGS. 4 and FIG. 6, which teaches generating single stage transistor networks, [page 193]: “The NSP kernels are mapped to switch networks applying a reordering in the label of the edges”, [page 193 col 1 paragraph 1]; “Similarly to the step (A), the algorithm of the step (B) must apply some transformations over the graph to map each found SP kernel to a switch network”, [page 193 col 1 paragraph 4 lines 1-3]), wherein each single-stage transistor network is composed of a pulldown network and a pullup network (the algorithm is applied to CMOS gates, (see [Title] and [Abstract]; It is important to notice that CMOS gates are made of two logically complementary networks, one PMOS network for pull up and one NMOS network for pull-down, as illustrated in Fig. 1; The remainder of this paper aims the generation of individual networks that can be used for either pull-up or pull down planes, [page 191 col 1 paragraph 2]-[page 191 col 2 paragraph 1]); scaling, by the one or more processors (Intel Core i5, [page 192 paragraph 1 lines 2-3]), the single-stage transistor networks to multi-stage transistor networks to globally optimize for factored form literals (The fourth one tries to merge the kernels found in order to deliver an optimized switch network, [page 192 col 2 paragraph 2 lines 5-7]; the intent of which is provide a literal count better than factorization, see [page 191 col 2 paragraph 2]; and “when considering only the literal count metric”, [page 191 col 2 paragraph 4 lines 4-5]) and performing, by the one or more processors (Intel Core i5, [page 192 paragraph 1 lines 2-3]), ... based on the factored form literals to generate a circuit design (It is worth to notice that existing techniques apply usually greedy
strategies and deliver satisfactory results. However, to the best of our knowledge, no one of these methods can achieve the best results even for a set of simple functions when considering only
the literal count metric [13], [page 191 col 2 paragraph 4 lines 1-5]; where “techniques” refer to factorization and graph based methods, [page 191 col 2 paragraphs 2-3]; and the purpose of reducing literal count is: “The transistor arrangement optimization is an effective possibility to improve VLSI design, especially when generating CMOS logic gates to be inserted in standard cell libraries”, [Abstract] lines 1-3; where the standard cell library is part of a larger process referred to as technology mapping; see also: “Transistor netlists are of special interest when designing standard cell libraries [4] or custom gates for IC design improvement”, [page 191 col 1 paragraph 1 lines 4-6]).
Possani does not specifically teach how technology mapping leads to VLSI/circuit design, but makes reference to “designing standard cell libraries”, which a person having skill in the art would recognize as part of the logic synthesis process, which includes technology mapping, but daRosa makes this explicit.
DaRosa teaches and performing, by the one or more processors, technology mapping based on the factored form literals to generate a circuit design (The proposal of standard-cell design is to reduce the implementation effort by reusing a library of cells,. The advantage of this approach is that the cells only need to be designed and verified once for a given technology, and they can be reused many times, thus amortizing the design cost, [page 16 paragraph 3]-[page 17 paragraph 1 line 2]; then “Technology mapping is the procedure of expressing a given Boolean network in terms of logic cells or gates. Typically, the objective function aims the optimal use of all gates in the library to implement a circuit with critical-path delay less than a target value and minimum area”, [page 17 paragraph 3 lines 1-4]; where the algorithms are performed on a CPU, [page 20 paragraph 2 line 7]).
It would have been obvious to one skilled in the art before the effective filing date to combine Possani with daRosa because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. In the first paragraph, Possani provides a specific teaching, suggestion, motivation for the purpose of the method, [page 191 col 1 paragraph 1 lines 1-6]. DaRosa goes into further detail explaining the bigger picture. The standard cell library is part of Technology mapping. Technology mapping is part of a larger process known as logic synthesis, which in turn is part of the process of circuit design:
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(daRosa [page 18]).
A person having skill in the art would have a reasonable expectation of building an optimized Cell Library using the method and system of Possani, which in turn can be used in the larger process that includes technology mapping as described by daRosa. Therefore, it would have been obvious to combine Possani with daRosa to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 2, Possani in view of daRosa teaches all of the limitations of claim 1, as noted above. Possani further teaches wherein generating the single-stage transistor networks includes: representing a function to be performed by the integrated circuit element as a sum-of-products (SOP) (The proposed method starts from an ISOP, and tries to combine the cubes of a function to build NSP and SP kernels, [page 192 col 2 paragraph 1 lines 1-2]); and finding a factorization that minimizes a number of the factored form literals (see [page 191 col 2 paragraph 2]; factorization could be applied to the (B) SP kernel finder step, [page 192 col 2 paragraph 2 bullet (B)]; note, section 3.2 and FIG. 6 shows a graph based method to find the kernel, [page 193]; Possani teaches that graph-based or factorization can be used, but chooses to use graph because graph methods can also find NSP arrangements, see [page 191 col 2 paragraph 3 lines 5-8]; for SP kernel finding, graph-based and factorization can be substituted for one another).
It would have been obvious to one skilled in the art before the effective filing date to combine Possani with Possani because this simple substitution of one known element for another to obtain predictable results. The graph based method of Possani is the base reference that teaches all limitations except for using factoring to get the SP kernels. As described by Possani, the substituted component of factoring for finding SP kernels is well-known in the art and the purpose of using factoring methods to optimize transistor networks is well known in the art, (Possani [page 191 col 2 paragraph 2]). One of ordinary skill in the art could have substituted the factoring method for the method at least in SP kernel finding, and the results of the substitution would have been predictable. Therefore, it would have been obvious to combine the main method of Possani that uses graph based method to find the SP kernel with the factoring disclosed in Possani to find the SP kernel to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 3, Possani in view of Marques teaches all of the limitations of claim 2, as noted above. Possani further teaches wherein finding the factorization includes performing one of algebraic or Boolean factoring (The most traditional solutions are based on algebraic and Boolean factorization, [page 191 col 2 paragraph 2 lines 2-3]).
It would have been obvious to one skilled in the art before the effective filing date to combine Possani with Possani because this simple substitution of one known element for another to obtain predictable results. The graph based method of Possani is the base reference that teaches all limitations except for using factoring to get the SP kernels. As described by Possani, the substituted component of factoring for finding SP kernels is well-known in the art and the purpose of using factoring methods to optimize transistor networks is well known in the art, (Possani [page 191 col 2 paragraph 2]). One of ordinary skill in the art could have substituted the factoring method for the method at least in SP kernel finding, and the results of the substitution would have been predictable. Therefore, it would have been obvious to combine the main method of Possani that uses graph based method to find the SP kernel with the factoring disclosed in Possani to find the SP kernel to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 4, Possani in view of daRosa teaches all of the limitations of claim 3, as noted above. Possani does not teach wherein the Boolean factoring generates a solution represented as an AND-OR graph, in which factored forms are generated for both the function to be performed and a complement of the function to be performed.
However, daRosa teaches wherein the Boolean factoring generates a solution represented as an AND-OR graph, in which factored forms are generated for both the function to be performed and a complement of the function to be performed (see specifically FIG. 2.19, [page 44], but more generally, [page 43 paragraph 2]-[page 45 paragraph 2]; FIG. 2.19 gives the factorized form of an equation using and-or graphs; with reference to eq’s. (2.13) and (2.14), the onset equation (2.13) represents the pullup network, and the offset equation represents the pulldown network, [page 44], The equation (2.14) can be factorized into equation (2.15). Equation (2.15) can be used to implement a topologically complementary switch network that respects the minimum number of elements in series, [page 45 paragraph 1]).
It would have been obvious to one skilled in the art before the effective filing date to combine Possani with daRosa because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. Possani teaches both factorization and graph-based methods, [page 191 col 2 paragraphs 2-3], but focuses mostly on graph-based methods because they find NSP arranges that factorization methods cannot, [page 191 col 2 paragraph 3 lines 5-8]. DaRosa, who is also an author on the Possani paper, provides further details on factorization procedures, and how and why most programs start from SOP form (sum-of-products), which is a two-level AND-OR graph, but then factorize the Boolean function, which results in a multi-level AND-OR graph;
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According to Mintz (2005), factorization is the procedure of deriving a factorized form from a SOP form of a function. For example, if f = a *e+a *d+b *c then one possible factorization off is a*(e+d)+b*c. In most logic synthesis systems Boolean functions are internally stored in the SOP form (SENTOVICH, 1992; KARMA, 2008). However, the number of elements in a switch network is more accurately represented by the number of literals in the factorized form of the network. This means that an efficient factorization method is required in order to minimize a switch network.
(daRosa [page 44 paragraph 1 lines 1-7]).
A person having skill in the art would have a reasonable expectation of optimizing as switch network using the method and system of Possani, using the factorization method of daRosa, at least for the SP kernel finding step. Therefore, it would have been obvious to combine Possani with daRosa to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 5, Possani in view of daRosa teaches all of the limitations of claim 3, as noted above. Possani does not teach wherein finding the factorization includes creating an AND-OR graph for each transistor topology corresponding to the factored form literals.
However, daRosa teaches wherein finding the factorization includes creating an AND-OR graph for each transistor topology corresponding to the factored form literals (see specifically FIG. 2.19, [page 44], but more generally, [page 43 paragraph 2]-[page 45 paragraph 2]; FIG. 2.19 gives the factorized form of an equation using and-or graphs; with reference to eq’s. (2.13) and (2.14), the onset equation (2.13) represents the pullup network, and the offset equation represents the pulldown network, [page 44], The equation (2.14) can be factorized into equation (2.15). Equation (2.15) can be used to implement a topologically complementary switch network that respects the minimum number of elements in series, [page 45 paragraph 1]).
It would have been obvious to one skilled in the art before the effective filing date to combine Possani with daRosa because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. Possani teaches both factorization and graph-based methods, [page 191 col 2 paragraphs 2-3], but focuses mostly on graph-based methods because they find NSP arranges that factorization methods cannot, [page 191 col 2 paragraph 3 lines 5-8]. DaRosa, who is also an author on the Possani paper, provides further details on factorization procedures, and how and why most programs start from SOP form (sum-of-products), which is a two-level AND-OR graph, but then factorize the Boolean function, which results in a multi-level AND-OR graph;
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According to Mintz (2005), factorization is the procedure of deriving a factorized form from a SOP form of a function. For example, if f = a *e+a *d+b *c then one possible factorization off is a*(e+d)+b*c. In most logic synthesis systems Boolean functions are internally stored in the SOP form (SENTOVICH, 1992; KARMA, 2008). However, the number of elements in a switch network is more accurately represented by the number of literals in the factorized form of the network. This means that an efficient factorization method is required in order to minimize a switch network.
(daRosa [page 44 paragraph 1 lines 1-7]).
A person having skill in the art would have a reasonable expectation of optimizing as switch network using the method and system of Possani, using the factorization method of daRosa, at least for the SP kernel finding step. Therefore, it would have been obvious to combine Possani with daRosa to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 6, Possani in view of daRosa teaches all of the limitations of claim 3, as noted above. Possani teaches wherein generating the single-stage transistor networks comprises generating an irredundant sum-of-products (ISOP) ... (The proposed method starts from an ISOP, and tries to combine the cubes of a function to build NSP and SP kernels, [page 192 col 2 paragraph 2 lines 1-2]; definition of ISOP is irredundant sum of products, which refers to a Boolean expression, [page 192 col 2 paragraph 1]).
Possani does not specifically teach that the ISOP is ...from a truth table.
However, daRosa teaches ...from a truth table (both network generation and network optimization start from on-set and off-set equations, see for example eq’s. (2.9) and (2.10), [page 38], eq’s. (2.11) and (2.12), [page 43], and eq’s. (2.13) and (2.14), [page 44]; the equations are ISOP based on the definition, “A prime irredundant SOP with minimum cube literal cost for function f is a prime irredundant SOP where the maximum number of literals in a single cube is minimum for function”, [page 28 paragraph 2 lines 2-4]; previous sections describe how to generate on-set and off-set equations and why they are generated from truth tables: “For a given Boolean function, the set of input vectors that produces an output value is called on-set. '1' In the same way, the set of input vectors that produces an output value '0' is called off-set”, [page 24 paragraph 2]; and “Basically, logic network can be constructed with their logic planes in a shared structure or not”, [page 37 paragraph 2 lines 1-2], but for a full understand read all of [page 37 paragraph 2]-[page 39 paragraph 1], which gives a detailed explanation of how to generate pullup and pulldown networks from on-set and off-set equations.
It would have been obvious to one skilled in the art before the effective filing date to combine Possani with daRosa because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. Possani teaches both factorization and graph-based methods, [page 191 col 2 paragraphs 2-3], but focuses mostly on graph-based methods because they find NSP arranges that factorization methods cannot, [page 191 col 2 paragraph 3 lines 5-8]. DaRosa, who is also an author on the Possani paper, provides further details on everything from factorization procedures to basics like how to generate on-set and off-set equations from truth tables in order to apply factorization procedures. A person having skill in the art would have a reasonable expectation of optimizing as switch network using the method and system of Possani, using the factorization method of daRosa, at least for the SP kernel finding step. Therefore, it would have been obvious to combine Possani with daRosa to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 14, Possani teaches A computing system, comprising: memory configured to store integrated circuit information; and one or more processors operatively coupled to the memory, the one or more processors being configured to (computer running method described in Abstract running in an Intel Core i5 at 2.8GHz with 4Gb of RAM, [page 196 col 1 paragraph 1 lines 1-4]):
Regarding the rest of claim 14, incorporating the rejection of claim 1, claim 14 is rejected for a substantially similar rationale.
With respect to claim 15, Possani in view of daRosa teaches all of the limitations of claim 14, as noted above. Possani further teaches wherein the one or more processors are further configured ... in the memory (computer running method described in Abstract running in an Intel Core i5 at 2.8GHz with 4Gb of RAM, [page 196 col 1 paragraph 1 lines 1-4]).
Possani does not teach ... to store the circuit design...
However, daRosa teaches wherein the one or more processors are further configured to store the circuit design in the memory (see circuit design methodology in Fig. 1.2, [page 18], where the caption “Digital circuit design methodology using predefined cell library” uses the word “digital” to indicate method is implemented on a computer; author describes three tools, where tools in this context refers to software running on a computer, “In this context, an academic environment composed of 3 parts was idealized by our group. The first one is a logic synthesis tool, which only performs logic manipulations over Boolean functions. This tool is called KARMA 3. The second one is an electrical synthesis tool, developed to provide transistor networks generation, manipulation and evaluation at cell level. This tool is named ELECTRO. The last one is a physical synthesis tool, proposed to implement, optimize and evaluate the layout of logic cells, [page 131 paragraph 2 lines 1-7]; because the tools are implemented in software, the circuit design including the “Spice netlist description”, [page 140 paragraph 3 line 3], would be stored in memory while being generated into an image such as figure E11, [page 141]).
It would have been obvious to one skilled in the art before the effective filing date to combine Possani with daRosa because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. In the first paragraph, Possani provides a specific teaching, suggestion, motivation for the purpose of the method, [page 191 col 1 paragraph 1 lines 1-6]. DaRosa goes into further detail explaining the bigger picture. The standard cell library is part of Technology mapping. Technology mapping is part of a larger process known as logic synthesis, which in turn is part of the process of circuit design:
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(daRosa [page 18]).
A person having skill in the art would have a reasonable expectation of building an optimized Cell Library using the method and system of Possani, which in turn can be used in the larger process that includes technology mapping as described by daRosa. Therefore, it would have been obvious to combine Possani with daRosa to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 16, incorporating the rejections of claim 2 and claim 14, claim 16 is rejected for substantially similar rationale.
With respect to claim 17, incorporating the rejections of claim 6 and claim 14, claim 17 is rejected for substantially similar rationale.
Claim(s) 7-13 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over “Efficient Transistor-Level Design of CMOS Gates” (2013-Possani) in view of “Automatic Generation and Evaluation of Transistor Networks in Different Logic Styles” (2008-daRosa) in further view of Boolean Decomposition for AIG Optimization (2017-Machado)
With respect to claim 7, Possani in view of daRosa teaches all of the limitations of claim 1, as noted above. Possani and daRosa do not teach wherein scaling the single-stage transistor networks to multi-stage transistor networks to globally optimize for factored form literals includes And-inverter graph (AIG) rewriting for the factored form literals.
However, Machado teaches wherein scaling the single-stage transistor networks to multi-stage transistor networks to globally optimize for factored form literals includes And-inverter graph (AIG) rewriting for the factored form literals (see section labeled AIG optimization, where “In this work, multi-output decomposition is used by iteratively selecting the Boolean divisor that minimizes the literals of the functions factored forms, [page 144 col 2 paragraph 4 lines 3-5]; Algorithm provided in detail in FIG. 5 and FIG. 6, where FIG. 5 shows the AIG input in line 1 and the BoolDecompose algorithm is invoked at line 8, [page 146]; and the BoolDecompose function is shown in FIG. 6, with the numLiterals defined at line 10 and checked at line 34, [page 146]; see also “The cost function to be minimized is defined as the sum of literals of all functions in factored form (numLiterals, line 10), [page 146 col 2 paragraph 4 lines 3-5]).
It would have been obvious to one skilled in the art before the effective filing date to combine Possani in view of daRosa with Machado because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. Possani in view of daRosa discloses a system and method that teaches how to perform a first pass at network optimization. Machado introduces concepts of rewriting and refactoring, which additionally applies local optimizations:
Restructuring techniques for And-Inverter Graphs (AIG), such as rewriting and refactoring, are powerful, scalable and fast, achieving highly optimized AIGs after few iterations. However, these techniques are biased by the original AIG structure and limited by single output optimizations. This paper investigates AIG optimization for area, exploring how far Boolean methods can reduce AIG nodes through local optimization.
A person having skill in the art would have a reasonable expectation of successfully further optimizing the networks produced in the system and method of Possani in view of daRosa by modifying Possani in view of daRosa with the local optimizations of Machado. Therefore, it would have been obvious to combine Possani in view of daRosa with Machado to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 8, Possani in view daRosa and Machado teach all of the limitations of claim 7, as noted above. Possani and daRosa do not teach wherein the AIG rewriting includes replacing a part of a circuit component using one or more precomputed smaller structures that are smaller than the circuit component.
However, Machado teaches wherein the AIG rewriting includes replacing a part of a circuit component using one or more precomputed smaller structures that are smaller than the circuit component (see FIG. 5 lines 10-11: new klcut = AIG network of divisors; and replace klcut by new klcut in AIG, [page 146]; all the divisors are computed previously using algorithm shown in FIG. 6, [page 146], at FIG. 5 line 8, [page 146]).
It would have been obvious to one skilled in the art before the effective filing date to combine Possani in view of daRosa with Machado because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. Possani in view of daRosa discloses a system and method that teaches how to perform a first pass at network optimization. Machado introduces concepts of rewriting and refactoring, which additionally applies local optimizations:
Restructuring techniques for And-Inverter Graphs (AIG), such as rewriting and refactoring, are powerful, scalable and fast, achieving highly optimized AIGs after few iterations. However, these techniques are biased by the original AIG structure and limited by single output optimizations. This paper investigates AIG optimization for area, exploring how far Boolean methods can reduce AIG nodes through local optimization.
A person having skill in the art would have a reasonable expectation of successfully further optimizing the networks produced in the system and method of Possani in view of daRosa by modifying Possani in view of daRosa with the local optimizations of Machado. Therefore, it would have been obvious to combine Possani in view of daRosa with Machado to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 9, Possani in view of daRosa teaches all of the limitations of claim 1, as noted above. Possani and daRosa do not teach wherein the AIG uses size as a cost function to limit a number of AIG nodes.
However, Machado teaches wherein the AIG uses size as a cost function to limit a number of AIG nodes (This paper studies technology-independent transformations that reduce the AIG size by exploring the use of Boolean decomposition, [page 143 col 2 paragraph 2 lines 1-3]; where the specific line in the algorithm is FIG. 5 line 9: “if size of divisors < size of klcut then”, [page 146];).
It would have been obvious to one skilled in the art before the effective filing date to combine Possani in view of daRosa with Machado because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. Possani in view of daRosa discloses a system and method that teaches how to perform a first pass at network optimization. Machado introduces concepts of rewriting and refactoring, which additionally applies local optimizations:
Restructuring techniques for And-Inverter Graphs (AIG), such as rewriting and refactoring, are powerful, scalable and fast, achieving highly optimized AIGs after few iterations. However, these techniques are biased by the original AIG structure and limited by single output optimizations. This paper investigates AIG optimization for area, exploring how far Boolean methods can reduce AIG nodes through local optimization.
A person having skill in the art would have a reasonable expectation of successfully further optimizing the networks produced in the system and method of Possani in view of daRosa by modifying Possani in view of daRosa with the local optimizations of Machado. Therefore, it would have been obvious to combine Possani in view of daRosa with Machado to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 10, Possani in view of daRosa teaches all of the limitations of claim 1, as noted above. Possani and daRosa do not teach , wherein scaling the single-stage transistor networks to multi-stage transistor networks to globally optimize for factored form literals includes And-inverter graph (AIG) resubstitution for the factored form literals.
However, Machado teaches wherein scaling the single-stage transistor networks to multi-stage transistor networks to globally optimize for factored form literals includes And-inverter graph (AIG) resubstitution for the factored form literals (see claim interpretation section, and note the abstract: This paper investigates AIG optimization for area, exploring how far Boolean methods can reduce AIG nodes through local optimization. Boolean division is applied for multi-output functions using two-literal divisors and Boolean decomposition is introduced as a method for AIG optimization, [Abstract] lines 5-10; actual method is described on page 144. Eq. (1) is divided by the divisor y = a.b, and because of the DC-set (i.e., don’t care set), you can substitute y for all of the first terms to get eq. (2).
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[page 144 col 1 paragraph 4]; see section labeled AIG optimization, where “In this work, multi-output decomposition is used by iteratively selecting the Boolean divisor that minimizes the literals of the functions factored forms, [page 144 col 2 paragraph 4 lines 3-5]; see also “The cost function to be minimized is defined as the sum of literals of all functions in factored form (numLiterals, line 10), [page 146 col 2 paragraph 4 lines 3-5]; the last step in the process is AIG rewriting if improved, which is a form of resubstitution as shown in FIG. 2, [page 144]).
It would have been obvious to one skilled in the art before the effective filing date to combine Possani in view of daRosa with Machado because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. Possani in view of daRosa discloses a system and method that teaches how to perform a first pass at network optimization. Machado introduces concepts of rewriting and refactoring, which additionally applies local optimizations:
Restructuring techniques for And-Inverter Graphs (AIG), such as rewriting and refactoring, are powerful, scalable and fast, achieving highly optimized AIGs after few iterations. However, these techniques are biased by the original AIG structure and limited by single output optimizations. This paper investigates AIG optimization for area, exploring how far Boolean methods can reduce AIG nodes through local optimization.
A person having skill in the art would have a reasonable expectation of successfully further optimizing the networks produced in the system and method of Possani in view of daRosa by modifying Possani in view of daRosa with the local optimizations of Machado. Therefore, it would have been obvious to combine Possani in view of daRosa with Machado to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 11, Possani in view of daRosa teaches all of the limitations of claim 1, as noted above. Possani and daRosa do not teach wherein scaling the single-stage transistor networks to multi-stage transistor networks to globally optimize for factored form literals includes performing refactoring.
However, Machado teaches wherein scaling the single-stage transistor networks to multi-stage transistor networks to globally optimize for factored form literals includes performing refactoring (see section labeled AIG optimization, where “In this work, multi-output decomposition is used by iteratively selecting the Boolean divisor that minimizes the literals of the functions factored forms, [page 144 col 2 paragraph 4 lines 3-5]; see also “The cost function to be minimized is defined as the sum of literals of all functions in factored form (numLiterals, line 10), [page 146 col 2 paragraph 4 lines 3-5]; the last step in the process is AIG rewriting if improved as shown in FIG. 2, [page 144]; rewriting and refactoring are related, see [Abstract], where the selected result is “refactorization” because considered in factored form: In this work, multi-output decomposition is used by iteratively selecting the Boolean divisor that minimizes the literals of the functions factored forms, [2], [page 144 col 2 paragraph 4 lines 3-5]).
It would have been obvious to one skilled in the art before the effective filing date to combine Possani in view of daRosa with Machado because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. Possani in view of daRosa discloses a system and method that teaches how to perform a first pass at network optimization. Machado introduces concepts of rewriting and refactoring, which additionally applies local optimizations:
Restructuring techniques for And-Inverter Graphs (AIG), such as rewriting and refactoring, are powerful, scalable and fast, achieving highly optimized AIGs after few iterations. However, these techniques are biased by the original AIG structure and limited by single output optimizations. This paper investigates AIG optimization for area, exploring how far Boolean methods can reduce AIG nodes through local optimization.
A person having skill in the art would have a reasonable expectation of successfully further optimizing the networks produced in the system and method of Possani in view of daRosa by modifying Possani in view of daRosa with the local optimizations of Machado. Therefore, it would have been obvious to combine Possani in view of daRosa with Machado to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 12, Possani in view of daRosa teaches all of the limitations of claim 11, as noted above. Possani and daRosa do not teach wherein refactoring includes rewriting maximum fanout-free cones (MFFCs) with a new factored implementation when a number of gates decreases.
However, Machado teaches wherein refactoring includes rewriting maximum fanout-free cones (MFFCs) with a new factored implementation when a number of gates decreases (the last step in the process is AIG rewriting if improved as shown in FIG. 2, [page 144]; rewriting and refactoring are related, see [Abstract], where the selected result is “refactorization” because considered in factored form: In this work, multi-output decomposition is used by iteratively selecting the Boolean divisor that minimizes the literals of the functions factored forms, [2], [page 144 col 2 paragraph 4 lines 3-5]; AIG rewriting and refactoring perform local transformations, extracting the local context with K-cuts [16], windows or maximum fanout-free cones (MFFCs), [page 143 col 1 paragraph 3 lines 1-3]).
It would have been obvious to one skilled in the art before the effective filing date to combine Possani in view of daRosa and Machado with this teaching of Machado because this simple substitution of one known element for another to obtain predictable results. Possani in view of daRosa discloses a system and method that teaches how to perform a first pass at network optimization. Machado introduces concepts of rewriting and refactoring, which additionally applies local optimizations, (see Machado [Abstract]). To perform local transformations local portions of the AIG need to be defined, and Machado provides a description of three methods to extract local contexts in order to perform local optimizations:
AIG rewriting and refactoring perform local transformations, extracting the local context with K-cuts [16], windows or maximum fanout-free cones (MFFCs).
(Machado [page 143 col 1 paragraph 2 lines 1-3]).
In the main embodiment, Machado teaches extracting KL-cuts as shown in Fig. 2, (Machado [page 144]), but the reference clearly contemplates that the other methods of local context extraction are possible. The MFFC method is well known in the art, as is noted by citing reference [11], (Machado [page 143 col 2 paragraph 6]). One of ordinary skill in the art could have substituted the MFFC method for the KL-cut method for extracting local contexts, and the results of the substitution would have been predictable. Therefore, it would have been obvious to combine Possani in view of daRosa and Machado with the MFFC method disclosed in Machado to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 13, Possani in view of daRosa teaches all of the limitations of claim 11, as noted above. Possani and daRosa do not teach wherein scaling the single-stage transistor networks to multi-stage transistor networks to globally optimize for factored form literals includes performing technology mapping driven by the factored form literals.
However, Machado teaches wherein scaling the single-stage transistor networks to multi-stage transistor networks to globally optimize for factored form literals includes performing technology mapping driven by the factored form literals (In this work, multi-output decomposition is used by iteratively selecting the Boolean divisor that minimizes the literals of the functions factored forms, [page 144 col 2 paragraph 4 lines 3-5]; Table 4 shows technology mapping performed for FPGAs and standard cells using the AIGs from Table 3. Area reduction was observed simply by changing the input with smaller AIGs, [page 148 col 1 paragraph 2 lines 1-4]; see also Table 4, [page 148]).
It would have been obvious to one skilled in the art before the effective filing date to combine Possani in view of daRosa with Machado because a teaching, suggestion, or motivation in the prior art would have led one skilled in the art to combine prior art teaching to arrive at the claimed invention. Possani in view of daRosa discloses a system and method that teaches how to perform a first pass at network optimization. DaRosa teaches technology mapping, but not in the scaling step as described in the claim. Machado introduces concepts of rewriting and refactoring, which additionally applies local optimizations. These optimizations are shown to improve the AIG in table 3, but the values in table 3 cannot show things like improving area, which requires the last step of technology mapping, which is why table 4 shows the results of technology mapping. A person having skill in the art would have a reasonable expectation of successfully further optimizing the networks produced in the system and method of Possani in view of daRosa by modifying Possani in view of daRosa with the local optimizations of Machado. Therefore, it would have been obvious to combine Possani in view of daRosa with Machado to a person having ordinary skill in the art, and this claim is rejected under 35 U.S.C. 103.
With respect to claim 18, incorporating the rejections of claim 7 and claim 14, claim 18 is rejected for substantially similar rationale.
With respect to claim 19, incorporating the rejections of claim 10 and claim 14, claim 19 is rejected for substantially similar rationale.
With respect to claim 20, incorporating the rejections of claim 11 and claim 14, claim 20 is rejected for substantially similar rationale.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20110050281 A1 (Moe) - A method and system are described to group logic terms at a higher level of abstraction than that found using standard cells to implement the logic functions using a reduced number of transistors, and to reduce the total number of unique geometry patterns needed to create the integrated circuit implementation. By grouping the logic functions in terms of a larger number of literals (logic variable inputs), the functions can be implemented in terms of a number of transistors that is often less and no more than equal to that which is required for implementing the same function with a number of logic primitives, or simpler standard logic cells. The optimized transistor level designs are further optimized and physically constructed to reduce the total number of unique geometry patterns required to implement the integrated circuit, [Abstract]; see also FIG. 1.
“Logic synthesis in a nutshell” (2010-Jiang) - Logic synthesis is the process that takes place in the transition from the register-transfer level to the transistor level. It is a highly automated procedure bridging the gap between high-level synthesis and physical design automation. Given a digital design at the register-transfer level, logic synthesis transforms it into a gate-level or transistor-level implementation. The highly engineered process explores different ways of implementing a logic function optimal with respect to some desired design constraints. The physical positions and interconnections of the gate layouts are then further determined at the time of physical design, [page 300].
“Transistor Count Reduction by Gate Merging” (2019-de Oliveira Conceicao) - If the new gates presented in Figure 6 replaces the circuit parts previously shown in Figure 5, it results in the circuit shown in right side of Figure 4, where gates marked in yellow are the new SCCGs, and the pink ones are new inverters needed to guarantee the logic equivalence, [page 2180 col 1 paragraph 2];
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[page 2179];
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[page 2180].
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL MILLER whose telephone number is (408) 918-7548. The examiner can normally be reached on Monday-Friday from 11am to 5pm (PT). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang, can be reached at telephone number 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.M./Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
