Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-14, 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Goodman et al., US Patent Application Publication 2024/0095065 (hereinafter Goodman) in view of Tran, US Patent Application Publication 2021/0389979 (hereinafter Tran).
Regarding claim 1, Goodman teaches:
A processor comprising: a processing core having at least one execution resource comprising: a thread arbiter (see e.g. para. [0024-5], scheduling circuitry); a plurality of execution pipeline hardware circuitry comprising a math execution pipeline and an integer execution pipeline to share resources of the thread arbiter (see e.g. fig. 2, para. [0024-5], [0059], floating-point and integer execution pipelines share resources of the scheduling circuitry); arbitration hardware circuitry to determine whether the math execution pipeline is available for loading math operand data of a math instruction, the math operand data received from the thread arbiter (see e.g. para. [0128], instructions and their operand data are arbitrated based on resource availability); wherein the integer execution pipeline is to receive integer operand data for an integer instruction, the integer operand data received from the thread arbiter (see e.g. para. [0036], [0057-8], schedulers manage instruction and data flow); and wherein the math execution pipeline is to receive, responsive to the math execution pipeline becoming available, the math operand data (see e.g. para. [0036], [0057-8], [0128], instructions and their operands are sent to a corresponding pipeline based on resource availability).
Goodman fails to explicitly teach a math instruction staging buffer to store the math operand data responsive to the math execution pipeline not being available; the integer operand data received while bypassing the math operand data in the math instruction staging buffer; and receiving the math operand data from the math instruction staging buffer.
Tran teaches using a staging buffer (execution queue) to store instructions and their operands when a pipeline is unavailable for an instruction due to a data dependency or resource hazard, and receiving the instruction data from the execution queue (see e.g. para. [0015-9]). Tran also teaches that another instruction is allowed to bypass the execution queue (see e.g. para. [0015-6]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Goodman and Tran to include a math instruction staging buffer to store the math operand data responsive to the math execution pipeline not being available; the integer operand data received while bypassing the math operand data in the math instruction staging buffer; and receiving the math operand data from the math instruction staging buffer. This would have provided advantages such as discussed by Tran to allow ready instructions to proceed without needing to be queued to reduce unnecessary pipelines stalls (see e.g. para. [0010]).
Regarding claim 2, Goodman in view of Tran teaches or suggests:
The processor of claim 1, wherein the math instruction staging buffer comprises a first in first out (FIFO) queue data structure (see e.g. Tran para. [0021]).
Regarding claim 3, Goodman in view of Tran teaches or suggests:
The processor of claim 1, wherein the math instruction staging buffer is configured to store math operand data for more than one math instruction (see e.g. Tran fig. 4).
Regarding claim 4, Goodman in view of Tran teaches or suggests:
The processor of claim 1, wherein the math operand data comprises a plurality of phases of math operand data, and wherein the arbitration hardware circuitry is to load a first phase of the plurality of phases of the math operand data directly to the math execution pipeline and a remainder of the plurality of phases of the math operand data to the math instruction staging buffer (see e.g. Tran fig. 4, some operands are sent directly rather than from the execution queue).
Regarding claim 5, Goodman in view of Tran teaches or suggests:
The processor of claim 1, wherein the math instruction staging buffer is to store the math operand data to enable the thread arbiter to continue to load the integer operand data to the integer execution pipeline (see e.g. Tran para. [0015-9]).
Regarding claim 7, Goodman in view of Tran teaches or suggests:
The processor of claim 1, wherein the integer execution pipeline and the math execution pipeline comprise arithmetic logic units (ALUs) that comprises a plurality of adders and shifters (see e.g. Goodman para. [0025], Tran para. [0019]).
Regarding claim 8, Goodman in view of Tran teaches or suggests:
The processor of claim 1, wherein the processor comprises a graphics processing unit (GPU) (see e.g. Goodman para. [0038]).
Regarding claim 9, Goodman in view of Tran teaches or suggests:
The processor of claim 1, wherein the processor is at least one of a single instruction multiple data (SIMD) machine or a single instruction multiple thread (SIMT) machine (see e.g. Goodman para. [0036]).
Claims 10-14 are rejected for reasons corresponding to those given above for claims 1-5.
Claims 16-20 are rejected for reasons corresponding to those given above for claims 1-5.
Claims 6, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Goodman in view of Tran, further in view of Liu et al., US Patent Application Publication 2008/0109611 (hereinafter Liu).
Regarding claim 6, Goodman in view of Tran teaches or suggests:
The processor of claim 1.
Goodman in view of Tran fails to explicitly teach wherein the math instruction performs an operation comprising at least one of a sine operation, a cosine operation, a logarithm operation, a tangent operation, or an exponent operation.
Liu teaches buffering instructions and data for execution pipelines executing math instructions including logarithm, sine, cosine, and power function operations (see e.g. para. [0066]).
Before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to combine the teachings of Goodman, Tran, and Liu such that the math instruction performs an operation comprising at least one of a sine operation, a cosine operation, a logarithm operation, a tangent operation, or an exponent operation. This would have provided greater flexibility of instruction programming options to improve specific calculations such as for graphics processing in Liu (see e.g. para. [0032]).
Claim 15 is rejected for reasons corresponding to those given above for claim 6.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M LINDLOF whose telephone number is (571)270-1024. The examiner can normally be reached Mon-Tue 8:30-5:00.
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/JOHN M LINDLOF/Primary Examiner, Art Unit 2183
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