Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1,3,5-9,11,13-17,19 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claim(s) recite(s) mental processes – concepts performed in the human mind.
Regarding claim 1, the claim recites concepts performed in the human mind.
The limitations ‘determining fault classes to which at least one piece of to-be-processed fault information respectively belongs based on a pre-configured first corresponding relationship stored in a first configuration register and between a fault identifier and the fault class, wherein the to-be-processed fault information comprises a fault identifier of a to-be-processed fault, and wherein the fault identifier of the to-be-processed fault is carried in the fault information reported by a security module, or is determined by using a connection interface between the security module and the fault processing apparatus; arbitrating the to-be-processed fault information included at all fault classes respectively, to determine target to-be-processed fault information respectively corresponding to all the fault classes, wherein the target to-be-processed fault information represents the to-be-processed fault information that is arbitrated from a plurality of pieces of to- be-processed fault information and that currently needs to be processed’ are mental processes -concepts performed in the human mind by observation, evaluation, judgment, and/or opinion, as well as organizing.
Step 2A: Prong two
This judicial exception is not integrated into a practical application because the limitation ‘concurrently performing corresponding fault processing on the faults at a plurality of the fault classes based on all the target to-be-processed fault information’ is simply adding insignificant extra-solution activity to the judicial exception (MPEP 2106.05(g)) by performing a generic fault processing post-solution activity as indicated by the specification. The limitation ‘in response to that authorization enabling information preconfigured in a third configuration register is detected by detecting a state of a register which is used to configure the authorization enabling information, wherein the fault processing at least includes determining that the faults need to be processed by a processor based on the to-be-processed fault information and transmitting an interrupt signal to the processor’ is simply adding insignificant extra-solution activity to the judicial exception (MPEP 2106.05(g)) by data gathering.
Step 2B
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the limitation ‘by a fault processing apparatus of a chip; by the fault processing apparatus of a chip’ are directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 3, the limitations ‘wherein the performing corresponding fault processing based on all the target to-be-processed fault information comprises: determining processing types respectively corresponding to all the target to-be-processed fault information based on a pre-configured second corresponding relationship stored in a second configuration register and between the fault identifier and the processing type’ is a mental process - concept performed in the human mind by observation, evaluation, judgment, and/or opinion, as well as organizing; and ‘outputting fault processing signals respectively corresponding to all the target to-be-processed fault information based on the processing types respectively corresponding to all the target to-be-processed fault information’ is simply adding insignificant extra-solution activity to the judicial exception (MPEP 2106.05(g)) by performing a generic fault processing post-solution activity as indicated by the specification. The limitation ‘by the fault processing apparatus of the chip’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 5, the limitations ‘storing processing timestamps of the target to-be-processed fault information respectively corresponding to all the fault classes into a time register’ are simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception (MPEP 2106.05(d)) II. iv.- Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93; and/or ‘encoding the target to-be-processed fault information in a fourth storage which has been arbitrated and respectively corresponding to all the fault classes to obtain a fault code of the target to-be-processed fault information respectively corresponding to all the fault classes into a fault code register’ are mere instructions to implement an abstract idea or other exception on a computer and in this case generic computer components (MPEP 2106.05(f)); and ‘storing the fault code of the target to-be-processed fault information respectively corresponding to all the fault classes’ are simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception (MPEP 2106.05(d)) II. iv.- Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93. The limitation ‘by the fault processing apparatus of the chip’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 6, the limitation ‘wherein the arbitrating the to-be-processed fault information included at all fault classes respectively, to determine target to-be-processed fault information respectively corresponding to all the fault classes comprises: for any fault class, arbitrating the to-be-processed fault information at this fault class based on a round robin algorithm depending on the authorization enabling information in a third configuration register, to determine the target to-be-processed fault information corresponding to this fault class’ are mental processes - concepts performed in the human mind by observation, evaluation, judgment, and/or opinion, as well as organizing. The limitation ‘by the fault processing apparatus of the chip’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 7, the limitation ‘for any fault class, recording a round-robin position of the target to-be-processed fault information at this fault class in the to-be-processed fault information at this fault class in a round-robin position register’ is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception (MPEP 2106.05(d)) II. iv.- Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93.
The limitation ‘by the fault processing apparatus of the chip’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 8, the limitations ‘after the arbitrating the to-be-processed fault information included at all fault classes respectively, to determine target to-be-processed fault information respectively corresponding to all the fault classes, the method further comprises: recording a quantity of processing times for each piece of target to-be-processed fault information in a fault quantity register’ is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception (MPEP 2106.05(d)) II. iv.- Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93; and ‘the method further comprises: for any target to-be-processed fault information, receiving the quantity of processing times corresponding to the target to-be-processed fault information from the fault quantity register’ is simply adding insignificant extra-solution activity to the judicial exception (MPEP 2106.05(g)) by data gathering, and ‘in response to that the quantity of processing times corresponding to the target to-be-processed fault information and extracted from the fault quantity register reaches a preset threshold of times, updating the fault class of the target to-be-processed fault information to an upper fault class of the current fault class, so that the target to-be-processed fault information serves as the to-be-processed fault information at the upper fault class to be arbitrated’ are mental processes - concepts performed in the human mind by observation, evaluation, judgment, and/or opinion, as well as organizing. The limitation ‘by the fault processing apparatus of the chip; by the fault processing apparatus of the chip’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 9, with the exception of the limitation ‘A computer readable storage medium, wherein the storage medium stores a computer program, and the computer program is used for implementing a fault processing method’, the claim recites concepts performed in the human mind.
The limitations ‘determining fault classes to which at least one piece of to-be-processed fault information respectively belongs based on a pre-configured first corresponding relationship in a first configuration register and between a fault identifier and the fault class, wherein the to-be-processed fault information comprises a fault identifier of a to-be-processed fault, and wherein the fault identifier of the to-be-processed fault is carried in the fault information reported by a security module, or is determined by using a connection interface between the security module and the fault processing apparatus; arbitrating the to-be-processed fault information included at all fault classes respectively, to determine target to-be-processed fault information respectively corresponding to all the fault classes, wherein the target to-be-processed fault information represents the to-be-processed fault information that is arbitrated from a plurality of pieces of to- be-processed fault information and that currently needs to be processed’ are mental processes -concepts performed in the human mind by observation, evaluation, judgment, and/or opinion, as well as organizing.
Step 2A: Prong two
This judicial exception is not integrated into a practical application because the limitation ‘concurrently performing corresponding fault processing based on all the target to-be-processed fault information, wherein the fault processing at least includes determining that the faults need to be processed by a processor based on the to-be-processed fault information and transmitting an interrupt signal to the processor’ is simply adding insignificant extra-solution activity to the judicial exception (MPEP 2106.05(g)) by performing a generic fault processing post-solution activity as indicated by the specification. The limitation ‘in response to that authorization enabling information preconfigured in a third configuration register is detected by detecting a state of a register which is used to configure the authorization enabling information’ is simply adding insignificant extra-solution activity to the judicial exception (MPEP 2106.05(g)) by data gathering.
Step 2B
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the limitation ‘A computer readable storage medium, wherein the storage medium stores a computer program, and the computer program is used for implementing a fault processing method; by the fault processing apparatus of the chip’ are directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 11, the limitations ‘wherein the performing corresponding fault processing based on all the target to-be-processed fault information comprises: determining processing types respectively corresponding to all the target to-be-processed fault information based on a pre-configured second corresponding relationship in a third storage and between the fault identifier and the processing type’ is a mental process - concept performed in the human mind by observation, evaluation, judgment, and/or opinion, as well as organizing; and ‘outputting fault processing signals respectively corresponding to all the target to-be-processed fault information based on the processing types respectively corresponding to all the target to-be-processed fault information’ is simply adding insignificant extra-solution activity to the judicial exception (MPEP 2106.05(g)) by performing a generic fault processing post-solution activity as indicated by the specification. The limitation ‘by the processor’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 13, the limitations ‘storing processing timestamps of the target to-be-processed fault information respectively corresponding to all the fault classes’ are simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception (MPEP 2106.05(d)) II. iv.- Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93; and/or ‘encoding the target to-be-processed fault information in a forth storage which has been arbitrated and respectively corresponding to all the fault classes to obtain a fault code of the target to-be-processed fault information respectively corresponding to all the fault classes’ are mere instructions to implement an abstract idea or other exception on a computer and in this case generic computer components (MPEP 2106.05(f)); and ‘storing the fault code of the target to-be-processed fault information respectively corresponding to all the fault classes’ are simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception (MPEP 2106.05(d)) II. iv.- Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93. The limitation ‘’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 14, the limitation ‘wherein the arbitrating the to-be-processed fault information included at all fault classes respectively, to determine target to-be-processed fault information respectively corresponding to all the fault classes comprises: for any fault class, arbitrating the to-be-processed fault information at this fault class based on a round robin algorithm depending on the authorization enabling information in a third configuration register, to determine the target to-be-processed fault information corresponding to this fault class’ are mental processes - concepts performed in the human mind by observation, evaluation, judgment, and/or opinion, as well as organizing. The limitation ‘by the fault processing apparatus of the chip’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 15, the limitation ‘for any fault class, recording a round-robin position of the target to-be-processed fault information at this fault class in the to-be-processed fault information at this fault class in a round-robin position register’ are simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception (MPEP 2106.05(d)) II. iv.- Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93.
The limitation ‘by the fault processing apparatus of the chip’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 16, the limitations ‘after the arbitrating the to-be-processed fault information included at all fault classes respectively, to determine target to-be-processed fault information respectively corresponding to all the fault classes, the method further comprises: recording a quantity of processing times for each piece of target to-be-processed fault information ius simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception (MPEP 2106.05(d)) II. iv.- Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93; and ‘the method further comprises: for any target to-be-processed fault information, in response to that the quantity of processing times corresponding to the target to-be-processed fault information reaches a preset threshold of times, updating the fault class of the target to-be-processed fault information to an upper fault class of the current fault class, so that the target to-be-processed fault information serves as the to-be-processed fault information at the upper fault class to be arbitrated’ are mental processes - concepts performed in the human mind by observation, evaluation, judgment, and/or opinion, as well as organizing. The limitation ‘by the fault processing apparatus of the chip’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 17, with the exception of the limitation ‘a fault processing apparatus of the chip; and a memory, configured to store processor-executable instructions, wherein the processor is configured to read the executable instructions from the memory, and execute the instructions to implement a fault processing method’, the claim recites concepts performed in the human mind.
The limitations ‘determining fault classes to which at least one piece of to-be-processed fault information respectively belongs based on a pre-configured first corresponding relationship in a first configuration register and between a fault identifier and the fault class, wherein the to-be-processed fault information comprises a fault identifier of a to-be-processed fault, and wherein the fault identifier of the to-be-processed fault is carried in the fault information reported by a security module, or is determined by using a connection interface between the security module and the fault processing apparatus; arbitrating the to-be-processed fault information included at all fault classes respectively, to determine target to-be-processed fault information respectively corresponding to all the fault classes, wherein the target to-be-processed fault information represents the to-be-processed fault information that is arbitrated from a plurality of pieces of to- be-processed fault information and that currently needs to be processed’ are mental processes -concepts performed in the human mind by observation, evaluation, judgment, and/or opinion, as well as organizing.
Step 2A: Prong two
This judicial exception is not integrated into a practical application because the limitation ‘concurrently performing corresponding fault processing on the faults at a plurality of classes based on all the target to-be-processed fault information, wherein the fault processing at least includes determining that the faults need to be processed by a processor based on the to-be-processed fault information and transmitting an interrupt signal to the processor’ is simply adding insignificant extra-solution activity to the judicial exception (MPEP 2106.05(g)) by performing a generic fault processing post-solution activity as indicated by the specification. The limitation ‘in response to that authorization enabling information preconfigured in a third configuration register is detected by detecting a state of a register which is used to configure the authorization enabling information’ is simply adding insignificant extra-solution activity to the judicial exception (MPEP 2106.05(g)) by data gathering.
Step 2B
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the limitation ‘a fault processing apparatus of the chip; and a memory, configured to store processor-executable instructions, wherein the processor is configured to read the executable instructions from the memory, and execute the instructions to implement a fault processing method; by the fault processing apparatus of the chip’ are directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 19, the limitations ‘wherein the performing corresponding fault processing based on all the target to-be-processed fault information comprises: determining processing types respectively corresponding to all the target to-be-processed fault information based on a pre-configured second corresponding relationship stored in a second configuration register and between the fault identifier and the processing type’ is a mental process - concept performed in the human mind by observation, evaluation, judgment, and/or opinion, as well as organizing; and ‘outputting fault processing signals respectively corresponding to all the target to-be-processed fault information based on the processing types respectively corresponding to all the target to-be-processed fault information’ is simply adding insignificant extra-solution activity to the judicial exception (MPEP 2106.05(g)) by performing a generic fault processing post-solution activity as indicated by the specification. The limitation ‘by the processor’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Claim Objections
Claim 19 is objected to because of the following informalities: ‘by the processor’ should be: ‘the fault processing apparatus of the chip’. Appropriate correction is required.
Response to Arguments
Applicant's arguments and amendments filed 11/26/2025 have been fully considered. Concerning the 101 abstract idea rejection, the determining is based on information that has been stored in memory and which has been gathered such that it becomes a mental process to determine the relationship. A computer is used as a tool to gather information. .The claims are generally tied to receiving information from a security module, which is data gathering. The intent to tie the limitations to interrupt storms or starving to death due to lack of responses needs to be explicitly stated in the claims concerning how this is supposed to occur.
The added limitations have been rejected and do not overcome the 101 abstract idea rejection. The added limitation is still viewed as being part of data gathering. Concerning the arguments of claims 5,13, please the above rejection. Concerning the arguments of claims 6,14, the claim still discloses mental processes and generically storing information. Concerning the arguments of claims 7,15, please see the above rejection. Concerning the arguments of claims 8,16, the claim still discloses mental processes and generically storing information.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Yolanda L Wilson/Primary Examiner, Art Unit 2113