Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1,3,5-9,11,13-17,19,21-26 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claim(s) recite(s) mental processes – concepts performed in the human mind.
Regarding claim 1, the claim recites concepts performed in the human mind.
The limitations ‘determining fault classes to which at least one piece of to-be-processed fault information respectively belongs based on a pre-configured first corresponding relationship stored in a first configuration register and between a fault identifier and the fault class, wherein the to-be-processed fault information comprises a fault identifier of a to-be-processed fault; in response to that the authorization enabling information being preconfigured in the corresponding third configuration register, arbitrating the to-be-processed fault information included at the fault class, to determine target to-be-processed fault information corresponding to the fault class, wherein the target to-be-processed fault information represents the to-be-processed fault information that is arbitrated from a plurality of pieces of to- be-processed fault information and that currently needs to be processed’ are mental processes -concepts performed in the human mind by observation, evaluation, judgment, and/or opinion, as well as organizing.
Step 2A: Prong two
This judicial exception is not integrated into a practical application because the limitation ‘concurrently performing corresponding fault processing on the faults at a plurality of the fault classes based on all the target to-be-processed fault information’ is simply adding insignificant extra-solution activity to the judicial exception (MPEP 2106.05(g)) by performing a generic fault processing post-solution activity as indicated by the specification.
Step 2B
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the limitation ‘by a fault classification module a fault processing apparatus of a chip; transmitting, by the fault classification module based on the fault classes, the at least one piece of to-be-processed fault information to arbiters of a fault arbitration module of the fault processing apparatus of the chip, wherein each of the arbiters corresponds to one of the fault classes and one of a plurality of third configuration registers of the fault processing apparatus of the chip; for each of the fault classes, determining, by a corresponding one of the arbiters of the fault arbitration module, whether authorization enabling information is preconfigured in a corresponding one of the plurality of third configuration registers; for each of the fault classes; by a corresponding one of the arbiters of the fault arbitration module; by the corresponding arbiter of the fault arbitration module’ are directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 3, the limitations ‘wherein the performing corresponding fault processing based on all the target to-be-processed fault information comprises: determining processing types respectively corresponding to all the target to-be-processed fault information based on a pre-configured second corresponding relationship stored in a second configuration register and between the fault identifier and the processing type’ is a mental process - concept performed in the human mind by observation, evaluation, judgment, and/or opinion, as well as organizing; and ‘outputting fault processing signals respectively corresponding to all the target to-be-processed fault information based on the processing types respectively corresponding to all the target to-be-processed fault information’ is simply adding insignificant extra-solution activity to the judicial exception (MPEP 2106.05(g)) by performing a generic fault processing post-solution activity as indicated by the specification. The limitation ‘by the fault processing apparatus of the chip’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 5, the limitations ‘storing processing timestamps of the target to-be-processed fault information respectively corresponding to all the fault classes into a time register’ are simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception (MPEP 2106.05(d)) II. iv.- Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93; and/or ‘encoding the target to-be-processed fault information in a fourth storage which has been arbitrated and respectively corresponding to all the fault classes to obtain a fault code of the target to-be-processed fault information respectively corresponding to all the fault classes into a fault code register’ are mere instructions to implement an abstract idea or other exception on a computer and in this case generic computer components (MPEP 2106.05(f)); and ‘storing the fault code of the target to-be-processed fault information respectively corresponding to all the fault classes’ are simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception (MPEP 2106.05(d)) II. iv.- Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93. The limitation ‘by the fault processing apparatus of the chip’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 6, the limitation ‘wherein for each of the fault classes, arbitrating the to-be-processed fault information included at the fault class, to determine target to-be-processed fault information corresponding to the fault class comprises: for each fault class, arbitrating the to-be-processed fault information at this fault class based on a round robin algorithm depending on the authorization enabling information in a third configuration register, to determine the target to-be-processed fault information corresponding to this fault class’ are mental processes - concepts performed in the human mind by observation, evaluation, judgment, and/or opinion, as well as organizing. The limitation ‘by the fault processing apparatus of the chip’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 7, the limitation ‘for any fault class, recording a round-robin position of the target to-be-processed fault information at this fault class in the to-be-processed fault information at this fault class in a round-robin position register’ is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception (MPEP 2106.05(d)) II. iv.- Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93.
The limitation ‘by the fault processing apparatus of the chip’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 8, the limitations ‘after the arbitrating the to-be-processed fault information included at the fault class, to determine target to-be-processed fault information corresponding to all the fault classes, the method further comprises: recording a quantity of processing times for each piece of target to-be-processed fault information in a fault quantity register’ is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception (MPEP 2106.05(d)) II. iv.- Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93; and ‘the method further comprises: for any target to-be-processed fault information, receiving the quantity of processing times corresponding to the target to-be-processed fault information from the fault quantity register’ is simply adding insignificant extra-solution activity to the judicial exception (MPEP 2106.05(g)) by data gathering, and ‘in response to the quantity of processing times corresponding to the target to-be-processed fault information and extracted from the fault quantity register reaching a preset threshold of times, updating the fault class of the target to-be-processed fault information to an upper fault class of the current fault class, so that the target to-be-processed fault information serves as the to-be-processed fault information at the upper fault class to be arbitrated’ are mental processes - concepts performed in the human mind by observation, evaluation, judgment, and/or opinion, as well as organizing. The limitation ‘by the fault processing apparatus of the chip; by the fault processing apparatus of the chip’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 9, with the exception of the limitation ‘A computer readable storage medium, wherein the storage medium stores a computer program, and the computer program is used for implementing a fault processing method’, the claim recites concepts performed in the human mind.
The limitations ‘determining fault classes to which at least one piece of to-be-processed fault information respectively belongs based on a pre-configured first corresponding relationship stored in a first configuration register and between a fault identifier and the fault class, wherein the to-be-processed fault information comprises a fault identifier of a to-be-processed fault; in response to that the authorization enabling information being preconfigured in the corresponding third configuration register, arbitrating the to-be-processed fault information included at the fault class, to determine target to-be-processed fault information corresponding to the fault class, wherein the target to-be-processed fault information represents the to-be-processed fault information that is arbitrated from a plurality of pieces of to- be-processed fault information and that currently needs to be processed’ are mental processes -concepts performed in the human mind by observation, evaluation, judgment, and/or opinion, as well as organizing.
Step 2A: Prong two
This judicial exception is not integrated into a practical application because the limitation ‘concurrently performing corresponding fault processing on the faults at a plurality of the fault classes based on all the target to-be-processed fault information’ is simply adding insignificant extra-solution activity to the judicial exception (MPEP 2106.05(g)) by performing a generic fault processing post-solution activity as indicated by the specification.
Step 2B
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the limitation ‘A computer readable storage medium, wherein the storage medium stores a computer program, and the computer program is used for implementing a fault processing method; by a fault classification module a fault processing apparatus of a chip; transmitting, by the fault classification module based on the fault classes, the at least one piece of to-be-processed fault information to arbiters of a fault arbitration module of the fault processing apparatus of the chip, wherein each of the arbiters corresponds to one of the fault classes and one of a plurality of third configuration registers of the fault processing apparatus of the chip; for each of the fault classes, determining, by a corresponding one of the arbiters of the fault arbitration module, whether authorization enabling information is preconfigured in a corresponding one of the plurality of third configuration registers; for each of the fault classes; by a corresponding one of the arbiters of the fault arbitration module; by the corresponding arbiter of the fault arbitration module’ are directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 11, the limitations ‘wherein the performing corresponding fault processing based on all the target to-be-processed fault information comprises: determining processing types respectively corresponding to all the target to-be-processed fault information based on a pre-configured second corresponding relationship in a third storage and between the fault identifier and the processing type’ is a mental process - concept performed in the human mind by observation, evaluation, judgment, and/or opinion, as well as organizing; and ‘outputting fault processing signals respectively corresponding to all the target to-be-processed fault information based on the processing types respectively corresponding to all the target to-be-processed fault information’ is simply adding insignificant extra-solution activity to the judicial exception (MPEP 2106.05(g)) by performing a generic fault processing post-solution activity as indicated by the specification. The limitation ‘by the processor’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 13, the limitations ‘storing processing timestamps of the target to-be-processed fault information respectively corresponding to all the fault classes’ are simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception (MPEP 2106.05(d)) II. iv.- Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93; and/or ‘encoding the target to-be-processed fault information in a forth storage which has been arbitrated and respectively corresponding to all the fault classes to obtain a fault code of the target to-be-processed fault information respectively corresponding to all the fault classes’ are mere instructions to implement an abstract idea or other exception on a computer and in this case generic computer components (MPEP 2106.05(f)); and ‘storing the fault code of the target to-be-processed fault information respectively corresponding to all the fault classes’ are simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception (MPEP 2106.05(d)) II. iv.- Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93. The limitation ‘’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 14, the limitation ‘wherein for each of the fault classes, arbitrating the to-be-processed fault information included at the fault class, to determine target to-be-processed fault information corresponding to the fault class comprises: for each fault class, arbitrating the to-be-processed fault information at this fault class based on a round robin algorithm depending on the authorization enabling information in a third configuration register, to determine the target to-be-processed fault information corresponding to this fault class’ are mental processes - concepts performed in the human mind by observation, evaluation, judgment, and/or opinion, as well as organizing. The limitation ‘by the fault processing apparatus of the chip’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 15, the limitation ‘for any fault class, recording a round-robin position of the target to-be-processed fault information at this fault class in the to-be-processed fault information at this fault class in a round-robin position register’ is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception (MPEP 2106.05(d)) II. iv.- Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93.
The limitation ‘by the fault processing apparatus of the chip’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 16, the limitations ‘after the arbitrating the to-be-processed fault information included at the fault class, to determine target to-be-processed fault information corresponding to all the fault classes, the method further comprises: recording a quantity of processing times for each piece of target to-be-processed fault information in a fault quantity register’ is simply appending well-understood, routine, conventional activities previously known to the industry, specified at a high level of generality, to the judicial exception (MPEP 2106.05(d)) II. iv.- Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93; and ‘the method further comprises: for any target to-be-processed fault information, receiving the quantity of processing times corresponding to the target to-be-processed fault information from the fault quantity register’ is simply adding insignificant extra-solution activity to the judicial exception (MPEP 2106.05(g)) by data gathering, and ‘in response to the quantity of processing times corresponding to the target to-be-processed fault information and extracted from the fault quantity register reaching a preset threshold of times, updating the fault class of the target to-be-processed fault information to an upper fault class of the current fault class, so that the target to-be-processed fault information serves as the to-be-processed fault information at the upper fault class to be arbitrated’ are mental processes - concepts performed in the human mind by observation, evaluation, judgment, and/or opinion, as well as organizing. The limitation ‘by the fault processing apparatus of the chip; by the fault processing apparatus of the chip’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 17, with the exception of the limitation ‘a fault processing apparatus of the chip; and a memory, configured to store processor-executable instructions, wherein the processor is configured to read the executable instructions from the memory, and execute the instructions to implement a fault processing method’, the claim recites concepts performed in the human mind.
The limitations ‘determine fault classes to which at least one piece of to-be-processed fault information respectively belongs based on a pre-configured first corresponding relationship stored in a first configuration register and between a fault identifier and the fault class, wherein the to-be-processed fault information comprises a fault identifier of a to-be-processed fault; in response to that the authorization enabling information being preconfigured in the corresponding third configuration register, arbitrating the to-be-processed fault information included at the fault class, to determine target to-be-processed fault information corresponding to the fault class, wherein the target to-be-processed fault information represents the to-be-processed fault information that is arbitrated from a plurality of pieces of to- be-processed fault information and that currently needs to be processed’ are mental processes -concepts performed in the human mind by observation, evaluation, judgment, and/or opinion, as well as organizing.
Step 2A: Prong two
This judicial exception is not integrated into a practical application because the limitation ‘concurrently perform corresponding fault processing on the faults at a plurality of the fault classes based on all the target to-be-processed fault information’ is simply adding insignificant extra-solution activity to the judicial exception (MPEP 2106.05(g)) by performing a generic fault processing post-solution activity as indicated by the specification.
Step 2B
The claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the limitation ‘a fault processing apparatus of the chip comprising a fault classification module, a fault arbitration module, a first configuration register, and a plurality of third configuration registers; wherein the fault classification module; wherein the fault arbitration module; transmit, by the fault classification module based on the fault classes, the at least one piece of to-be-processed fault information to arbiters of a fault arbitration module of the fault processing apparatus of the chip, wherein each of the arbiters corresponds to one of the fault classes and one of a plurality of third configuration registers of the fault processing apparatus of the chip; for each of the fault classes, determining, by a corresponding one of the arbiters of the fault arbitration module, whether authorization enabling information is preconfigured in a corresponding one of the plurality of third configuration registers; for each of the fault classes; by a corresponding one of the arbiters of the fault arbitration module; by the corresponding arbiter of the fault arbitration module’ are directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 19, the limitations ‘determining processing types respectively corresponding to all the target to-be-processed fault information based on a pre-configured second corresponding relationship stored in a second configuration register and between the fault identifier and the processing type’ is a mental process - concept performed in the human mind by observation, evaluation, judgment, and/or opinion, as well as organizing; and ‘outputting fault processing signals respectively corresponding to all the target to-be-processed fault information based on the processing types respectively corresponding to all the target to-be-processed fault information’ is simply adding insignificant extra-solution activity to the judicial exception (MPEP 2106.05(g)) by performing a generic fault processing post-solution activity as indicated by the specification. The limitation ‘the fault arbitration module is configured to concurrently perform corresponding fault processing on the faults at a plurality of fault classes based on all the target-to-be-processed fault information’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 21, the limitation ‘wherein each of the arbiters comprises an encoding unit, configured to encode the target to-be-processed fault information at the corresponding fault class to obtain a fault code of the target to-be-processed fault information at the corresponding fault class’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 22, the limitation ‘wherein the fault processing apparatus further comprising: a time register configured to store processing timestamps of the target to-be-processed fault information respectively corresponding to all the fault classes; or a fault code register configured to store a fault code of the target to-be-processed fault information respectively corresponding to all the fault classes’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 23, the limitation ‘wherein each of the arbiters comprises a round-robin authorization unit, configured to arbitrate the to-be-processed fault information at the corresponding fault class based on a round robin algorithm depending on the authorization enabling information in the corresponding third configuration register, to determine the target to-be-processed fault information corresponding to the fault class’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 24, the limitation ‘wherein each of the arbiters comprises a round-robin position register, configured to record a round-robin position of the target to-be-processed fault information at the corresponding fault class in the to-be-processed fault information at the corresponding fault class’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 25, the limitation ‘wherein each of the arbiters comprises: a fault quantity register, configured to record a quantity of processing times for the target to- be-processed fault information; and a round-robin authorization unit, configured to: receive the quantity of processing times corresponding to the target to-be-processed fault information from the fault quantity register, and in response to the quantity of processing times corresponding to the target to-be-processed fault information reaching a preset threshold of times, update the fault class of the target to-be- processed fault information to an upper fault class of the current fault class, so that the target to- be-processed fault information serves as the to-be-processed fault information at the upper fault class to be arbitrated’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Regarding claim 26, the limitation ‘further comprising: a fault pin; a processor; and a reset management module, wherein each of the arbiters is connected to the processor through an interrupt signal output line and connected to the reset management module through a reset signal output line, wherein one of the arbiters corresponding to a highest fault class among the fault classes is connected to the fault pin’ is directed to generic computer components recited at a high-level of generality such that they amount to nothing more than mere instructions to apply the exception using generic computer components (MPEP 2106.05(f)).
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: ‘fault classification module’ in claim 17; ‘fault arbitration module’ in claim 17,19; ‘encoding unit’ in claim 21; ‘round-robin authorization unit’ in claim 23,25.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Response to Arguments
Applicant's arguments and amendments filed 06/16/2026 have been fully considered. Concerning the 101 abstract idea rejection, the newly added limitations have been rejected and do not overcome the 101 abstract idea rejection. The ‘arbiters’ are generically stated within the claim limitations. Concerning the arguments of the ‘fault classification module’ and ‘fault arbitration module’, they are considered to be generic computing components performing actions. Please see the above rejection.
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/Yolanda L Wilson/Primary Examiner, Art Unit 2113
Prosecution Insights