DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-14 are pending in the application.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 8-11 and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nam et al. (US 2020/0411106) (hereinafter, “Nam”).
Re: independent claim 1, Nam discloses in fig. 28 a fabrication method of a semiconductor structure, wherein the semiconductor structure includes at least one deck structure, and a fabrication method of the deck structure comprises: providing a first stack structure (PERI), wherein a peripheral circuit (2394) is disposed in the first stack structure; forming a first contact (2271a, 2272a) and a second contact (2271b, 2272b) that at least penetrate through the first stack structure, wherein the second contact (2271b, 2272b) is connected with the peripheral circuit (2394), and the first contact (2271a, 2272a) is located on a side of the second contact (2271b, 2272b) far away from the peripheral circuit (2394); providing a second stack structure (CELL), wherein a memory cell array (including 2330) is disposed in the second stack structure; forming a third contact (2371a, 2372a) and a fourth contact (2371b, 2372b) that penetrate through the second stack structure, wherein the fourth contact (2371b, 2372b) is connected with the memory cell array, and the third contact (2371a, 2372a) is located on a side of the fourth contact (2371b, 2372b) far away from the memory cell array; and stacking and bonding the first stack structure and the second stack structure along a first direction to form the deck structure [0134], wherein the first contact (2271a, 2272a) is connected with the third contact (2371a, 2372a) by bonding to form a first interconnection structure, and the second contact (2271b, 2272b) is connected with the fourth contact (2371b, 2372b) by bonding to form a second interconnection structure.
Re: independent claim 8, Nam discloses in fig. 28 a semiconductor structure including a deck structure, the deck structure comprising: a first stack structure (PERI) and a second stack structure (CELL) that are disposed in a stack along a first direction, wherein a peripheral circuit (2394) is disposed in the first stack structure, and a memory cell array (including 2330) is disposed in the second stack structure; a first contact (2271a, 2272a) and a second contact (2271b, 2272b) that at least penetrate through the first stack structure (PERI), wherein the second contact (2271b, 2272b) is connected with the peripheral circuit (2394), and the first contact (2271a, 2272a) is located on a side of the second contact (2271b, 2272b) far away from the peripheral circuit; and a third contact (2371a, 2372a) and a fourth contact (2371b, 2372b) that penetrate through the second stack structure (CELL), wherein the fourth contact (2371b, 2372b) is connected with the memory cell array (including 2330), and the third contact (2371a, 2372a) is located on a side of the fourth contact far (2371b, 2372b) away from the memory cell array, wherein the first contact (2271a, 2272a) is connected with the third contact (2372a, 2371a) by bonding to constitute a first interconnection structure [0134], and the second contact (2271b, 2272b) is connected with the fourth contact (2372b, 2371b) by bonding to constitute a second interconnection structure [0134].
Re: claim 9, Nam discloses in fig. 28 the semiconductor structure of claim 8, wherein a composition material of the first contact is the same as a composition material of the second contact ([0134] discloses Cu-Cu bonding).
Re: claim 10, Nam discloses in fig. 28 the semiconductor structure of claim 8, wherein a composition material of the first contact is different from a composition material of the second contact ([0134] discloses bonding metals may be copper, aluminum or tungsten).
Re: claim 11, Nam discloses in fig. 28 the semiconductor structure of claim 10, wherein the composition material of the first contact (2271a, 2272a) includes copper, and the composition material of the second contact (2271b, 2272b) includes tungsten [0139].
Re: independent claim 14, Nam discloses in fig. 28 a memory system, comprising: a memory device comprising: a semiconductor structure comprising: at least one deck structure comprising: a first stack structure (PERI) and a second stack structure (CELL) that are disposed in a stack along a first direction, wherein a peripheral circuit (2394) is disposed in the first stack structure, and a memory cell array (including 2330) is disposed in the second stack structure; a first contact (2271a, 2271b) and a second contact (2271b, 2272b) that at least penetrate through the first stack structure, wherein the second contact (2271b, 2272b) is connected with the peripheral circuit (2394), and the first contact (2271a, 2272a) is located on a side of the second contact (2271b, 2272b) far away from the peripheral circuit; and a third contact (2372a, 2371a) and a fourth contact (2372b, 2371b) that penetrate through the second stack structure, wherein the fourth contact (2372b, 2371b) is connected with the memory cell array, and the third contact (2372a, 2372b) is located on a side of the fourth contact (2372b, 2371b) far away from the memory cell array, wherein the first contact (2271a, 2272a) is connected with the third contact (2372a, 2371a) by bonding to constitute a first interconnection structure [0134], and the second contact (2271a, 2272b) is connected with the fourth contact (2372b, 2371b) by bonding to constitute a second interconnection structure [0134]; and a memory controller (600 in fig. 26) connected with the memory device and configured to control the memory device.
Allowable Subject Matter
Claims 2-7 and 12-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Ogawa et al. US 11,322,483 teach a memory device containing multiple tiers.
Zhang et al. US 12,477,749 teach a three dimensional memory device containing multiple memory array assemblies and multiple periphery structures.
The examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. When responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALLISON BERNSTEIN whose telephone number is (571)272-9011. The examiner can normally be reached M-F 8AM-5PM.
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/ALLISON BERNSTEIN/Primary Examiner, Art Unit 2824 01/21/2026