CTFR 18/463,557 CTFR 91845 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-40 are pending. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-8, 11-12, 15-31, and 34-40 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kaburlasos et al. (US 20190377395) in view of Berke et al. (US 20140067139) and Felter et al. (US 20060288241) . Regarding claim 1, Kaburlasos teaches A power limiter circuit for limiting power consumption of a plurality of processing units (PUs) in a processor-based system, configured to: (a) determine a total PU power limit budget based on a difference between an overall power limit for the processor-based system and a power usage in the processor-based system ; ([0158], “multi-GPU systems, which can be found on discrete graphics cards, contain a number of GPU units that may operate on different workloads, but such GPUs are subject to a global power budget.”) (e) cause power consumption by each PU of the plurality of PUs to be constrained within the allocated power limit budget determined for the PU; (Fig. 16A, (1608), [0170], “GPU utilization can be defined in physical terms, such as the current (Icc) drawn by the GPU in an implementation in which each GPU has a current-monitor available to it.”, [0174], “The process then provides for evaluating utilization of each GPU 1608 ”) (f) determine a difference between actual power consumption of each PU of the plurality of PUs and the power limit budget for each PU; and (Fig. 16A (1610-1616), [0175], “If the utilization of a particular GPU[i] is lower than a threshold[i] value that has been defined for the GPU[i] 1610 , then this GPU is allocated a ‘low’ power budget 1614 , which is lower than the default power budget for the GPU … If there are additional GPUs to evaluate 1616 , the i value is incremented 1618 and evaluation process continues 1610 ”) (h) reallocate a new power limit budget from the total PU power limit budget for each PU of the plurality of PUs based on the determined difference between the actual power consumption and the power limit budget for each PU and based on the performance throttle event received for the PU . (Fig. 16A (1612,1614), power budgets are reallocated based on the difference) Kaburlasos teaches a total PU power limit budget but does not teach that the power limit budget is based on a difference between the overall power budget and the power usage of the system and throttling. Berke teaches (a) determine a total PU power limit budget based on a difference between an overall power limit for the processor-based system and a power usage in the processor-based system; ([0037], “dynamically allocates the power budget of the power system 202 for a plurality of time intervals based on the powered subsystem current operation (and dynamic and peak power requirements limits that are associated with that current operation).”, [0022], “the power system controller 204/300 is operable to periodically, continually, and/or constantly poll the system (e.g., the system current monitor 220) and/or the powered subsystems (e.g., the processor subsystem 206, the memory subsystem 208, the graphics processor subsystem 210, the storage subsystem 212, the Input/Output (I/O) subsystem 214, the LOB subsystem 216, and/or the one or more other powered subsystems 218) in the power budget allocation system 200 to determine how power is being used in the system .”, [0020], “a system current monitor 220 is coupled to the power system controller 204 and is operable to determine the power demands for some or all of the powered subsystems.”, and [0038], “those powered subsystems may be operable to send an alert (e.g., as programmed in blocks 610 and/or 622 of the method 600) to ensure that the power system 202 does not exceed its power output capabilities.”) (g) receive a performance throttle event for any PU of the plurality of PUs throttled based on the difference between the actual power consumption of each PU and the power limit budget for the PU: and (Figs. 6-7, [0038-39], “block 702 where a powered subsystem checks its current power demand against threshold(s) programmed in the powered subsystem. In an embodiment, the POL voltage regulator in the powered subsystem is operable to check the threshold(s) programmed in the POL voltage regulator to determine whether the power demand from the powered component in the powered subsystem exceeds the threshold(s). … block 704, the powered subsystem determines that one or more threshold(s) have been exceeded, … system level fast throttling may be based on a level of the threshold exceeded, and may result in, for example, processor performance state capping in the processor subsystem 206”) (h) reallocate a new power limit budget from the total PU power limit budget for each PU of the plurality of PUs based on the determined difference between the actual power consumption and the power limit budget for each PU and based on the performance throttle event received for the PU. (Figs. 6-7, [0037], “for each of a plurality of time intervals, to retrieve power usage data during a current time interval for each of the plurality of powered subsystems, project the powered subsystem power requirements for a subsequent time interval based on their operation during the current time interval (and, in some embodiments, powered subsystem power usage histories and/or power tables describing the worst case power requirements that can result in light of the current operating state of powered components), program the powered subsystems to ensure that their power demands do not exceed the power output capability of the power system 202 during the subsequent time interval, and program thresholds and alerts in the powered subsystems during the subsequent time interval. As such, the method 600 dynamically allocates the power budget of the power system 202 for a plurality of time intervals based on the powered subsystem current operation (and dynamic and peak power requirements limits that are associated with that current operation)” and [0039-40], “block 704, the powered subsystem determines that one or more threshold(s) have been exceeded, … system level fast throttling may be based on a level of the threshold exceeded, and may result in, for example, processor performance state capping in the processor subsystem 206 … Following the system level fast throttling at block 708, the method proceeds to block 710 where the system retrieves powered subsystem power usage data and compares that data to the programmed thresholds. In an embodiment, the power system controller 204 retrieves the power usage data from the powered subsystems subsequent to the system level fast throttling to determine system power requirements similarly as described above for blocks 614, 616, and 618 of the method 600. The method 700 then proceeds to block 712 where the system reallocates power to the subsystems based on the system power requirements determined in block 710 similarly as discussed above for blocks 620 and 622 of the method 600. In an embodiment, the power system controller 204 reallocates the power budget of the power system 202 to provide dynamic and peak power requirements of the powered subsystems based on the power usage data retrieved at the time of the assertion of the interrupt at block 706 and, in some cases, the power usage history of prior time intervals, to allocate power such that subsequent system level fast throttling events can be avoided.”) Kaburlasos and Berke are analogous art. Berke is cited to teach a similar concept of power management of an electronic system using a power budget/limits. Kaburlasos teaches controlling a processing system using a total processing limit for the processing units/cores/CPUs and reallocating power budgets. Berke teaches that a method for determining the total processing limit is based on a difference between power usage, the power limit, and throttling to change the power budget limits for each subsystem/PU. Based on Berke, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Kaburlasos to use the difference between the power consumption and the budget to reallocate a budget based on an occurrence of a throttle. Furthermore, being able to use this process improves on Kaburlasos by being able to increase performance. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because “the operation of one or more of the powered subsystems may be adjusted for each subsequent time interval based on the operation of the powered subsystems in a current time interval in order to provide the highest performance possible by the powered subsystems while ensuring that the power demand from the powered subsystems does not exceed the power output capability of the power system 202.”, [0031] Kaburlasos and Berke teach power allocation to processing units but do not teach the that the portion of total PU power limit budget for each PU of the plurality of PUs proportional to the workload activity. Felter teaches (b) receive a plurality of workload data indicating a workload activity of workloads being executed by each PU of a plurality of the PUs; ([0050-51], “power administrator 200 includes computer executable instructions for determining (block 302) for each component in the dynamic power allocation domain. Power administrator 200 is not required to dynamically allocate power to all components of the system, but is instead preferentially directed to manage the power dissipation of the major components (i.e., the components that consume the bulk of the available power). Determining component activity is preferably achieved using the same monitors that are used to determine when a component is exceeding its budgeted power, namely, performance monitoring hardware . … the predicted activity for time period N+1 is the measured activity ” and [0062], “allocates the available active power in proportion to the requirement for the components by the workload(s) executing on the system. ”) (c) determine a portion of the total PU power limit budget for each PU of the plurality of PUs proportional to the workload activity of each PU to a total workload activity of the plurality of workload data of the plurality of PUs; (Figs. 3 and 5, [0051], “the predicted activity for time period N+1 is the measured activity ”, “[0061], “The portion of P.sub.AVAIL allocated to a system is determined by the ratio of the components active power requirements to the total active power requirements of the system. This formula is represented in block 508 as PALLOC.sub.N=PMIN.sub.N+P.sub.AVAIL*(PACT.sub.N/PACT.sub.TOT). This formula effectively distributes the available system power to the system components in a manner that … (2) allocates the available active power in proportion to the requirement for the components by the workload(s) executing on the system.”) (d) allocate a power limit budget from the total PU power limit budget for each PU of the plurality of PUs based on the portion of the total PU power limit budget for each PU of the plurality of PUs; (Figs. 3 and 5, [0061], “The portion of P.sub.AVAIL allocated to a system is determined by the ratio of the components active power requirements to the total active power requirements of the system. This formula is represented in block 508 as PALLOC.sub.N=PMIN.sub.N+P.sub.AVAIL*(PACT.sub.N/PACT.sub.TOT). This formula effectively distributes the available system power to the system components in a manner that … (2) allocates the available active power in proportion to the requirement for the components by the workload(s) executing on the system.”) Kaburlasos, Berke, and Felter are analogous art. Felter is cited to teach a similar concept of power management of an electronic system using a power budget/limits. Kaburlasos teaches controlling a processing system using a total processing limit for the processing units/cores/CPUs and reallocating power budgets. Berke teaches that a method for determining the total processing limit is based on a difference between power usage, the power limit, and throttling to change the power budget limits for each subsystem/PU. Felter teaches determining a power allocation based on workload activity proportional to the total workload activity. Based on Felter, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Kaburlasos and Berke to allocate power based on workload activity proportional to the total workload activity. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because “the ability to manage multiple components gives greater flexibility and can be more effectively exploited to reduce the performance impact of regulating activity.”, [0006] and “a relationship among the activity levels of various components in a data processing system that makes dynamic power allocation more efficient than static allocation.”, [0022] Regarding claim 2, Kaburlasos teaches further configured to set an operating point for a PU of the plurality of PUs based on the allocated power limit budget for the PU. ([0167], “the CPU 1505 submits different workloads on each GPU and the GPUs execute the submitted workloads at a particular frequency and power budget.”) Regarding claim 3, Kaburlasos teaches further configured to reset the operating point for the PU of the plurality of PUs based on the reallocated new power limit budget for the PU. (Fig. 16A, (1642), [0176], “The reallocation of the power budget may occur in various forms depending on the individual system, but may include allowance of increased frequency of operation or other power allowance. As a result of the dynamic power budget reallocation, any one or more GPUs with utilization less than their utilization-threshold (Threshold[i]) will operate with a reduced (lower than the applicable default for each GPU) power budget in the next cycle, whereas the remaining one or more GPUs will operate with an increased (higher than the applicable default for each GPU) power budget”) Regarding claim 4, Kaburlasos teaches configured to: determine the difference between the actual power consumption of each PU of the plurality of PUs and the power limit budget for each PU, by being configured to: receive a first actual power consumption of a first PU of the plurality of PUs; compare the first actual power consumption to the power limit budget allocated to the first PU; and determine a difference between the first actual power consumption and the power limit budget allocated to the first PU; and reallocate the new power limit budget by being configured to: reallocate the new power limit budget from the total PU power limit budget for the first PU based on the determined difference between the first actual power consumption and the power limit budget allocated to the first PU and based on the performance throttle event received for the PU ; and reallocate at least one power limit budget for at least one second PU of the plurality of PUs from the total PU power limit budget based on a difference between the total PU power limit budget and the new power limit budget for the first PU and based on the performance throttle event received for the PU . (Figs. 16 (1608, 1610, 1620, 1622), [0176], “The reallocation of the power budget may occur in various forms depending on the individual system, but may include allowance of increased frequency of operation or other power allowance. As a result of the dynamic power budget reallocation, any one or more GPUs with utilization less than their utilization-threshold (Threshold[i]) will operate with a reduced (lower than the applicable default for each GPU) power budget in the next cycle, whereas the remaining one or more GPUs will operate with an increased (higher than the applicable default for each GPU) power budget”) Kaburlasos teaches that power can be reallocated from GPU’s using less power than their budget to GPU’s requiring more power but does not specifically teach that this event occurs based on a throttling event. Berke teaches and based on the performance throttle event received for the PU (Figs. 6-7, [0037], “for each of a plurality of time intervals, to retrieve power usage data during a current time interval for each of the plurality of powered subsystems, project the powered subsystem power requirements for a subsequent time interval based on their operation during the current time interval (and, in some embodiments, powered subsystem power usage histories and/or power tables describing the worst case power requirements that can result in light of the current operating state of powered components), program the powered subsystems to ensure that their power demands do not exceed the power output capability of the power system 202 during the subsequent time interval, and program thresholds and alerts in the powered subsystems during the subsequent time interval. As such, the method 600 dynamically allocates the power budget of the power system 202 for a plurality of time intervals based on the powered subsystem current operation (and dynamic and peak power requirements limits that are associated with that current operation)” and [0039-40], “block 704, the powered subsystem determines that one or more threshold(s) have been exceeded, … system level fast throttling may be based on a level of the threshold exceeded, and may result in, for example, processor performance state capping in the processor subsystem 206 … Following the system level fast throttling at block 708, the method proceeds to block 710 where the system retrieves powered subsystem power usage data and compares that data to the programmed thresholds. In an embodiment, the power system controller 204 retrieves the power usage data from the powered subsystems subsequent to the system level fast throttling to determine system power requirements similarly as described above for blocks 614, 616, and 618 of the method 600. The method 700 then proceeds to block 712 where the system reallocates power to the subsystems based on the system power requirements determined in block 710 similarly as discussed above for blocks 620 and 622 of the method 600. In an embodiment, the power system controller 204 reallocates the power budget of the power system 202 to provide dynamic and peak power requirements of the powered subsystems based on the power usage data retrieved at the time of the assertion of the interrupt at block 706 and, in some cases, the power usage history of prior time intervals, to allocate power such that subsequent system level fast throttling events can be avoided.”) Regarding claim 5, Kaburlasos teaches configured to: determine the difference between the first actual power consumption and the power limit budget allocated to the first PU by being configured to determine if the first actual power consumption is less than the power limit budget allocated to the first PU; (Fig. 16A, (1610)) reallocate the new power limit budget from the total PU power limit budget for the first PU based on lowering the power limit budget for the first PU based on the determined difference between the first actual power consumption and the power limit budget allocated to the first PU and based on the performance throttle event for the first PU; and (Fig. 16A, (1614)) reallocate the at least one power limit budget for the at least one second PU by being configured to increase the at least one power limit budget for the at least one second PU from the total PU power limit budget based on the difference between the total PU power limit budget and the new power limit budget for the first PU and based on the performance throttle event for at least one second PU. (Fig. 16A, (1622)), [0176], “re-allocates the remaining power budget that is left over to any GPUs whose utilization has not dropped below their threshold[i] value 1622 . The reallocation of the power budget may occur in various forms depending on the individual system, but may include allowance of increased frequency of operation or other power allowance.”) Kaburlasos teaches that power can be reallocated from GPU’s using less power than their budget to GPU’s requiring more power but does not specifically teach that this event occurs based on a throttling event. Berke teaches and based on the performance throttle event received for the PU (Figs. 6-7, [0037], “for each of a plurality of time intervals, to retrieve power usage data during a current time interval for each of the plurality of powered subsystems, project the powered subsystem power requirements for a subsequent time interval based on their operation during the current time interval (and, in some embodiments, powered subsystem power usage histories and/or power tables describing the worst case power requirements that can result in light of the current operating state of powered components), program the powered subsystems to ensure that their power demands do not exceed the power output capability of the power system 202 during the subsequent time interval, and program thresholds and alerts in the powered subsystems during the subsequent time interval. As such, the method 600 dynamically allocates the power budget of the power system 202 for a plurality of time intervals based on the powered subsystem current operation (and dynamic and peak power requirements limits that are associated with that current operation)” and [0039-40], “block 704, the powered subsystem determines that one or more threshold(s) have been exceeded, … system level fast throttling may be based on a level of the threshold exceeded, and may result in, for example, processor performance state capping in the processor subsystem 206 … Following the system level fast throttling at block 708, the method proceeds to block 710 where the system retrieves powered subsystem power usage data and compares that data to the programmed thresholds. In an embodiment, the power system controller 204 retrieves the power usage data from the powered subsystems subsequent to the system level fast throttling to determine system power requirements similarly as described above for blocks 614, 616, and 618 of the method 600. The method 700 then proceeds to block 712 where the system reallocates power to the subsystems based on the system power requirements determined in block 710 similarly as discussed above for blocks 620 and 622 of the method 600. In an embodiment, the power system controller 204 reallocates the power budget of the power system 202 to provide dynamic and peak power requirements of the powered subsystems based on the power usage data retrieved at the time of the assertion of the interrupt at block 706 and, in some cases, the power usage history of prior time intervals, to allocate power such that subsequent system level fast throttling events can be avoided.”) Regarding claim 6, Kaburlasos teaches configured to: determine the difference between the first actual power consumption and the power limit budget allocated to the first PU by being configured to determine if the first actual power consumption is greater than the power limit budget allocated to the first PU; reallocate the new power limit budget from the total PU power limit budget for the first PU based on increasing the power limit budget for the first PU based on the determined difference between the first actual power consumption and the power limit budget allocated to the first PU, and based on the performance throttle event for the first PU ; and reallocate the at least one power limit budget for the at least one second PU by being configured to decrease the at least one power limit budget for the at least one second PU from the total PU power limit budget based on the difference between the total PU power limit budget and the new power limit budget for the first PU, and based on the performance throttle event for the second PU . (Fig 16B, (1638-1642), [0179], “If the workload of one or more GPU(s) requires additional power budget 1640 , such as the execution of an application that requires a faster frame rate than can be provided with the current power budget, and if additional power budget is available from the remaining GPUs 1642 (such as, if it is possible to reduce power budget without significantly reducing performance of the other GPUs), then a portion of the global power budget is reallocated to the one or more GPUs from the remaining GPUs 1644 .”) Kaburlasos teaches that power can be reallocated from GPU’s using less power than their budget to GPU’s requiring more power but does not specifically teach that this event occurs based on a throttling event. Berke teaches and based on the performance throttle event received for the PU (Figs. 6-7, [0037], “for each of a plurality of time intervals, to retrieve power usage data during a current time interval for each of the plurality of powered subsystems, project the powered subsystem power requirements for a subsequent time interval based on their operation during the current time interval (and, in some embodiments, powered subsystem power usage histories and/or power tables describing the worst case power requirements that can result in light of the current operating state of powered components), program the powered subsystems to ensure that their power demands do not exceed the power output capability of the power system 202 during the subsequent time interval, and program thresholds and alerts in the powered subsystems during the subsequent time interval. As such, the method 600 dynamically allocates the power budget of the power system 202 for a plurality of time intervals based on the powered subsystem current operation (and dynamic and peak power requirements limits that are associated with that current operation)” and [0039-40], “block 704, the powered subsystem determines that one or more threshold(s) have been exceeded, … system level fast throttling may be based on a level of the threshold exceeded, and may result in, for example, processor performance state capping in the processor subsystem 206 … Following the system level fast throttling at block 708, the method proceeds to block 710 where the system retrieves powered subsystem power usage data and compares that data to the programmed thresholds. In an embodiment, the power system controller 204 retrieves the power usage data from the powered subsystems subsequent to the system level fast throttling to determine system power requirements similarly as described above for blocks 614, 616, and 618 of the method 600. The method 700 then proceeds to block 712 where the system reallocates power to the subsystems based on the system power requirements determined in block 710 similarly as discussed above for blocks 620 and 622 of the method 600. In an embodiment, the power system controller 204 reallocates the power budget of the power system 202 to provide dynamic and peak power requirements of the powered subsystems based on the power usage data retrieved at the time of the assertion of the interrupt at block 706 and, in some cases, the power usage history of prior time intervals, to allocate power such that subsequent system level fast throttling events can be avoided.”) Regarding claim 7, Kaburlasos teaches further configured to: in response to receiving the performance throttle event for a first PU of the plurality of PUs: ([0185], “GPUs often are designed so that they can throttle their frequency down when the Icc load gets close to the Iccmax limit.” And [0195], “ the process further includes identifying power budget violations by each processor 1930 , such as identifying instances in which a typical performance processor (such as a processor having the typical performance curve 1810 illustrated in FIG. 18) exceeds the current draw limits for such processor because of operation at or near a maximum frequency at a high application ratio.”) reallocate the new power limit budget by being configured to: reallocate the new power limit budget for the first PU lower than the power limit budget allocated to the first PU; and reallocate at least one new power limit budget for at least one second PU of the plurality of PUs based on a difference between the total PU power limit budget and the new power limit budget allocated to the first PU. ([0198], “If power budget violations are detected 1935 , then workloads may be reassigned between processors to reduce such violations, the reassignment being the transfer of workloads between the one or more lower performance processors that have had power budget violations and the one more or more higher performance processors 1940 . The reassignment of workloads may be utilized to reduce the number of power budget violations due to the ability of the one or more higher performance processors to operate at a higher frequency while drawing lower current.” And [0195], “The process may further include reallocating the global power budget among the processors according to certain criteria 1925 , such as illustrated in FIGS. 16A and 16B.”) Regarding claim 8, Berke teaches further configured to: (e) monitor the actual power consumption comprising an average power consumption of each PU of the plurality of PUs; and ([0032], “where powered subsystem power usage data is retrieved. In an embodiment, the power system controller 204 polls or otherwise retrieves from each powered subsystem (e.g., from the POL voltage regulator in each powered subsystem) an average power, a peak power (or peak current), any programmed threshold crossings (including warning thresholds, danger thresholds, critical thresholds, and/or other thresholds known in the art)”) (g) reallocate the new power limit budget from the total PU power limit budget for each PU of the plurality of PUs based on the monitored average power consumption of each PU of the plurality of PUs and based on the performance throttle event received for the PU. ((Figs. 6-7, [0037], “for each of a plurality of time intervals, to retrieve power usage data during a current time interval for each of the plurality of powered subsystems, project the powered subsystem power requirements for a subsequent time interval based on their operation during the current time interval (and, in some embodiments, powered subsystem power usage histories and/or power tables describing the worst case power requirements that can result in light of the current operating state of powered components), program the powered subsystems to ensure that their power demands do not exceed the power output capability of the power system 202 during the subsequent time interval, and program thresholds and alerts in the powered subsystems during the subsequent time interval. As such, the method 600 dynamically allocates the power budget of the power system 202 for a plurality of time intervals based on the powered subsystem current operation (and dynamic and peak power requirements limits that are associated with that current operation)” and [0039-40], “block 704, the powered subsystem determines that one or more threshold(s) have been exceeded, … system level fast throttling may be based on a level of the threshold exceeded, and may result in, for example, processor performance state capping in the processor subsystem 206 … Following the system level fast throttling at block 708, the method proceeds to block 710 where the system retrieves powered subsystem power usage data and compares that data to the programmed thresholds. In an embodiment, the power system controller 204 retrieves the power usage data from the powered subsystems subsequent to the system level fast throttling to determine system power requirements similarly as described above for blocks 614, 616, and 618 of the method 600. The method 700 then proceeds to block 712 where the system reallocates power to the subsystems based on the system power requirements determined in block 710 similarly as discussed above for blocks 620 and 622 of the method 600. In an embodiment, the power system controller 204 reallocates the power budget of the power system 202 to provide dynamic and peak power requirements of the powered subsystems based on the power usage data retrieved at the time of the assertion of the interrupt at block 706 and, in some cases, the power usage history of prior time intervals, to allocate power such that subsequent system level fast throttling events can be avoided.”) Regarding claim 11, Kaburlasos teaches configured to continuously repeat (a)-(g). (Fig. 16A) Regarding claim 12, Kaburlasos teaches configured to continuously repeat (a)-(f) in response to expiration of a timer reset to a constant time. ([0174], “After a certain unit of time (the unit of time being ‘dt’), the utilization of each GPU is evaluated. ”) Regarding claim 15, Kaburlasos teaches further configured to enable the continuous repeat of (a)-(g) in response to a PU enable signal indicating an active operation state of the plurality of PUs. (0173], “ Upon starting operation at an initial time (Time=0) 1600 , a workload is assigned to each GPU 1602 and an initial (default) power budget is set for each GPU 1604 . The initial power budget may in some embodiments be the same for each GPU.”) Regarding claim 16, Kaburlasos teaches further configured to receive power telemetry data comprising the power usage in the processor-based system. ([0194],” The system is to monitor the power usage of each of the processors 1920 .”) Regarding claim 17, Berke teaches wherein the power telemetry data comprises power usage of a plurality of non-PU power consuming devices in the processor-based system. ([0022], “the power system controller 204/300 is operable to periodically, continually, and/or constantly poll the system (e.g., the system current monitor 220) and/or the powered subsystems (e.g., the processor subsystem 206, the memory subsystem 208, the graphics processor subsystem 210, the storage subsystem 212, the Input/Output (I/O) subsystem 214, the LOB subsystem 216, and/or the one or more other powered subsystems 218) in the power budget allocation system 200 to determine how power is being used in the system. … The power system controller 204/300 may interface with the system current monitor 220, the voltage regulators in the powered subsystems, and/or other power conversion and/or detection elements throughout the power budget allocation system 200. In one embodiment, the real-time or near-real-time telemetry measurement conducted by the power system controller 204/300 may be realized using a power capping algorithm that performs measurements at a rate of approximately once per millisecond (ms).”) Regarding claim 18, Kaburlasos teaches further comprising: a power limit budget determination circuit configured to: determine the total PU power limit budget based on the difference between the overall power limit for the processor-based system and the power usage; ([0158], “multi-GPU systems, which can be found on discrete graphics cards, contain a number of GPU units that may operate on different workloads, but such GPUs are subject to a global power budget.”) a power limit budget allocation circuit configured to: (b) receive the plurality of workload data indicating the workload activity of each PU of the plurality of the PUs; (Fig. 16A (1602), [0173], “ a workload is assigned to each GPU 1602 ”) a power limit budget circuit configured to: (e) cause the power consumption by each PU of the plurality of PUs to be constrained within the allocated power limit budget determined for each PU; (Fig. 16A, (1608), [0170], “GPU utilization can be defined in physical terms, such as the current (Icc) drawn by the GPU in an implementation in which each GPU has a current-monitor available to it.”, [0174], “The process then provides for evaluating utilization of each GPU 1608 ”) a power consumption differential circuit configured to: (f) determine the difference between the actual power consumption of each PU of the plurality of PUs and the power limit budget for each PU; and (Fig. 16A (1610-1616), [0175], “If the utilization of a particular GPU[i] is lower than a threshold[i] value that has been defined for the GPU[i] 1610 , then this GPU is allocated a ‘low’ power budget 1614 , which is lower than the default power budget for the GPU … If there are additional GPUs to evaluate 1616 , the i value is incremented 1618 and evaluation process continues 1610 ”) the power limit budget allocation circuit further configured to: (g) reallocate the new power limit budget from the total PU power limit budget for each PU of the plurality of PUs based on the determined difference between the actual power consumption of each PU of the plurality of PUs and the power limit budget for each PU and based on the performance throttle event received for the PU . (Fig. 16A (1612,1614), power budgets are reallocated based on the difference) Kaburlasos teaches a total PU power limit budget but does not teach that the power limit budget is based on a difference between the overall power budget and the power usage of the system. Berke teaches the total PU power limit budget based on the difference between the overall power limit for the processor-based system and the power usage; ([0037], “dynamically allocates the power budget of the power system 202 for a plurality of time intervals based on the powered subsystem current operation (and dynamic and peak power requirements limits that are associated with that current operation).”, [0022], “the power system controller 204/300 is operable to periodically, continually, and/or constantly poll the system (e.g., the system current monitor 220) and/or the powered subsystems (e.g., the processor subsystem 206, the memory subsystem 208, the graphics processor subsystem 210, the storage subsystem 212, the Input/Output (I/O) subsystem 214, the LOB subsystem 216, and/or the one or more other powered subsystems 218) in the power budget allocation system 200 to determine how power is being used in the system .”, [0020], “a system current monitor 220 is coupled to the power system controller 204 and is operable to determine the power demands for some or all of the powered subsystems.”, and [0038], “those powered subsystems may be operable to send an alert (e.g., as programmed in blocks 610 and/or 622 of the method 600) to ensure that the power system 202 does not exceed its power output capabilities.”) (g) reallocate the new power limit budget from the total PU power limit budget for each PU of the plurality of PUs based on the determined difference between the actual power consumption of each PU of the plurality of PUs and the power limit budget for each PU and based on the performance throttle event received for the PU. (Figs. 6-7, [0037], “for each of a plurality of time intervals, to retrieve power usage data during a current time interval for each of the plurality of powered subsystems, project the powered subsystem power requirements for a subsequent time interval based on their operation during the current time interval (and, in some embodiments, powered subsystem power usage histories and/or power tables describing the worst case power requirements that can result in light of the current operating state of powered components), program the powered subsystems to ensure that their power demands do not exceed the power output capability of the power system 202 during the subsequent time interval, and program thresholds and alerts in the powered subsystems during the subsequent time interval. As such, the method 600 dynamically allocates the power budget of the power system 202 for a plurality of time intervals based on the powered subsystem current operation (and dynamic and peak power requirements limits that are associated with that current operation)” and [0039-40], “block 704, the powered subsystem determines that one or more threshold(s) have been exceeded, … system level fast throttling may be based on a level of the threshold exceeded, and may result in, for example, processor performance state capping in the processor subsystem 206 … Following the system level fast throttling at block 708, the method proceeds to block 710 where the system retrieves powered subsystem power usage data and compares that data to the programmed thresholds. In an embodiment, the power system controller 204 retrieves the power usage data from the powered subsystems subsequent to the system level fast throttling to determine system power requirements similarly as described above for blocks 614, 616, and 618 of the method 600. The method 700 then proceeds to block 712 where the system reallocates power to the subsystems based on the system power requirements determined in block 710 similarly as discussed above for blocks 620 and 622 of the method 600. In an embodiment, the power system controller 204 reallocates the power budget of the power system 202 to provide dynamic and peak power requirements of the powered subsystems based on the power usage data retrieved at the time of the assertion of the interrupt at block 706 and, in some cases, the power usage history of prior time intervals, to allocate power such that subsequent system level fast throttling events can be avoided.”) Kaburlasos and Berke teach power allocation to processing units but do not teach the that the portion of total PU power limit budget for each PU of the plurality of PUs proportional to the workload activity. Felter teaches (c) determine a portion of the total PU power limit budget for each PU of the plurality of PUs proportional to the workload activity of each PU to a total workload activity of the plurality of workload data of the plurality of PUs; (Figs. 3 and 5, [0051], “the simplest implementation, the predicted activity for time period N+1 is the measured activity ” and [0061], “The portion of P.sub.AVAIL allocated to a system is determined by the ratio of the components active power requirements to the total active power requirements of the system. This formula is represented in block 508 as PALLOC.sub.N=PMIN.sub.N+P.sub.AVAIL*(PACT.sub.N/PACT.sub.TOT). This formula effectively distributes the available system power to the system components in a manner that … (2) allocates the available active power in proportion to the requirement for the components by the workload(s) executing on the system.”) (d) allocate a power limit budget from the total PU power limit budget for each PU of the plurality of PUs based on the portion of the total PU power limit budget for each PU of the plurality of PUs; (Figs. 3 and 5, [0061], “The portion of P.sub.AVAIL allocated to a system is determined by the ratio of the components active power requirements to the total active power requirements of the system. This formula is represented in block 508 as PALLOC.sub.N=PMIN.sub.N+P.sub.AVAIL*(PACT.sub.N/PACT.sub.TOT). This formula effectively distributes the available system power to the system components in a manner that … (2) allocates the available active power in proportion to the requirement for the components by the workload(s) executing on the system.”) Regarding claim 19, Kaburlasos teaches integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter. ([0037], “In some embodiments the system 100 is a mobile phone, smart phone, tablet computing device or mobile Internet device. The processing system 100 can also include, couple with, or be integrated within a wearable device, such as a smart watch wearable device, smart eyewear device, augmented reality device, or virtual reality device.”) As to claims 20 and 31, Kaburlasos, Berke, and Felter teach these claims according to the reasoning provided in claim 1. As to claim 21, Kaburlasos, Berke, and Felter teach this claim according to the reasoning provided in claim 2. As to claim 22, Kaburlasos, Berke, and Felter teach these claims according to the reasoning provided in claim 3. As to claims 23-25 and 34-36, Kaburlasos, Berke, and Felter teach these claims according to the reasoning provided in claim 4-6, respectively. As to claims 26 and 37, Kaburlasos, Berke, and Felter teach these claims according to the reasoning provided in claims 1 and 7. As to claims 27 and 38, Kaburlasos, Berke, and Felter teach these claims according to the reasoning provided in claim 8. As to claims 28 and 39, Kaburlasos, Berke, and Felter teach these claims according to the reasoning provided in claim 11. As to claims 29-30, Kaburlasos, Berke, and Felter teach these claims according to the reasoning provided in claim 16-17, respectively. As to claim 40, Kaburlasos, Berke, and Felter teach this claim according to the reasoning provided in claim 19 . 07-22-aia AIA Claim (s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kaburlasos and Berke as applied to claim 1 above, and further in view of Kim et al. (US 20120173895) . Regarding claim 9, Kaburlasos, Berke, and Felter teach using workload activity to determine power budgets but do not teach using weighting to of the workload activity to determine the power allocations. Kim teaches further comprising a power budget weight distribution circuit configured to: (b) receive the plurality of workload data indicating the workload activity of each PU of the plurality of the PUs; and ([0023], “the power control unit may manage a power budget for multiple domains on a priority basis. For example, the power control unit may shift the power budget from a domain with poor efficiency rating to a domain with high efficiency rating such as that the maximum performance for the workload “ and [0025], “the PCL 109 may be provided within each domain or a centralized power control unit 150 may be provided to perform power budget allocation. In one embodiment, each P-core 110-A to 110-N may represent an independent domain. … The efficiency rating and power allocation techniques described above are applicable to any of the scenarios described above and many other scenarios in which there are portions of the processor 100 operating at different clock frequency levels.” And [0033], “the efficiency rating block ERB 105 may determine the efficiency rating for each domain 101-A to 101-K simultaneously or at the same time based on the values stored in the registers 102, 103, 104, and the performance monitoring counter PMC 111.”) (c) allocate the power limit budget for each PU of the plurality of PUs by being configured to: ([0040], “the power control unit 150 may allocate the power budget to the domains 110-A to 110-K based on the efficiency ratings.”) determine a percentage weight of the total PU power limit budget for each PU of the plurality of PUs proportional to the workload activity of each PU to a total workload activity of the plurality of workload data of the plurality of PUs; and ([0043], “the ERB 105 may determine the scalability factor for the domain 101-A using the performance values stored in the PMC 111-A and the FV register 104-A as described above.” [0033], ““the efficiency rating block ERB 105 may determine the efficiency rating for each domain 101-A to 101-K simultaneously or at the same time based on the values stored in the registers 102, 103, 104, and the performance monitoring counter PMC 111.” Where the efficiency rating is proportional to the performance counters (i.e. workload activity)) allocate the power limit budget from the total PU power limit budget for each PU of the plurality of PUs based on the percentage weight of each PU of the plurality of PUs. ([0040], “the power control unit 150 may allocate the power budget to the domains 110-A to 110-K based on the efficiency ratings. For example, the domain with a higher efficiency rating may be provided a maximum of the total power budget that may be required to complete the workload successfully. … In one embodiment, the power control unit 150 may sort the domains based on the efficiency ratings and allocate the power budget in that order .”) Kim, Kaburlasos, Berke, and Felter are analogous art. Kim is cited to teach a similar concept of power management of an electronic system using a power budget/limits. Kaburlasos teaches controlling a processing system using a total processing limit for the processing units/cores/CPUs. Kim teaches determining a power limit budget base on weighting of workload activity. Based on Kim, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Kaburlasos and Berke to determine the power budget limits based on weighting determined by workload activity. Furthermore, being able to use this process improves on Kaburlasos, Berke, and Felter by being able to increase performance. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because “The ER may indicate relative advantage among domains in terms of performance return for a given power budget, i.e., a higher effectiveness may be expected in power utilization if the ER is higher for a domain.”, Abstract 07-22-aia AIA Claim (s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kaburlasos, Berke, and Felter as applied to claim 1 above, and further in view of Mukherjee et al. (US 20230239809) Regarding claim 10, Kaburlasos, Berke, and Felter do not teach but Mukherjee teaches further comprising a memory comprising a plurality of power limit budget registers each configured to store the power limit budget for a PU of the plurality of PUs, wherein: the power limiter circuit is further configured to: store the allocated power limit budget for each PU of the plurality of PUs in a power limit budget register of the plurality of power limit budget registers assigned to the PU; and access the stored power limit budget for each PU of the plurality of PUs in the plurality of power limit budget registers; and the power limiter circuit is configured to cause the power consumption by each PU of the plurality of PUs to be constrained within the accessed stored power limit budget determined for each PU. ([0025], “optionally additional information as described herein, to determine power limits 101 C, 102 C, 103 C for the devices 101 , 102 , 103 . The group power manager 122 can provide the power limits 101 C, 102 C, 103 C to the devices 101 , 102 , 103 , and the local managers 101 A, 102 A, 103 A can enforce the power limits 101 C, 102 C, 103 C at the devices 101 , 102 , 103 .” And [0035], “The respective local managers 101 A, 102 A, 103 A can be configured to receive respective power limits 101 C, 102 C, 103 C from the group power manager 122 , and to enforce the respective power limits 101 C, 102 C, 103 C at the respective devices 101 , 102 , and 103 .”) Mukherjee, Kaburlasos, Berke, and Felter are analogous art. Mukherjee is cited to teach a similar concept of power management of an electronic system using a power budget/limits. Kaburlasos teaches controlling a processing system using a total processing limit for the processing units/cores/CPUs. Mukherjee teaches power budget register to store the power budget limits. Based on Mukherjee, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Kaburlasos, Berke, and Felter to be able to control and modify the power budget limits by being able to store them in registers. Furthermore, being able to use control and modify the power budget limits by storing them in a register improves on Kaburlasos, Berke, and Felter by being able to control and modify the power budget limits dynamically to improve performance of the system. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification to control and modify the power budget limits dynamically which improves performance of the system . 07-22-aia AIA Claim (s) 13-14 and 32-33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kaburlasos, Berke, and Felter as applied to claim 1 above, and further in view of Lu et al. (US 20160054776) Regarding claim 13, Kaburlasos, Berke, and Felter do not teach but Lu teaches configured to continuously repeat (a)-(g) in response to a power limiting budget interrupt. ([0041], “the processing circuit 110 is capable of raising an interrupt request (IRQ) (e.g. a peak power IRQ, or any of another types of IRQs) according to the power consumption index, to trigger the power limiter protection operation for the electronic device.”) Lu, Kaburlasos, Berke, and Felter are analogous art. Lu is cited to teach a similar concept of power management of an electronic system using a power budget/limits. Kaburlasos teaches controlling a processing system using a total processing limit for the processing units/cores/CPUs. Lu teaches issuing an interrupt when a peak power occurs which will trigger power limiter protections. Based on Lu, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Kaburlasos, Berke, and Felter to use an interrupt to trigger peak power limiter protections. Furthermore, being able to use this process improves on Kaburlasos, Berke, and Felter by being able to increase performance. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because “It is an advantage of the present invention that the present invention method and the associated apparatus can enhance the overall performance of the electronic system”, [0010] Regarding claim 14, Lu teaches further configured to disable the continuous repeat of (a)-(g) in response to a PU disable signal indicating an inactive operation state of the plurality of PUs. (FIG. 3 in the peak power IRQ control scheme. Please note that, when needed, the processing circuit 110 (e.g. the power budget control circuit 310 ) may selectively enable the power consumption index generators {PCIG(n)}, and may switch between enabling the power consumption index generators {PCIG(n)} and disabling the power consumption index generators {PCIG(n)}.” And Fig. 5 (530), “In Step 530 , the power budget control circuit 310 may wait for the next round (of operations).”) Lu, Kaburlasos, Berke, and Felter are analogous art. Lu is cited to teach a similar concept of power management of an electronic system using a power budget/limits. Kaburlasos teaches controlling a processing system using a total processing limit for the processing units/cores/CPUs. Lu teaches enabling and disabling the power limit protection evaluation. Based on Lu, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Kaburlasos, Berke, and Felter to be able to disable the power limit protection analysis until the power limit interrupt is issued. Furthermore, being able to use this process improves on Kaburlasos, Berke, and Felter by being able to increase performance. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because “It is an advantage of the present invention that the present invention method and the associated apparatus can enhance the overall performance of the electronic system”, [0010] Regarding claim 32, Kaburlasos, Berke, and Felter teach controlling a power budget and controlling frequency but does not specifically mention controlling voltage. Lu teaches comprising: a dynamic voltage frequency scaling (DVFS) circuit configured to set an operating frequency and voltage for operation of a PU of the plurality of PUs; ([0045], “a plurality of control schemes may be utilized at the same time based on the architecture shown in FIG. 3. Examples of the plurality of control schemes may include, but not limited to, software (SW) dynamic voltage and frequency scaling (DVFS) control schemes, hardware (HW) DVFS control schemes” the power limiter circuit further configured to: set an operating point for a PU of the plurality of PUs in the DVFS circuit based on the allocated power limit budget for the PU of the plurality of PUs and based on the performance throttle event received for the PU.. ([0046-47], “the power budget control circuit 310 may perform power budget calculations according to one or more inputs of the power budget control circuit 310 , to generate one or more of multiple outputs of the power budget control circuit 310 , where the number of activated outputs within the multiple outputs of the power budget control circuit 310 may depend on the activated control schemes within the plurality of control schemes. … examples of the multiple outputs of the power budget control circuit 310 may include, but not limited to, the remaining power budget information RPB, the hardware DVFS information {HW_DVFS},”) Lu, Kaburlasos, Berke, and Felter are analogous art. Lu is cited to teach a similar concept of power management of an electronic system using a power budget/limits. Kaburlasos teaches controlling a processing system using a total processing limit for the processing units/cores/CPUs. Lu teaches using DVFS to maintain the processing units/cores/CPUs within the power budget. Based on Lu, it would have been obvious before the effective filing date of the invention to a person having ordinary skill in the art to which said subject matter pertains to have modified Kaburlasos, Berke, and Felter to be able to use DVFS to maintain the processing units/cores/CPUs within the power budget. Furthermore, being able to use this process improves on Kaburlasos, Berke, and Felter by being able optimize performance of the system. To one of ordinary skill in the art before the effective filing data of the invention it would have been advantageous to make this modification because “It is an advantage of the present invention that the present invention method and the associated apparatus can enhance the overall performance of the electronic system”, [0010] As to claims 33, Kaburlasos, Berke, Felter and Lu teach these claims according to the reasoning provided in claim 3 . Response to Arguments 07-37 AIA Applicant's arguments filed 02/03/2026 have been fully considered but they are not persuasive. The Applicant argues that in claims 1, 20, and 31 Felter does not teach “determine a portion of the total PU power limit budget for each PU of the plurality of PUs proportional to the workload activity of each PU to a total workload activity of the plurality of workload data of the plurality of PUs”. The Examiner respectfully disagrees because Felter teaches that the workload activity that the power budget is calculated from is a current workload activity based on paragraph [0051]. The Applicant argues that the “active power requirement” is not indicative of “workload activity of workloads being executed” because in Felter the “expected level of active power consumption” occurs during the upcoming interval. According to Fig. 5 of the Applicant’s invention, a periodic timer triggers the calculation of the power for a component and then calculates a new power budget after the power consumption is determined for the components. Paragraph [0051] and Figs. 3 and 5 of Felter explicitly state “the predicted activity for time period N+1 is the measured activity for time period N” i.e. a trigger is issued to measure a current amount of activity/power (period N) and from the current activity new power budget limits are set and “(2) allocates the available active power in proportion to the requirement for the components by the workload(s) executing on the system.” [0061]. In Felter’s Fig. 3 and 5, as described in paragraphs [0051 and 61], the power consumption then generates a new power budget limit based on the current duration of activity of the component and in proportion to the workload activity which reads on the claim language “ determine a portion of the total PU power limit budget for each of the PUs proportional to the workload activity ”. Therefore, the Applicant’s arguments are not persuasive and the rejection is maintained . Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHERI L. HARRINGTON whose telephone number is (571)270-0468. The examiner can normally be reached Generally, M-F, 7:30a-4p. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHERI L HARRINGTON/Examiner, Art Unit 2176 May 28, 2026 /JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176 Application/Control Number: 18/463,557 Page 2 Art Unit: 2176 Application/Control Number: 18/463,557 Page 3 Art Unit: 2176 Application/Control Number: 18/463,557 Page 4 Art Unit: 2176 Application/Control Number: 18/463,557 Page 5 Art Unit: 2176 Application/Control Number: 18/463,557 Page 6 Art Unit: 2176 Application/Control Number: 18/463,557 Page 7 Art Unit: 2176 Application/Control Number: 18/463,557 Page 8 Art Unit: 2176 Application/Control Number: 18/463,557 Page 9 Art Unit: 2176 Application/Control Number: 18/463,557 Page 10 Art Unit: 2176 Application/Control Number: 18/463,557 Page 11 Art Unit: 2176 Application/Control Number: 18/463,557 Page 12 Art Unit: 2176 Application/Control Number: 18/463,557 Page 13 Art Unit: 2176 Application/Control Number: 18/463,557 Page 14 Art Unit: 2176 Application/Control Number: 18/463,557 Page 15 Art Unit: 2176 Application/Control Number: 18/463,557 Page 16 Art Unit: 2176 Application/Control Number: 18/463,557 Page 17 Art Unit: 2176 Application/Control Number: 18/463,557 Page 18 Art Unit: 2176 Application/Control Number: 18/463,557 Page 19 Art Unit: 2176 Application/Control Number: 18/463,557 Page 20 Art Unit: 2176 Application/Control Number: 18/463,557 Page 21 Art Unit: 2176 Application/Control Number: 18/463,557 Page 22 Art Unit: 2176 Application/Control Number: 18/463,557 Page 23 Art Unit: 2176 Application/Control Number: 18/463,557 Page 24 Art Unit: 2176 Application/Control Number: 18/463,557 Page 25 Art Unit: 2176 Application/Control Number: 18/463,557 Page 26 Art Unit: 2176 Application/Control Number: 18/463,557 Page 27 Art Unit: 2176 Application/Control Number: 18/463,557 Page 28 Art Unit: 2176 Application/Control Number: 18/463,557 Page 29 Art Unit: 2176 Application/Control Number: 18/463,557 Page 30 Art Unit: 2176 Application/Control Number: 18/463,557 Page 31 Art Unit: 2176 Application/Control Number: 18/463,557 Page 32 Art Unit: 2176 Application/Control Number: 18/463,557 Page 33 Art Unit: 2176 Application/Control Number: 18/463,557 Page 34 Art Unit: 2176 Application/Control Number: 18/463,557 Page 35 Art Unit: 2176 Application/Control Number: 18/463,557 Page 36 Art Unit: 2176 Application/Control Number: 18/463,557 Page 37 Art Unit: 2176 Application/Control Number: 18/463,557 Page 38 Art Unit: 2176
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