DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed June 8, 2026 has been entered. Claims 1-4 and 6-21 remain pending in the application. Applicant’s amendments to the specification and claims have overcome each and every objection previously presented in the Non-Final Office Action mailed March 6, 2026, with one exception outlined below.
The objection relating to improper trademarks in the specification and drawings has not been addressed by applicant’s amendments, and as applicant has not provided any arguments that the objection is not valid, the objection remains.
Response to Arguments
Applicant's arguments filed June 8, 2026 have been fully considered but they are not persuasive. Applicant argues, see pages 8-11, that previously presented prior art reference Okabe et al. (Patent Number US 10,892,720 B2), as cited by applicant, hereafter referred to as Okabe, fails to disclose “wherein a first collector of the first semiconductor device and a second collector of the second semiconductor device are connected to a same direct current (DC) voltage source or connected to two different DC voltage sources”, as recited by the independent claims. Examiner respectfully disagrees.
Applicant states that in Okabe, the collectors of the first and second semiconductor devices are driven by a variable control current that corresponds to the level control voltage Vramp. However, Okabe describes two operation modes in Col. 8, lines 27-44. The first operation mode corresponds to that described by the applicant, wherein the collectors are driven variably. However, in the second operation mode, enabled by modifying switch settings in the circuit of Okabe, the collectors of the first and second semiconductor devices are driven by a constant current and/or voltage source (Okabe, Col. 8, lines 39-44). Therefore, Okabe does disclose “wherein a first collector of the first semiconductor device and a second collector of the second semiconductor device are connected to a same direct current (DC) voltage source or connected to two different DC voltage sources”, and therefore, applicant’s arguments are unconvincing and the rejections of claims 1-4 and 6-21 remain.
Specification
The use of the terms “Wi-Fi®” (See Paragraph 65, line 15, Paragraph 75, line 5, and Paragraph 120, line 9, and Fig. 2, Element 262) and “BLUETOOTH®” (See Paragraph 75, line 5, and Fig. 2, Element 262), which are trade names or marks used in commerce, has been noted in this application. The terms should be accompanied by the generic terminology; furthermore the terms should be capitalized wherever they appear or, where appropriate, include a proper symbol indicating use in commerce such as ™, SM , or ® following the terms.
Although the use of trade names and marks used in commerce (i.e., trademarks, service marks, certification marks, and collective marks) are permissible in patent applications, the proprietary nature of the marks should be respected and every effort made to prevent their use in any manner which might adversely affect their validity as commercial marks.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 6-9 and 12-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Okabe.
Regarding claim 1, Okabe discloses:
A power amplifier driver (Okabe, Fig. 7, 80) comprising: a first driver stage (Fig. 7, 81); a second driver stage (Fig. 7, 82); a biasing component (Fig. 7, 84 and 85) including a first emitter follower circuit (Fig. 7, 84) and a second emitter follower circuit (Fig. 7, 85), the biasing component configured to receive a first source current from a first current source (Fig. 7, see connection between current Ib1 and elements 84 and 85), and to provide a first bias voltage to the first driver stage using the first emitter follower circuit (Col. 7, lines 38-39) and a second bias voltage to the second driver stage using the second emitter follower circuit (Col. 7, lines 39-41), the first bias voltage and the second bias voltage being based upon the first current source (Col. 8, lines 3-4); wherein the first emitter follower circuit includes a first semiconductor device (Fig. 7, see instance of 84d in first emitter follower circuit 84), and the second emitter follower circuit includes a second semiconductor device (Fig. 7, see instance of 84d in second emitter follower circuit 85); and wherein a first collector of the first semiconductor device and a second collector of the second semiconductor device are connected to a same direct current (DC) voltage source or connected to two different DC voltage sources (Col. 8, lines 39-44).
Regarding claim 2, Okabe further discloses:
wherein the first driver stage includes a first power amplification device (Okabe, Fig. 7, 81a) and the second driver stage includes a second power amplification device (Fig. 7, 82a).
Regarding claim 3, Okabe further discloses:
wherein the first bias voltage is provided to the first power amplification device (Okabe, Col. 7, lines 38-39), and the second bias voltage is provided to the second power amplification device (Col. 7, lines 39-41).
Regarding claim 4, Okabe further discloses:
further comprising a diode circuit (Okabe, Fig. 7, 84b and 84c) coupled to a common node between the first emitter follower circuit and the second emitter follower circuit (Fig. 7, see connection between emitter follower 84d of the first emitter follower circuit 84 and emitter follower 84d of the second emitter follower circuit 85 via node at emitter/base of diode transistor 84b), the diode circuit configured to receive the first source current from the first current source (Fig. 7, see connection between diode transistor 84b and current Ib1).
Regarding claim 6, Okabe further discloses:
wherein a first base of the first semiconductor device is coupled to the first source current (Okabe, Fig. 7, see connection between base of instance of 84d in 84 and Ib1), and a second base of the second semiconductor device is coupled to the first source current (Fig. 7, see connection between base of instance of 84d in 85 and Ib1).
Regarding claim 7, Okabe further discloses:
wherein a first emitter of the first semiconductor device is coupled to the first driver stage (Okabe, Fig. 7, see connection between emitter of instance of 84d in 84 to first driver stage 81), the first emitter providing the first bias voltage to the first driver stage (Col. 11, lines 29-33).
Regarding claim 8, Okabe further discloses:
wherein a second emitter of the second semiconductor device is coupled to the second driver stage (Okabe, Fig. 7, see connection between emitter of instance of 84d in 85 to second driver stage 82), the second emitter providing the second bias voltage to the second driver stage (Col. 11, lines 29-39).
Regarding claim 9, Okabe further discloses:
wherein the first emitter is coupled to the first driver stage via a first resistive element (Okabe, Fig. 7, see connection between emitter of instance of 84d in 84 and 81 via instance of resistor 84f in 84) having a first resistance value (Fig. 7, consider resistance of resistor 84f), and the second emitter is coupled to the second driver stage via a second resistive element (Fig. 7, see connection between emitter of instance of 84d in 85 and 82 via instance of resistor 84f in 85) having a second resistance value (Fig. 7, consider resistance of resistor 84f).
Regarding claim 12, Okabe further discloses:
wherein the first collector of the first semiconductor device is coupled to a first DC voltage source (Okabe, Col. 11, lines 20-28), and the second collector of the second semiconductor device is coupled to a second DC voltage source (Col. 11, lines 20-28).
Regarding claim 13, Okabe further discloses:
wherein the first collector of the first semiconductor device and the second collector of the second semiconductor device are coupled to the same DC voltage source (Okabe, Col. 11, lines 20-28).
Regarding claim 14, Okabe further discloses:
wherein a first output of the first driver stage is coupled to a first input of the second driver stage (Okabe, Fig. 7, see connection between output of 81 and input of 82).
Regarding claim 15, Okabe discloses:
A power amplifier (Okabe, Fig. 7, 80) comprising: a first driver stage (Fig. 7, 81); a second driver stage (Fig. 7, 82) coupled to the first driver stage (Fig. 7, see connection between 81 and 82); an output stage (Fig. 7, 83) coupled to the second driver stage (Fig. 7, see connection between 82 and 83); a biasing component (Fig. 7, 84 and 85) including a first emitter follower circuit (Fig. 7, 84) and a second emitter follower circuit (Fig. 7, 85), the biasing component configured to receive a first source current from a first current source (Fig. 7, see connection between current Ib1 and elements 84 and 85), and provide a first bias voltage to the first driver stage using the first emitter follower circuit (Col. 7, lines 38-39) and a second bias voltage to the second driver stage using the second emitter follower circuit (Col. 7, lines 39-41), the first bias voltage and the second bias voltage being based upon the first current source (Col. 8, lines 3-4); wherein the first emitter follower circuit includes a first semiconductor device (Fig. 7, see instance of 84d in first emitter follower circuit 84), and the second emitter follower circuit includes a second semiconductor device (Fig. 7, see instance of 84d in second emitter follower circuit 85); and wherein a first collector of the first semiconductor device and a second collector of the second semiconductor device are connected to a same direct current (DC) voltage source or connected to two different DC voltage sources (Col. 8, lines 39-44).
Regarding claim 16, Okabe further discloses:
wherein the output stage is configured to receive a third bias voltage from a second current source (Okabe, Col. 16, lines 38-40).
Regarding claim 17, Okabe further discloses:
wherein the first current source is different from the second current source (Okabe, Fig. 7, consider that Ib1 and Ib2 are difference current sources).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Okabe as applied to claim 9 above, and further in view of Gerard et al. (Patent Number US 6,472,937 B1), as cited by applicant, hereafter referred to as Gerard.
Regarding claim 10, Okabe fails to disclose:
wherein a first ratio of the first bias voltage to the second bias voltage is adjustable based upon a second ratio of the first resistance value and the second resistance value.
However, Gerard teaches wherein a first ratio of the first bias voltage to the second bias voltage is adjustable based upon a second ratio of the first resistance value and the second resistance value (Gerard, Col. 4, lines 13-20).
Okabe and Gerard are both considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Okabe to incorporate the teachings of Gerard to include the resistors of Gerard in the circuit of Okabe, which would have the effect of providing control over the bias voltages of Okabe (Gerard, Col. 4, lines 13-20).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Okabe in view of Gerard as applied to claim 10 above, and further in view of Hitoshi et al. (Patent Publication Number JP 2005/020383 A), hereafter referred to as Hitoshi.
Regarding claim 11, Okabe and Gerard fail to disclose:
wherein the first ratio of the first bias voltage to the second bias voltage is further adjustable based upon a third ratio of a first emitter size of the first emitter follower circuit to a second emitter size of the second emitter follower circuit.
However, Hitoshi teaches wherein the first ratio of the first bias voltage to the second bias voltage is further adjustable based upon a third ratio of a first emitter size of the first emitter follower circuit to a second emitter size of the second emitter follower circuit (Hitoshi, Paragraph 32, lines 7-9).
Okabe, Gerard, and Hitoshi are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Okabe to incorporate the teachings of Hitoshi to modify the bias voltages of Okabe based on the emitter sizes of the transistors of Okabe, which would have the effect of enabling additional control over the bias voltages of Okabe (Hitoshi, Paragraph 32, lines 7-9).
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Okabe in view of Luther et al. (Patent Number CA 2,235,019 C), hereafter referred to as Luther.
Regarding claim 18, Okabe discloses:
A device (Okabe, Fig. 7, 80) comprising: a power amplifier (Fig. 7, 80), the power amplifier including a first driver stage (Fig. 7, 81) and a second driver stage (Fig. 7, 82); a first current source (Fig. 7, Ib1); a biasing component (Fig. 7, 84 and 85) including a first emitter follower circuit (Fig. 7, 84) and a second emitter follower circuit (Fig. 7, 85), the biasing component configured to receive a first source current from the first current source (Fig. 7, see connection between current Ib1 and elements 84 and 85), and provide a first bias voltage to the first driver stage using the first emitter follower circuit (Col. 7, lines 38-39) and a second bias voltage to the second driver stage using the second emitter follower circuit (Col. 7, lines 39-41) based upon the first current source (Col. 8, lines 3-4); wherein the first emitter follower circuit includes a first semiconductor device (Fig. 7, see instance of 84d in first emitter follower circuit 84), and the second emitter follower circuit includes a second semiconductor device (Fig. 7, see instance of 84d in second emitter follower circuit 85); and wherein a first collector of the first semiconductor device and a second collector of the second semiconductor device are connected to a same direct current (DC) voltage source or connected to two different DC voltage sources (Col. 8, lines 39-44), but fails to disclose a transceiver; [the power amplifier] coupled to the transceiver.
However Luther teaches a transceiver (Luther, Page 2, lines 4-5); [the power amplifier] coupled to the transceiver (Page 2, lines 1-6).
Okabe and Luther are both considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Okabe to incorporate the teachings of Luther to include the transceiver of Luther in the circuit of Okabe, which would have the effect of providing a well-known usage for the power amplifier of Okabe (Luther, Page 2, lines 1-6).
Regarding claim 19, Okabe further discloses:
wherein the first driver stage includes a first power amplification device (Okabe, Fig. 7, 81a) and the second driver stage includes a second power amplification device (Fig. 7, 82a).
Regarding claim 20, Okabe further discloses:
wherein the first bias voltage is provided to the first power amplification device (Okabe, Col. 7, lines 38-39), and the second bias voltage is provide to the second power amplification device (Col. 7, lines 39-41).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Okabe as applied to claim 1 above, and further in view of Kazuhiko et al. (Patent Publication Number JP 2006/166089 A), hereafter referred to as Kazuhiko, and Ishihara et al. (Patent Number US 10,153,737 B2), as cited by applicant, hereafter referred to as Ishihara.
Regarding claim 21, Okabe further discloses:
wherein a third base of the first semiconductor device is coupled to the first source current via a fifth resistive element (Okabe, Fig. 7, see connection between instance of 84d in bias circuit 84 coupled to Ib1 via resistor 84a), and wherein an output of the first driver stage is coupled to an input of the second driver stage via a matching network and a capacitor (Fig. 7, see connection between output of first driver stage 81 and input of second driver stage 82 via matching network capacitor 90), but fails to disclose wherein a first emitter of the first semiconductor device is coupled to the first driver stage via a first resistive element and a second resistive element connected in series, the second resistive element coupled to a first base of the first driver stage, a second emitter of the second semiconductor device is coupled to the second driver stage via a third resistive element and a fourth resistive element connected in series, and the fourth resistive element coupled to a second base of the second driver stage, and a fourth base of the second semiconductor device is coupled to the first source current without an intervening resistive element.
However, Kazuhiko teaches wherein a first emitter of the first semiconductor device is coupled to the first driver stage via a first resistive element and a second resistive element connected in series (Kazuhiko, Fig. 1, see connection between emitter of Qb1 and base of Q1 via two resistors in series including resistor R1), the second resistive element coupled to a first base of the first driver stage (Fig. 1, see connection between R1 and base of Q1), a second emitter of the second semiconductor device is coupled to the second driver stage via a third resistive element and a fourth resistive element connected in series (Fig. 1, see connection between emitter of Qb1 and base of Qn via two resistors in series including resistor Rn), and the fourth resistive element coupled to a second base of the second driver stage (Fig. 1, see connection between Rn and base of Qn), but fails to teach and a fourth base of the second semiconductor device is coupled to the first source current without an intervening resistive element.
However, Ishihara teaches and a fourth base of the second semiconductor device is coupled to the first source current without an intervening resistive element (Ishihara, Fig. 1, see connection between base of Tr32 and current source 60 lacking an intervening resistive element).
Okabe, Kazuhiko, and Ishihara are all considered to be analogous to the claimed invention because they are in the same field of improving power amplifiers used in radio frequency communications. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Okabe to incorporate the teachings of Kazuhiko and Ishihara to include the series resistors of Kazuhiko in the circuit of Okabe, which would have the effect of improving the amplification capabilities of the circuit of Okabe (Kazuhiko, Page 5, Paragraph 7, lines 1-6), and to include the direct path of Ishihara in the circuit of Okabe, which would have the effect of an effective biasing method to the circuit of Okabe that reduces required circuit components (Ishihara, Col. 10, lines 37-56).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Hirobe (Patent Publication Number US 2023/0073635 A1) discloses (Fig. 2) a multistage power amplifier with a common biasing circuit.
Ishimaru et al. (Patent Publication Number US 2008/0186099 A1) discloses (Fig. 22) a multistage power amplifier with a common biasing circuit.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lance T Bartol whose telephone number is (703)756-1267. The examiner can normally be reached Monday - Thursday 6:30 a.m. - 4:00 p.m. CT, Alternating Fridays 6:30 - 3:00.
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/LANCE TORBJORN BARTOL/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843
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