Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/8/2023 is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97.
Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 16 – 35 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by McLaren (US 10211785 B2).
Regarding Independent Claim 16, McLaren teaches,
A Doherty power amplifier device (Fig. 3, 300) comprising:
an input (Fig. 3, 202);
a power divider (Fig. 3, 210) coupled to the input (Fig. 3, 202) and configured to divide an input signal (Fig. 3, signal at 202) received from the input into a first signal (Fig. 3, signal at 214) and a second signal (Fig. 3, signal at 216);
a carrier amplification path (Fig. 3, 330) configured to receive the first signal (Fig. 3, signal from 214), the carrier amplification path (Fig. 3, 330) comprising:
a carrier amplifier (Fig. 3, 236) configured to amplify the first signal to produce a first amplified signal (Fig. 3, signal from 236); and
phase slope adjustment circuitry (Fig. 3, 332, 333, 336, 337, 338, and 339) coupled between the power divider (Fig. 3, 210) and the carrier amplifier (Fig. 3, 236), wherein the phase slope adjustment circuitry (Fig. 3, 332, 333, 336, 337, 338, and 339) is configured to adjust a phase-dependent slope of a phase of the first signal (Fig. 3, signal from 214), the phase slope adjustment circuitry (Fig. 3, 332, 333, 336, 337, 338, and 339) comprising at least one resonant circuit (See Fig. 3. See column 3, lines 7 – 28, “The compensation circuit embodiments discussed herein correct, negate, and equalize the group delay response of an output circuit, and also may optimize the load impedance dispersion characteristics of the main and peaking amplifiers in the full power region in which the peaking device is active. The compensation circuit embodiments may be specifically designed to reduce peak power dispersion. In addition, the compensation circuit embodiments may maximize utilization of a Doherty power amplifier in the full power region, while also enabling higher efficiency operation at a fixed output power back-off level.
The compensation circuit embodiments described herein may have improved power handling capability over other input circuits that may use lumped LCR (inductor/capacitor/resistor) elements. In addition, the overall circuit losses may be reduced, when compared with Doherty amplifiers that do not include embodiments of the compensation circuits. Further, the compensation circuit embodiments may be implemented without the use of an active control circuit, thereby avoiding the additional cost, complexity, and bandwidth limitation that may be associated with such an active control circuit.”);
a peaking amplification path (Fig. 3, 340) configured to receive the second signal (Fig. 3, signal from 216), the peaking amplification path (Fig. 3, 340) comprising:
a peaking amplifier (Fig. 3, 246) configured to amplify the second signal to produce a second amplified signal (Fig. 3, signal from 246); and
a combining node (Fig. 3, 260) configured to combine first amplified signal and the second amplified signal to produce an output signal (Fig. 3, combined signal from 330 and 340).
Regarding claim 17,
The Doherty power amplifier (Fig. 3, 300) device of claim 16, wherein the phase slope adjustment circuitry (Fig. 3, 332, 333, 336, 337, 338, and 339) comprises:
an input node (Fig. 3, node at 214);
a first capacitor (Fig. 3, part of 332. See column 3, lines 18 – 21, “The compensation circuit embodiments described herein may have improved power handling capability over other input circuits that may use lumped LCR (inductor/capacitor/resistor) elements.21”);
a first inductor (Fig. 3, part of 332. See column 3, lines 18 – 21, “The compensation circuit embodiments described herein may have improved power handling capability over other input circuits that may use lumped LCR (inductor/capacitor/resistor) elements.21”);
an intermediate node (Fig. 3, node between 332 and 333), wherein the first capacitor and the first inductor are coupled in series between the input node and the intermediate node;
a second capacitor (Fig. 3, part of 333. See column 3, lines 18 – 21, “The compensation circuit embodiments described herein may have improved power handling capability over other input circuits that may use lumped LCR (inductor/capacitor/resistor) elements.21”);
a second inductor (Fig. 3, part of 333. See column 3, lines 18 – 21, “The compensation circuit embodiments described herein may have improved power handling capability over other input circuits that may use lumped LCR (inductor/capacitor/resistor) elements.21”);
an output node (Fig. 3, node between 333 and 234), wherein the second capacitor and the second inductor are coupled in series between the intermediate node and the output node;
a third capacitor (Fig. 3, part of 338. See column 3, lines 18 – 21, “The compensation circuit embodiments described herein may have improved power handling capability over other input circuits that may use lumped LCR (inductor/capacitor/resistor) elements.21”); and
a third inductor (Fig. 3, part of 338. See column 3, lines 18 – 21, “The compensation circuit embodiments described herein may have improved power handling capability over other input circuits that may use lumped LCR (inductor/capacitor/resistor) elements.21”), wherein the third capacitor and the third inductor are coupled together in parallel between the intermediate node and a reference potential (Fig. 3, 338 is between the node between 332 and 333 and ground).
Regarding claim 18,
The Doherty power amplifier device (Fig. 3, 300) of claim 17, wherein the first inductor (Fig. 3, part of 332) has a first inductance (Fig. 3, inductance of 332) that is within 10% of a second inductance (Fig. 3, inductance of 333) of the second inductor (Fig. 3, part of 333), the first capacitor (Fig. 3, part of 332) has a first capacitance (Fig. 3, capacitance of 332) that is within 10% of a second capacitance (Fig. 3, capacitance of 333) of the second capacitor (Fig. 3, part of 333).
Regarding claim 19,
The Doherty power amplifier device (Fig. 3, 300) of claim 18, wherein the phase slope adjustment circuitry (Fig. 3, 332, 333, 336, 337, 338, and 339) has a substantially linear phase response over a power frequency band of the Doherty power amplifier device (See column 9, lines 16 – 27, “At low power levels, where the power of the input signal at node 202 is lower than the turn-on threshold level of peaking amplifier 246, the amplifier 200 operates in a low-power (or back-off) mode in which the main amplifier 236 is the only amplifier supplying current to the load 206. When the power of the input signal exceeds a threshold level of the peaking amplifier 246, the amplifier 200 operates in a high-power mode in which the main amplifier 236 and the peaking amplifier 246 both supply current to the load 206. At this point, the peaking amplifier 246 provides active load modulation at combining node 260, allowing the current of the main amplifier 236 to continue to increase linearly.”).
Regarding claim 20,
The Doherty power amplifier device (Fig. 3, 300) of claim 19, wherein an insertion phase of the phase slope adjustment circuitry is 0 degrees at a center frequency of the Doherty power amplifier device (The insertion phase of the phase slope adjustment circuitry can be configured to be 0 degrees. See column 9, lines 52 – 58, “As with amplifier 100, Doherty amplifier 200 has an inverted load network configuration. In the inverted configuration, the input circuit is configured so that an input signal supplied to the main amplifier 236 is delayed by about 90 degrees with respect to the input signal supplied to the peaking amplifier 246 at the center frequency of operation, fo, of the amplifier 200.”).
Regarding claim 21,
The Doherty power amplifier device (Fig. 3, 300) of claim 17, wherein the phase slope adjustment circuitry (Fig. 3, 332, 333, 336, 337, 338, and 339) has a frequency response corresponding to a constant-k bandpass filter (The phase slope adjustment circuitry is part of the compensation circuit that functions include to correct, negate, and equalize the frequency response. See Fig. 3. See column 3, lines 7 – 28, “The compensation circuit embodiments discussed herein correct, negate, and equalize the group delay response of an output circuit, and also may optimize the load impedance dispersion characteristics of the main and peaking amplifiers in the full power region in which the peaking device is active.).
Regarding claim 22,
The Doherty power amplifier device (Fig. 3, 300) of claim 21, wherein a center frequency of the Doherty power amplifier device is between 2 GHz and 2.5 GHz (The power amplifier device can be configured to meet any desired frequency range. See column 3, lines 24 – 28, “Further, the compensation circuit embodiments may be implemented without the use of an active control circuit, thereby avoiding the additional cost, complexity, and bandwidth limitation that may be associated with such an active control circuit.”).
Regarding claim 23,
The Doherty power amplifier device (Fig. 3, 300) of claim 22, wherein a peak power of the Doherty power amplifier device is between 48 and 52 dBm, and an output power ripple of the Doherty power amplifier device is less than 0.2 dBm in a full power state (See column 20, lines 10 – 20, “As can be seen from FIG. 6, the inclusion of an embodiment of a phase compensation circuit in a Doherty amplifier may result in a reduction of peak power dispersion. For example, a comparison of plots 601 and 603 indicates a reduction of peak power dispersion from about 1.04 dB for conventional amplifier A (i.e., about 57.65 dBm minus about 56.61 dBm in region 614) to about 0.50 dB (i.e., about 57.61 dBm minus about 57.11 dBm in region 634) for compensated amplifier C. This represents about 0.5 dB of improvement in utilization of such a wideband Doherty power amplifier.”).
Regarding claim 24,
The Doherty power amplifier device of claim 23, wherein a quality factor of the phase slope adjustment circuitry is between 0.3 and 0.4 (The phase slope adjustment circuitry can be configured to meet any desired quality factor. See column 3, lines 24 – 28, “Further, the compensation circuit embodiments may be implemented without the use of an active control circuit, thereby avoiding the additional cost, complexity, and bandwidth limitation that may be associated with such an active control circuit.”).
Regarding claim 25,
The Doherty power amplifier device (Fig. 3, 300) of claim 24, wherein a bandwidth of the Doherty power amplifier device is between 850 MHz and 950 MHz (The bandwidth can be configured to meet any desired frequency range. See column 3, lines 24 – 28, “Further, the compensation circuit embodiments may be implemented without the use of an active control circuit, thereby avoiding the additional cost, complexity, and bandwidth limitation that may be associated with such an active control circuit.”).
Regarding Independent claim 26,
An amplifier device (Fig. 3, 300) comprising:
a power divider (Fig. 3, 210) configured to receive an input signal (Fig. 3, signal at 202) and divide the input signal into a first signal (Fig. 3, signal at 214) and a second signal (Fig. 3, signal at 216);
a first amplification path (Fig. 3, 330) comprising:
a first amplifier (Fig. 3, 236) configured to amplify the first signal to produce a first amplified signal (Fig. 3, signal from 236); and
a phase slope adjustment circuitry (Fig. 3, 332, 333, 336, 337, 338, and 339) coupled between the power divider (Fig. 3, 210) and the first amplifier (Fig. 3, 236), wherein the phase slope adjustment circuitry (Fig. 3, 332, 333, 336, 337, 338, and 339) is configured to adjust a phase-dependent slope of a phase of the first signal, the phase slope adjustment circuitry (Fig. 3, 332, 333, 336, 337, 338, and 339) comprising at least one resonant circuit (See Fig. 3. See column 3, lines 7 – 28, “The compensation circuit embodiments discussed herein correct, negate, and equalize the group delay response of an output circuit, and also may optimize the load impedance dispersion characteristics of the main and peaking amplifiers in the full power region in which the peaking device is active. The compensation circuit embodiments may be specifically designed to reduce peak power dispersion. In addition, the compensation circuit embodiments may maximize utilization of a Doherty power amplifier in the full power region, while also enabling higher efficiency operation at a fixed output power back-off level.
The compensation circuit embodiments described herein may have improved power handling capability over other input circuits that may use lumped LCR (inductor/capacitor/resistor) elements. In addition, the overall circuit losses may be reduced, when compared with Doherty amplifiers that do not include embodiments of the compensation circuits. Further, the compensation circuit embodiments may be implemented without the use of an active control circuit, thereby avoiding the additional cost, complexity, and bandwidth limitation that may be associated with such an active control circuit.”);
a second amplification path (Fig. 3, 340) comprising:
a second amplifier (Fig. 3, 246) configured to amplify the second signal to produce a second amplified signal (Fig. 3, signal from 246);
and a combining node (Fig. 3, 260) configured to combine first amplified signal and the second amplified signal to produce an output signal (Fig. 3, combined signal from 330 and 340).
Regarding claim 27,
The amplifier device (Fig. 3, 300) of claim 26, wherein the phase slope adjustment circuitry (Fig. 3, 332, 333, 336, 337, 338, and 339) comprises a bandpass filter (The phase slope adjustment circuitry is part of the compensation circuit that functions include to correct, negate, and equalize the frequency response. See Fig. 3. See column 3, lines 7 – 28, “The compensation circuit embodiments discussed herein correct, negate, and equalize the group delay response of an output circuit, and also may optimize the load impedance dispersion characteristics of the main and peaking amplifiers in the full power region in which the peaking device is active.).
Regarding claim 28,
The amplifier device (Fig. 3, 300) of claim 27, wherein the bandpass filter of the phase slope adjustment circuitry (Fig. 3, 332, 333, 336, 337, 338, and 339) comprises:
an input node (Fig. 3, node at 214);
a first capacitor (Fig. 3, part of 332. See column 3, lines 18 – 21, “The compensation circuit embodiments described herein may have improved power handling capability over other input circuits that may use lumped LCR (inductor/capacitor/resistor) elements.21”);
a first inductor (Fig. 3, part of 332. See column 3, lines 18 – 21, “The compensation circuit embodiments described herein may have improved power handling capability over other input circuits that may use lumped LCR (inductor/capacitor/resistor) elements.21”);
an intermediate node (Fig. 3, node between 332 and 333), wherein the first capacitor and the first inductor are coupled in series between the input node and the intermediate node;
a second capacitor (Fig. 3, part of 333. See column 3, lines 18 – 21, “The compensation circuit embodiments described herein may have improved power handling capability over other input circuits that may use lumped LCR (inductor/capacitor/resistor) elements.21”);
a second inductor (Fig. 3, part of 333. See column 3, lines 18 – 21, “The compensation circuit embodiments described herein may have improved power handling capability over other input circuits that may use lumped LCR (inductor/capacitor/resistor) elements.21”);
an output node (Fig. 3, node between 333 and 234), wherein the second capacitor and the second inductor are coupled in series between the intermediate node and the output node;
a third capacitor (Fig. 3, part of 338. See column 3, lines 18 – 21, “The compensation circuit embodiments described herein may have improved power handling capability over other input circuits that may use lumped LCR (inductor/capacitor/resistor) elements.21”); and
a third inductor (Fig. 3, part of 338. See column 3, lines 18 – 21, “The compensation circuit embodiments described herein may have improved power handling capability over other input circuits that may use lumped LCR (inductor/capacitor/resistor) elements.21”), wherein the third capacitor and the third inductor are coupled together in parallel between the intermediate node and a reference potential (Fig. 3, 338 is between the node between 332 and 333 and ground).
Regarding claim 29,
The amplifier device (Fig. 3, 300) of claim 28, wherein the first inductor has a first inductor (Fig. 3, part of 332) has a first inductance (Fig. 3, inductance of 332) that is within 10% of a second inductance (Fig. 3, inductance of 333) of the second inductor (Fig. 3, part of 333), the first capacitor (Fig. 3, part of 332) has a first capacitance (Fig. 3, capacitance of 332) that is within 10% of a second capacitance (Fig. 3, capacitance of 333) of the second capacitor (Fig. 3, part of 333).
Regarding claim 30,
The amplifier device (Fig. 3, 300) of claim 27, wherein the bandpass filter of the phase slope adjustment circuitry (Fig. 3, 332, 333, 336, 337, 338, and 339) has a substantially linear phase response over a power frequency band of the Doherty power amplifier device (See column 9, lines 16 – 27, “At low power levels, where the power of the input signal at node 202 is lower than the turn-on threshold level of peaking amplifier 246, the amplifier 200 operates in a low-power (or back-off) mode in which the main amplifier 236 is the only amplifier supplying current to the load 206. When the power of the input signal exceeds a threshold level of the peaking amplifier 246, the amplifier 200 operates in a high-power mode in which the main amplifier 236 and the peaking amplifier 246 both supply current to the load 206. At this point, the peaking amplifier 246 provides active load modulation at combining node 260, allowing the current of the main amplifier 236 to continue to increase linearly.”).
Regarding claim 31,
The amplifier device (Fig. 3, 300) of claim 29, wherein an insertion phase of the bandpass filter of the phase slope adjustment circuitry is 0 degrees at a center frequency of the amplifier device (The insertion phase of the phase slope adjustment circuitry can be configured to be 0 degrees. See column 9, lines 52 – 58, “As with amplifier 100, Doherty amplifier 200 has an inverted load network configuration. In the inverted configuration, the input circuit is configured so that an input signal supplied to the main amplifier 236 is delayed by about 90 degrees with respect to the input signal supplied to the peaking amplifier 246 at the center frequency of operation, fo, of the amplifier 200.”).
Regarding claim 32,
The amplifier device (Fig. 3, 300) of claim 27, wherein a center frequency of the amplifier device is between 2 GHz and 2.5 GHz (The power amplifier device can be configured to meet any desired frequency range. See column 3, lines 24 – 28, “Further, the compensation circuit embodiments may be implemented without the use of an active control circuit, thereby avoiding the additional cost, complexity, and bandwidth limitation that may be associated with such an active control circuit.”).
Regarding claim 33,
The amplifier device (Fig. 3, 300) of claim 27, wherein a peak power of the amplifier device is between 48 and 52 dBm, and an output power ripple of the amplifier device is less than 0.2 dBm in a full power state (See column 20, lines 10 – 20, “As can be seen from FIG. 6, the inclusion of an embodiment of a phase compensation circuit in a Doherty amplifier may result in a reduction of peak power dispersion. For example, a comparison of plots 601 and 603 indicates a reduction of peak power dispersion from about 1.04 dB for conventional amplifier A (i.e., about 57.65 dBm minus about 56.61 dBm in region 614) to about 0.50 dB (i.e., about 57.61 dBm minus about 57.11 dBm in region 634) for compensated amplifier C. This represents about 0.5 dB of improvement in utilization of such a wideband Doherty power amplifier.”).
Regarding claim 34,
The amplifier device (Fig. 3, 300) of claim 27, wherein a quality factor of the bandpass filter of the phase slope adjustment circuitry is between 0.3 and 0.4 (The phase slope adjustment circuitry can be configured to meet any desired quality factor. See column 3, lines 24 – 28, “Further, the compensation circuit embodiments may be implemented without the use of an active control circuit, thereby avoiding the additional cost, complexity, and bandwidth limitation that may be associated with such an active control circuit.”).
Regarding claim 35,
The amplifier device (Fig. 3, 300) of claim 27, wherein a bandwidth of the amplifier device is between 850 MHz and 950 MHz (The bandwidth can be configured to meet any desired frequency range. See column 3, lines 24 – 28, “Further, the compensation circuit embodiments may be implemented without the use of an active control circuit, thereby avoiding the additional cost, complexity, and bandwidth limitation that may be associated with such an active control circuit.”).
Conclusion
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/JOSE E PINERO/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843