DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 8-10 and 12-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Garcia et al. [US 2022/0101085 A1] in view of Himebaugh et al. [US 2016/0328642 A1]. Claim 8 is rejected over Garcia and Himebaugh. Garcia teaches “ A temperature-resilient neural network training architecture, comprising: a nonvolatile memory comprising a plurality of layered subarrays, wherein each subarray comprises 256 rows and 256 columns of nonvolatile memory cells; ” as “ a non-volatile memory (NVM) crossbar is provided that includes a plurality of row signal lines configured to receive input analog voltage signals ” [ ¶0020 ] ( The analog signal can be tem p erature data ) “ a fixed-point computing unit configured to perform the batch normalization. ” as “ The fully-connected layers follow the convolutional and pooling layers, and include a flatten layer and a classification layer, followed by a normalization layer that includes a normalization function, such as the SoftMax function. ” [ ¶0030 ] Garcia does not explicitly teach a converter configured to digitize the analog temperature; a multiplexer connected to the converter and configured to select, from a global buffer, a set of batch normalization parameters as a function of the digitized analog temperature; and However, Himebaugh teaches “ a converter configured to digitize the analog temperature; ” as “ an analog signal that was converted from a digital signal output by a digital sensor (e.g., the digital sensor 104 of FIG. 1) ” [ ¶0051 ] “ a multiplexer connected to the converter and configured to select, from a global buffer, a set of batch normalization parameters as a function of the digitized analog temperature; and ” as “ FIG. 2 depicts a multiplexer 128 and inputs 130 of the analog neural network 106 that were described above in FIG. 1 ” [ ¶0050 ] Garcia and Himebaugh are analogous arts because they teach memory system and neural network. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Garcia and Himebaugh before him/her, to modify the teachings of Garcia to include the teachings of Himebaugh with the motivation of it is sometimes advantageous for the analog neural network to be operating while the digital processor is in a lower-power state . [ Himebaugh , ¶0026] Claim 9 is rejected over Garcia and Himebaugh. Garcia teaches “ wherein the nonvolatile memory comprises a random-access memory. ” as “ Typical NVM elements, such as, for example, PCM and RRAM ” [¶0058] Claim 10 is rejected over Garcia and Himebaugh. Garcia teaches “ wherein the nonvolatile memory is a resistive random-access memory. ” as “ Typical NVM elements, such as, for example, PCM and RRAM ” [¶0058] Claim 12 is rejected over Garcia and Himebaugh. Garcia teaches “ wherein the converter is an analog-to-digital converter. ” as “ an NVM crossbar module includes digital-to-analog converters (DACs), analog-to-digital converters (ADCs), and an NVM crossbar with an array of NVM cells. ” [¶0056] Claim 13 is rejected over Garcia and Himebaugh. Garcia does not explicitly teach further comprising a flash converter connected to a plurality of sense amplifiers. However, Himebaugh teaches “ further comprising a flash converter connected to a plurality of sense amplifiers. ” as “ If the analog neural network 106 determines an event of interest has been sensed by the sensors 102, 104, the analog signal output by the analog neural network 106 is sent to the digital processor 108 ” [¶0032] Claim 14 is rejected over Garcia and Himebaugh. Garcia does not explicitly teach wherein the fixed-point computing unit is configured to perform a fixed-point batch normalization computation from a plurality of sets. However, Himebaugh teaches “ wherein the fixed-point computing unit is configured to perform a fixed-point batch normalization computation from a plurality of sets. ” as “ If the analog neural network 106 determines an event of interest has been sensed by the sensors 102, 104, the analog signal output by the analog neural network 106 is sent to the digital processor 108 ” [¶0032] Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Garcia et al. [US 2022/0101085 A1] in view of Himebaugh et al. [US 2016/0328642 A1] and in further view of Kumar et al. [US 2019/0303750 A1] . Claim 11 is rejected over Garcia, Himebaugh and Kumar. The combination of Garcia and Himebaugh does not explicitly teach wherein each nonvolatile memory cell stores 2 bits. However, Kumar teaches “wherein each nonvolatile memory cell stores 2 bits.” as “ the NVM device can comprise a block addressable memory device, such as NAND technologies, or more specifically, multi-threshold level NAND flash memory (for example, Single-Level Cell (“SLC”), Multi-Level Cell (“MLC”), Quad-Level Cell (“QLC”), Tri-Level Cell (“TLC”), or some other NAND). ” [0057] Garcia, Himebaugh and Kumar are analogous arts because they teach memory system and neural network. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Garcia, Himebaugh and Kumar before him/her, to modify the teachings of combination of Garcia and Himebaugh to include the teachings of Kumar with the motivation of storing more data in limited amount of memory. Allowable Subject Matter The following is an examiner’s statement of reasons for allowance: Claim 1 recites – “ injecting, now using the student model as the teacher model, high temperature noises to an inherited student model ; and training the deep neural network model, while the model remains fixed, using a batch normalization adaptation algorithm, wherein the batch normalization adaptation algorithm includes training a plurality of batch normalization parameters with respect to a plurality of thermal variations. ” Closest prior art Yang et al. [ CN 111126599 A ] appears to teach a teacher-student model, wherein the teacher-student model comprises a student model and a teacher model, and the trained feedforward neural network model is respectively used as the teacher model and the student model; inputting the enhanced first group of target domain data to the teacher model to obtain the pseudo label of the sample data of each user . However, none of the prior arts of record teaches injecting using the student model as the teacher model, high temperature noises to an inherited student model and other recited features of this limitation. Therefore, claim 1 and its dependent claims 2-7 are allowed. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT MASUD K KHAN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-0606 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday-Friday (8am-5pm) . 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Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MASUD K KHAN/ Primary Examiner, Art Unit 2132