Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1- 30 are pending in the application under prosecution and have been examined. The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. The specification should be amended to reflect the status of all related application, whether patented or abandoned. Therefore, applications noted by their serial number and/or attorney docket number should be updated with correct serial number and patent number if patented. The first instance of all acronyms or abbreviation should be spelled out for clarity, whether or not considered well known in the art. In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application. 37 C.F.R. § 1.83(a) requires the Drawings to illustrate or show all claimed features. Applicant must clearly point out the patentable novelty that they think the claims present, in view of the state of the art disclosed by the references cited or the objections made, and must also explain how the amendments avoid the references or objections. See 37 C.F.R. § 1.111(c). Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claims 1- 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1, it recites the limitation " modification component that replaces a first channel of an initial quantum circuit with a second channel that represents the first channe l ". The feature “ replaces a first channel of an initial quantum circuit with a second channel that represents the first channel “ is unclear such that the rest of the claim features element of the first channel and the second channel . Claims 2- 8 are rejected for being dependent upon the rejected based claim. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim s 1- 6 , 9-1 2 , and 15-1 8 are rejected under 35 U.S.C. 103 as being unpatentable over US 20170308803 A1 (WALLMAN et al) ] in view of US 20220188682 A1 (VAN DEN BERG et al). With respect to claim 1, WALLMAN ( US 20170308803 A1 ) ) teaches computer-implemented method, comprising: replacing, by a system operatively coupled to a processor, a first channel of an initial quantum circuit with a second channel that represents the first channel; inserting, by the system, into the initial quantum circuit a pair of Pauli gates bounding the second channel, resulting in a modified quantum circuit ( method Pauli-Random-Error-Correction (PAREC) to eliminate static coherent errors involving changing multi-qubit gates in each step of the computation , using: r andom gates be effectively inserted in the initial quantum-logic gate sequence and combined with the quantum-logic gates to form a new, modified quantum-logic gate sequence (i.e., the modified quantum-logic gate sequence generated by applying random gates to the initial quantum-logic gate sequence ); the modified quantum-logic gate sequence from quantum-logic source code converted in to machine code to be executed by the quantum information processor , i.e., modified quantum-logic gate sequence can be provided to a quantum information processor for execution ) [ Par. 0038- 0041 ; Par. 0114-0117] . WALLMAN fails to specifically teach the pair of Pauli gates are based on Pauli transfer matrix elements of the first channel and the second channel. H owever, VAN DEN BERG teaches system comprises a memory that stores and a processor that executes computer executable components stored in the memory, wherein the computer executable components comprise an identification component that identifies a quantum channel within a quantum circuit that is configured for execution at a quantum processor, an evaluation component that generates a reshaped quantum channel based on application of quantum twirling to the quantum channe l using Pauli transfer matrix having noise attributable to each element of the matrix such that the reshaped quantum twirling employed for a readout quantum circuit, such as relative to a readout-error mitigation process) [ Abstract; Par. 0011-0012 ; Par. 0027-0029 ; Par. 0135] . Therefore it would have been obvious to one having at least ordinary skill in the art, before the effective filing of the instant application to combine the insertion of gates to the initial quantum-logic gate sequence , as taught by WALLMAN, with the a pplication of quantum twirling to the quantum channel using Pauli transfer matrix , as taught by VANDEN BERG, that in order to efficiently and accurately estimate quantum-computing readout results that perform operations that can be executed in an efficient and less complex manner , as taught by VAN DEN BERG [Par. 0012] . The combination is proper because VAN DEN BERG teaches the system to facilitate desirably mitigating error in readout results in a quick and efficient manner, the system to comprise a readout management component (RMC) that can be associated with (e.g., communicatively connected to) the quantum computer component where t he RMC can desirably (e.g., efficiently, quickly, and optimally) manage the production of readout results to mitigate (e.g., reduce or minimize) readout errors [Par. 0033] . With respect to claim s 2 , 10 , and 16, WALLMAN and VAN DEN BERG , combined teach t he system, wherein the measurement outcome of the execution of the modified quantum circuit from the quantum processor is error mitigated as compared to an execution of the initial quantum circuit prior to replacement of the first channel [VAN DEN BERG’s Par. 0028-0029; Par. 0083-0084] . With respect to claim s 3 , 11 , and 17, WALLMAN and VAN DEN BERG , combined teach the system , further comprising: a probability component that generates a probability based on the Pauli transfer matrix elements of the first channel and the second channel, wherein the pair of Pauli gates are selected based on the probability [VAN DEN BERG’s Par. 0083-0084] . With respect to claim s 4 , 12 , and 18 , WALLMAN and VAN DEN BERG , combined teach the system , further comprising: a selection component that, based on the Pauli transfer matrix elements of the first channel and the second channel, randomly selects the pair of Pauli gates, as a pair, within a set of probabilities for a group of pairs of Pauli gates, comprising the pair of Pauli gates [VAN DEN BERG’s Par. 0028-0029; Par. 0040-0043 ] . With respect to claim 5 , WALLMAN and VAN DEN BERG , combined teach the system, wherein the set of probabilities are individually based on elements of a quasi-probability matrix, and wherein each probability of the set of probabilities applies to a particular pair of the pairs of Pauli gates [VAN DEN BERG’s Par. 023-0024; Par. 00 48-0049; Par. 00 83-0084] . With respect to claim 6 , WALLMAN and VAN DEN BERG , combined teach the system, further comprising: a scaling component that, employing the measurement outcome of the execution of the modified quantum circuit from the quantum processor, determines an expectation value associated with the first channel by scaling the measurement outcome. [VAN DEN BERG’s Par. 00 0009-0012; Par. 00 0028-0029 ] Allowable Subject Matter Claims 7 -8, 13-14, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 11928004 B2 ( Earnest-Noble et al ) teaching system compris ing a processor, operably coupled to the memory to execute computer executable components stored in the memory , th e computer executable components compris ing an error mitigation component that can add a set of scaled quantum gates to a quantum circuit for error mitigation. US 20200184023 A1 (Delaney et al) teaching c omputer-implemented method includ ing: receiving one or more parameters for simulation of evolution of at least one quantum state of a chemical entity to be simulated; generating a quantum circuit for the simulation; performing one or more operations to minimize quantum resources to be used for the generated quantum circuit based on the one or more parameters . J. D. Guimarães and C. Tavares, "Towards a layered architecture for error mitigation in quantum computation," 2022 IEEE International Conference on Quantum Software (QSW), Barcelona, Spain, 2022, pp. 41-51. Berg, Ewout van den, “Single-shot error mitigation by coherent Pauli checks” arXiv.org, 12/07/2022 . R. Shaydulin and A. Galda, "Error Mitigation for Deep Quantum Optimization Circuits by Leveraging Problem Symmetries," 2021 IEEE International Conference on Quantum Computing and Engineering (QCE), Broomfield, CO, USA, 2021, pp. 291-300. N. Acharya and S. M. Saeed, "Automated Flag Qubit Insertion for Reliable Quantum Circuit Output," 2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, FL, USA, 2021, pp. 431-436. Henao, Ivan • Santos, Jader P. • Uzdin, Raam “Adaptive quantum error mitigation using pulse-based inverse evolutions,” arXiv.org, 2023-03-08. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT PIERRE MICHEL BATAILLE whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-4178 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday - Thursday 7-6 ET . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PIERRE MICHEL BATAILLE/ Primary Examiner, Art Unit 2138