Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 and 17-27 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “wherein a quantity of bits comprised in the first bit sequence is greater than or equal to zero, and a quantity of bits comprised in the second bit sequence is greater than or equal to zero.” However, nothing in the claims describes how a quantity of bits equaling zero can be used in mapping to obtain another bit sequence or in performing polar transformation using zero bits. Indeed, if the quantity of bits in the bit sequences are zero, then all of the claim limitations are rendered meaningless. Therefore, the abovementioned limitation fails to reasonably apprise one of ordinary skill in the art of the scope of the invention. Accordingly, claim 1 is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. For examination purposes, the above limitation has been construed as “wherein a quantity of bits comprised in the first bit sequence is greater than zero, and a quantity of bits comprised in the second bit sequence is greater than zero.”
Claim 1 further recites “mapping the second bit sequence to obtain a third bit sequence.” However, nothing in the claims describes what process is performed on the second bit sequence when mapping the second bit sequence to obtain the third bit sequence. Therefore, the abovementioned limitation fails to reasonably apprise one of ordinary skill in the art of the scope of the invention. Accordingly, claim 1 is indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. For examination purposes, the above limitation has been construed as “mapping the second bit sequence to obtain the third bit sequence by performing probability shaping and polar transformation are respectively performed on the second bit sequence” based at least on paragraph [0008] of the specification.
Claim 17 recites similar limitations as the abovementioned limitations of claim 1, and for the same reasons, claim 17 also fails to reasonably apprise one of ordinary skill in the art of the scope of the invention. Accordingly, claim 17 is also indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. The corresponding limitations in claim 17 are construed similarly as described above with respect to the limitations in claim 1.
Therefore, the abovementioned limitations fail to reasonably apprise one of ordinary skill in the art of the scope of the invention. Accordingly, claims are indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. For examination purposes, the abovementioned limitations have been construed a quantity of bits comprised in the first bit sequence is greater than or equal to one, and a quantity of bits comprised in the second bit sequence is greater than or equal to one.
Claims 2-10 and 18-27 depend from claims 1 and 17, respectively, and accordingly incorporate all of the limitations of claims 1 and 17. Therefore, for the reasons stated above for claims 1 and 17, claims 2-10 and 18-27 also fail to reasonably apprise one of ordinary skill in the art of the scope of the invention, and are indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Allowable Subject Matter
Claims 1-10 and 17-27 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
With regards to claims 1 and 17, Sankar et al. (U.S. Publication No. 2017/0338996 A1) discloses a device that includes “polar coder [that] perform[s] polar coding on bits U1-U4 and output encoded bits X1-X4, where polar coder 205 may create polarization of encoded bits, i.e., with higher and lower reliabilities” and further includes “[i]nterleaver [that] relies on an asymmetry in the polar coding to decide how to connect encoded bits associated with different reliabilities (e.g., ε− and ε−) to X1-X4, where the output of interleaver (e.g., Z1-Z4) may be different than the input of encoded bits.” (See ¶¶ [0038] and [0039]). Sankar further describes a modulation mapper that maps “the interleaved encoded bits to a modulation symbol. The mapping scheme implemented by modulation mapper [] may be such that a maximum polarization of the reliability of each component channel is preserved during modulation,” where the modulation mapper “may select or use a mapping scheme based on the modulation scheme being used.” (See ¶ [0040]).
Furthermore, Iscan et al. (WO2019197037A1) describes “an encoder for encoding a message into channel input symbols,” where “[t]he encoder is configured to divide the message for obtaining message parts” and “encode the message parts into encoded parts such that at least one encoded part has a non-uniform distribution. The encoder is configured to map the encoded parts into the channel input symbols. A channel input symbol is based on a plurality of encoded parts.” (See p. 3, lines 14-18). Iscan further describes at least one of encoded parts “has a non-uniform probability distribution” and “[t]he encoder is configured to map the encoded parts into the channel input symbols,” where “[t]he channel input symbols . . . are to be transmitted over a transmission channel.” (See p. 15, lines 13-16). Iscan also describes that “[t]he encoder 200 is based on a multi-level coding (MLC) with m bit-levels, wherein m >1. In Fig. 2, the 1st bit-level may refer to the constituent encoder 204a that generates the encoded part 205a of 1st bit-level. Similarly, the 2nd bit-level may refer to the constituent encoder 204b that generates the encoded part 205b of 2nd bit-level, etc., and the mth bit-level may refer to the constituent encoder 204c that generates the encoded part 205c of mth bit-level. A bit-level with a constituent encoder configured to generate a non-uniform encoded part is referred to as a shaped bit-level” (See p. 16, lines 29-31, and p. 17, lines 1-4).
However, none of the aforementioned references discloses limitations “mapping the second bit sequence to obtain the third bit sequence by performing probability shaping and polar transformation are respectively performed on the second bit sequence;” (as construed under 112(b) rejection as explained above) and “performing polar transformation on the first bit sequence and a fourth bit sequence to obtain a fifth bit sequence, wherein the fourth bit sequence is obtained by performing polar transformation on the third bit sequence; modulating the third bit sequence and the fifth bit sequence to obtain a modulation symbol sequence; and sending the modulation symbol sequence” in claim 1, and corresponding limitations in claim 17.
Conclusion
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/SRIHARSHA REDDY VANGAPATY/Examiner, Art Unit 2475
/HASHIM S BHATTI/Primary Examiner, Art Unit 2475
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