Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed action
1. Status of Claims:
Claims 1-20 are pending in this Office Action.
Response to Arguments
2. Applicant’s arguments with respect to amendment to independent claims 1, 14, and 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
3. Claims 1-5, 7, 11, 13-15, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over US2019/0163493 issued to Dubeyko et al. (Dubeyko) in view US 2016/0261493 issued to Li.
As per claim 1, Dubeyko teaches a system for achieving scalable distributed processing, the system comprising: a plurality of processing units electrically coupled to each other (Dubeyko: Fig. 9 - plurality of Data Processing Units (DPU) connected together), each of the processing units including: a processor, and random-access memory (Dubeyko: Claim 1 - plurality of data processing units communicatively coupled to the non-volatile memory in the absence of a central processing unit of the computing system, including a first data processing unit assigned to process data of a memory), wherein at least one of the processing units is configured to: receive a data request (Dubeyko: ¶ 0016 - first data processing unit receiving instructions (request) to execute a parent process from a second data processing unit); and in response to determining that at least a portion of the data request should be processed by the one or more remaining processing units, transfer the portion of the data request to the one or more remaining processing units (Dubeyko: ¶ 0016 - teaches after first data processing unit receives to process parent data from second processing unit, parsing a jobs queue at the first data processing unit for unexecuted processes in response to detection of an occurrence of a processing issue at the first data processing unit occurs and the first data processing unit transmitting instructions to execute a child process (portion of data) associated with the parent process to a third data processing unit (one or more remaining processing units); Fig. 21, ¶ 0159 - also teaches the first DPU may parse a jobs queue at the first DPU for unexecuted processes in response to detection of an occurrence of a processing issue at the first data processing unit, and/or parse a tasks queue at the first data processing unit for unexecuted processes in response to detection of an occurrence of a processing issue at the first data processing unit; and the first DPU re-assigning the child process for execution).
Dubeyko however does not explicitly teach evaluate the data request to determine whether at least a portion of the data request should be processed by one or more remaining processing units;
Li however explicitly teaches evaluate the data request to determine whether at least a portion of the data request should be processed by one or more remaining processing units (Li: Fig. 1, ¶ 0021 - responsive to the request, each of a plurality of egress edge nodes 113-116 is equipped to collect real-time performance data with regards to one or more routes linking the edge node to the destination node 122. Each egress edge node is also equipped to evaluate the route performance (e.g. by computing a set of metrics) based on collected data. The performance data and the evaluation results are communicated to the central controller 111 in the first autonomous system 110 and used to make a routing decision which identifies an optimal egress edge node and an associated route for routing subsequent data traffic between the selected egress node and the destination node 122);
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Dubeyko in view of Li to teach evaluate the data request to determine whether at least a portion of the data request should be processed by one or more remaining processing units. One would be motivated to do so as responsive to the request, each of a plurality of egress edge nodes is equipped to collect real-time performance data with regards to one or more routes linking the edge node to the destination node. Each egress edge node is also equipped to evaluate the route performance (e.g. by computing a set of metrics) based on collected data. The performance data and the evaluation results are communicated to the central controller in the first autonomous system and used to make a routing decision which identifies an optimal egress edge node and an associated route for routing subsequent data traffic between the selected egress node and the destination node (Li: Fig. 1, ¶ 0021).
As per claim 2, the modified teaching of Dubeyko teaches the system of claim 1, wherein each of the one or more remaining processing units is further configured to: receive the portion of the data request from the at least one of the processing units; satisfy the received portion of the data request; and transfer results of satisfying the received portion of the data request to the at least one of the processing units (Dubeyko: Fig. 26, ¶ 0169 - a first DPU determining that one or more root process generation criteria have been satisfied and the first DPU may assign a new root process to the hosting data processing unit).
As per claim 3, the modified teaching of Dubeyko teaches the system of claim 1, wherein each of the one or more remaining processing units is further configured to: receive the portion of the data request from the at least one of the processing units; satisfy the received portion of the data request; and transfer results of satisfying the received portion of the data request to a specific one of the processing units other than the at least one of the processing units (Dubeyko: Fig. 25, ¶ 0168 - a first DPU may check to make sure that at a system level there is at least a minimum number of root processes in simultaneous operation. In the event that a data processing unit executing a root process experiences a processing issue (e.g., a crash, goes offline, runs out of processing resources and/or becomes unresponsive), a new root process is assigned to a data processing unit distinct from the other data processing units executing a root process, and distinct from the failed data processing unit that experienced the processing issue).
As per claim 4, the modified teaching of Dubeyko teaches the system of claim 3, wherein the specific one of the processing units is identified in the given data request (Dubeyko: ¶ 0115 - root process is selected to run on a data processing unit on the basis of resource availability (e.g., on a minimally loaded device/DPU)).
As per claim 5, the modified teaching of Dubeyko teaches the system of claim 1, wherein the host processor, and random-access memory of each of the processing units are positioned on a same die (Dubeyko: Fig. 20 - respective components for DPU 38J (Task Queue 810J) and DPU 38A (Jobs Queue 812A) are on same die).
As per claim 7, the modified teaching of Dubeyko teaches the system of claim 1, wherein the random-access memory includes one or more types of non-volatile random access memory (NVRAM) selected from the group consisting of: magnetoresistive random-access memory (MRAM), resistive random-access memory (RRAM), and phase change memory (Dubeyko: ¶ 0084 - NVMAs (Non-Volatile Memory) include, but are not limited to phase-change memory (PCM) devices, resistive random-access memory (ReRAM) devices, magnetoresistive random-access memory (MRAM) devices).
As per claim 11, the modified teaching of Dubeyko teaches the system of claim 1, wherein the processor includes a host processor and a co-processor (Dubeyko: ¶ 0115 - if a set of DPUs comprises ten DPUs but there are twelve child processes of the root process, one or more DPUs may host more than one child process of the root process).
As per claim 13, the modified teaching of Dubeyko teaches the system of claim 1, wherein one or more of the processing units are physically configured differently than a remainder of the processing units, each of the one or more processing units being physically configured to perform specialized portions of data requests (Dubeyko: ¶ 0077 - the PiNVSM (processor-in-non-volatile-storage-memory) device may include both one or more processing units (PU), and one or more field programmable gate arrays (FPGAs). Processing units in some embodiments may be pre-fabricated in hardware to perform specific computations or data manipulations).
As per claim 14, the claim resembles claim 1 and is rejected under the same rationale.
As per claim 15, the claim resembles claim 2 and is rejected under the same rationale.
As per claim 18, the claim resembles claim 13 and is rejected under the same rationale.
As per claim 19, the claim resembles claim 1 and is rejected under the same rationale while Dubeyko also teaches a non-transitory computer readable medium having stored thereon, software instructions that, when executed by a processor of a given one of a plurality of processing units (Dubeyko: ¶ 0174, ¶ 0175 - a computer-readable storage medium may include a non-transitory medium and fully automated via, software code modules executed by one or more general purpose or special purpose computers or processors).
As per claim 20, the claim resembles claim 2, 5, and 7 and is rejected under the same rationale.
4. Claims 6 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over US2019/0163493 issued to Dubeyko et al. (Dubeyko) in view US 2016/0261493 issued to Li and further in view US 2016/0371211 issued to Isachar et al. (Isachar).
As per claim 6, the modified teaching of Dubeyko teaches the system of claim 5 however does not explicitly teach wherein at least two of the processing units are electrically coupled to each other by a parallel bus.
Isachar however explicitly teaches wherein at least two of the processing units are electrically coupled to each other by a parallel bus (Isachar: ¶ 0107 - the apparatus and techniques may be used to facilitate communication between any two devices connected to one another by a parallel bus, such as a pair of central processing units (CPUs), or a CPU and a memory device).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the modified teaching of Dubeyko in view of Isachar to teach wherein at least two of the processing units are electrically coupled to each other by a parallel bus. One would be motivated to do so as the apparatus and techniques may be used to facilitate communication between any two devices connected to one another by a parallel bus, such as a pair of central processing units (CPUs), or a CPU and a memory device (Isachar: ¶ 0107).
As per claim 16, the claim resembles claim 6 and is rejected under the same rationale.
5. Claims 8-10 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over US2019/0163493 issued to Dubeyko et al. (Dubeyko) in view US 2016/0261493 issued to Li and further in view US 2023/0367507 issued to Rathore et al. (Rathore).
As per claim 8, the modified teaching of Dubeyko teaches the system of claim 7 however does not explicitly teach wherein cells in the NVRAM are configured as (i) analog multi-bit storage elements.
Rathore however explicitly teaches wherein cells in the NVRAM are configured as (i) analog multi-bit storage elements (Rathore: ¶ 0006 - the flash memory includes non-volatile memory cells organized into blocks, where the blocks are a multi-bit mode for storing data in the non-volatile memory cells).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the modified teaching of Dubeyko in view of Rathore to teach wherein cells in the NVRAM are configured as (i) analog multi-bit storage elements. One would be motivated to do so as the flash memory includes non-volatile memory cells organized into blocks, where the blocks are a multi-bit mode for storing data in the non-volatile memory cells (Rathore: ¶ 0006).
As per claim 9, the modified teaching of Dubeyko teaches the system of claim 7 however does not explicitly teach wherein cells in the NVRAM are configured as analog adders and/or multipliers.
Rathore however explicitly teaches wherein cells in the NVRAM are configured as analog adders and/or multipliers (Rathore: ¶ 0049 - a phenomenon associated with flash where the actual amount of information physically written to the storage device is a multiple amount of the logical amount of data intended to be written).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the modified teaching of Dubeyko in view of Rathore to teach wherein cells in the NVRAM are configured as analog adders and/or multipliers. One would be motivated to do so as a phenomenon associated with flash where the actual amount of information physically written to the storage device is a multiple amount of the logical amount of data intended to be written (Rathore: ¶ 0049).
As per claim 10, the modified teaching of Dubeyko teaches the system in claim 7 however does not explicitly teach wherein cells in the NVRAM are configured as: analog multi-bit storage elements, and computing elements.
Rathore however explicitly teaches wherein cells in the NVRAM are configured as: analog multi-bit storage elements, and computing elements (Rathore: ¶ 0006 - the flash memory includes non-volatile memory cells organized into blocks, where the blocks are a multi-bit mode for storing data; while ¶ 0034 - teaches flash memory device (non-volatile memory) includes a number of storage elements).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the modified teaching of Dubeyko in view of Rathore to teach wherein cells in the NVRAM are configured as: analog multi-bit storage elements, and computing elements. One would be motivated to do so as the flash memory includes non-volatile memory cells organized into blocks, where the blocks are a multi-bit mode for storing data; and the flash memory device (non-volatile memory) includes a number of storage elements (Rathore: ¶ 0006, ¶ 0034).
As per claim 17, the claim resembles claim 7 and is rejected under the same rationale.
6. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over US2019/0163493 issued to Dubeyko et al. (Dubeyko) in view US 2016/0261493 issued to Li and further in view US 11,435,813 issued to Sadowski.
As per claim 12, the modified teaching of Dubeyko teaches the system of claim 11 however does not explicitly teach wherein the plurality of coprocessors form at least a portion of a distributed neural network.
Sadowski however explicitly teaches wherein the plurality of coprocessors form at least a portion of a distributed neural network (Sadowski: Col. 2, ll. (13-15) - the computing system implements a neural network on the plurality of processing units).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the modified teaching of Dubeyko in view of Sadowski to teach wherein the plurality of coprocessors form at least a portion of a distributed neural network. One would be motivated to do so as the computing system implements a neural network on the plurality of processing units (Rathore: Sadowski: Col. 2, ll. (13-15)).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136 (a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SM AZIZUR RAHMAN whose telephone number is (571) 270-7360. The examiner can normally be reached on M-F Telework;
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ali Shayanfar can be reached on 571-270-1050. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SM A RAHMAN/Primary Examiner, Art Unit 2434
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