Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of FILLIN "Enter claim indentification information" \* MERGEFORMAT Species VI ( Fig. 8E) in the reply filed on FILLIN "Enter mail date of the reply." \* MERGEFORMAT February 13, 2026 , is acknowledged. Drawings The drawings are objected to because : Figs. 5A and 5C are both cross sections of Fig. 4 that intersect each other (lines A-A’ and C-C’, respectively) . Fig. 5A shows a gate capping pattern GP disposed on top of the gate cutting pattern CT. However, Fig. 5C fails to show the gate capping pattern at all, even in the region where the depicted cross section intersects that of Fig. 5A. The text of the specification implies that the configuration of Fig. 5A is intended , and thus it will be assumed for examination purposes that this is the intended configuration . T he illustrations of the axes in Figs. 8B, 8D, and 8F appear to be cut off . Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Fig. 4 of Yeom , reproduced with annotations added by the examiner. Fig. 5A o f Yeom , reproduced with annotations added by the examiner. Fig. 5B of Yeom , reproduced with annotations added by the examiner. Fig. 5C of Yeom , reproduced with annotations added by the examiner. Fig. 5D of Yeom , reproduced with annotations added by the examiner. Fig. 5E of Yeom , reproduced with annotations added by the examiner. Fig. 6C of Yeom , reproduced with annotations added by the examiner. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application , as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims FILLIN "Insert the claim numbers which are under rejection." \d "[ 1 ]" 11 and 13 are rejected under 35 U.S.C. 102(a)(2) as being FILLIN "Insert either --clearly anticipated-- or --anticipated-- with an explanation at the end of the paragraph." \d "[ 2 ]" anticipated by FILLIN "Insert the prior art relied upon." \d "[ 3 ]" Yeom et. al. , Pub. No. US 2023/0019278, hereafter referred to as Yeom . The applied reference has a common FILLIN "Insert --assignee-- or --applicant-- or --joint inventor--." \d "[ 4 ]" applicant with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. Regarding claim 11 , Yeom teaches all of the limitations of the claim in Figs. 4, 5C-E, and 6C, reproduced above with annotations added by the examiner: “ A semiconductor device ” (Fig. 4) “ comprising: a substrate ” ([0035]; Fig. 4, substrate 100) ; “ a device isolation layer on the substrate ” ([0039]; Figs. 5D , 5E , and 6C , device isolation layer ST) ; “ a gate cutting pattern on the device isolation layer ” ([0061]; Fig. 5E, gate cutting pattern CT) ; “ a gate spacer on a sidewall of the gate cutting pattern ” ([0064] : “ The gate spacer GS may be extended lengthwise along the gate electrode GE and in the first direction D 1 . ” ; Fig. 4, first direction D1, gate electrode GE , and gate cutting pattern CT, Figs. 5C and 6C, gate spacer portions GSP1-3, hereafter collectively referred to as the gate spacer ) ; and “ an interlayer insulating layer ” ([0064], [0069]; Figs. 5D and 5E, first interlayer insulating layer 110, second interlayer insulating layer 120) “ on the device isolation layer ” ([0039]; Figs. 5D, 5E, and 6C, device isolation layer ST) “ and the gate spacer ” ([0064]; Figs. 5C and 6C, gate spacer portions GSP1-3, hereafter collectively referred to as the gate spacer; also see Fig. 4) , “ and an insulating pattern ” ( [0068] Fig. 6C, gate spacer portion GSP4 , recess RS3 ) “ between the device isolation layer ” (Fig. 6C, device isolation layer ST) “ and the interlayer insulating layer ” (Fig. 6C, interlayer insulating layer 110) “ and between the gate spacer ” (Fig. 6C, gate spacer portions GSP1-3, hereafter collectively referred to as the gate spacer GSP1-3 ) “ and the interlayer insulating layer ” (Fig. 6C, interlayer insulating layer 110) , “ wherein the insulating pattern includes: a first portion disposed between the interlayer insulating layer and the gate spacer ” (Fig. 6C, gate spacer portion GSP4, gate spacer GSP1-3, interlayer insulating layer 110) ; “ and a second portion disposed between the interlayer insulating layer and the device isolation layer ” (Fig. 6C, gate spacer portion GSP4, gate spacer GSP1-3, device isolation layer ST). Regarding claim 13 , Yeom further teaches “ wherein the second portion has a round profile in a cross-sectional view ” (Fig. 5C, gate spacer portion GSP4, recess RS3). Regarding claim 15 , Yeom further anticipates “ wherein the insulating pattern includes at least one of silicon nitride ( SiN ), silicon carbon nitride ( SiCN ), silicon oxycarbide ( SiOC ), or silicon oxycarbonitride ” by disclosing silicon nitride, silicon carbon nitride, and silicon oxycarbonitride as possible materials for the gate spacer portion GSP4 ([0064]: “ The gate spacer GS may be formed of or may include at least one of SiCN , SiCON , or SiN . ”). Fig. 6 of Min, reproduced with annotations added by the examiner. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness . Claims FILLIN "Pluralize claim, if necessary, and then insert the claim number(s) which is/are under rejection." \d "[ 1 ]" 1-4, 7-8, 16-17, and 20 are rejected under 35 U.S.C. 103 as being obvious over FILLIN "Insert the prior art reference." \d "[ 2 ]" Yeom in view of Min et. al. , Pub. No. US 2022/0208965, hereafter referred to as Min . The applied reference s ha ve a common FILLIN "Insert—assignee--, --applicant--, or—joint inventor--." \d "[ 3 ]" applicant with the instant application. Based upon the earlier effectively filed date s of the reference s , they constitute prior art under 35 U.S.C. 102(a)(2). Regarding claim 1 , Yeom teaches “ A semiconductor device ” ( Yeom Fig. 4) “ comprising: a substrate ” ( Yeom [0035]; Fig. 4, substrate 100) “ including a first active region ” ( Yeom [0036]; Fig. 4 , first P MOSFET region PR1 ) “ and a second active region ” ( Yeom [0036]; Fig. 4, second P MOSFET region P R 2 ) ; “ a first active pattern on the first active region ” ( Yeom [003 6 ]; Fig. 5A, a first copy of the first active region AP1, Figs. 5D and 5E , firs t PMOSFET region PR1 ) ; “ a second active pattern on the second active region ” ( Yeom [003 6 ]; Fig. 5A, a second copy of the first active region AP1, Fig s . 5D and 5E , second PMOSFET region PR 2) ; “ a device isolation layer filling a trench between the first active pattern and the second active pattern ” ( Yeom [0039]; Fig s . 5D and 5E , device isolation layer ST) , “ the device isolation layer having a concave top surface ” ( Yeom Fig s . 5D and 5E , device isolation layer ST) ; “ a first gate electrode in the first active region ” ( Yeom Fig. 5E, portion of gate electrode GE1 to the right of the gate cutting pattern CT ) ; “ a second gate electrode in the second active region ” ( Yeom Fig. 5E ; portion of gate electrode GE1 to the left of the gate cutting pattern CT ), and “ a gate cutting pattern between the first gate electrode and the second gate electrode and separating the first gate electrode and the second gate electrode ” ( Yeom [0061]; Fig s . 4 and 5E, gate cutting pattern CT) , but does not teach “ an insulating pattern between the gate cutting pattern and the concave top surface of the device isolation layer. ” Min, on the other hand, does teach an insulating pattern (Min Fig. 6, reproduced above with annotations added by the examiner, upper buried insulating layer 316S) disposed between a gate electrode (Min Fig. 6, gate electrode 160) and a device isolation layer with a concave top surface (Min Fig. 6, lower buried insulating layer 112C) . Furthermore, Min teaches that the purpose of the upper insulating layer is to reduce parasitic capacitance between two transistors, thus improving performance (Min [0004], [0077]). The insulating pattern of Min can be incorporated into the apparatus of Yeom through the splitting of the device isolation layer of Yeom into two portions, a lower portion and an upper portion , such that the lower portion has a concave top surface . The upper portion would be directly underneath the gate cutting pattern of Yeom , and thus the combined device teaches “ an insulating pattern between the gate cutting pattern and the concave top surface of the device isolation layer . ” It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to split the device isolation layer of Yeom into an upper portion and a lower portion as taught by Min because it would improve the performance of the device of Yeom by reducing parasitic capacitance, as taught by Min, and is a simple combination of elements of the two disclosures. Regarding claim 2 , the combination of Yeom and Min described in the discussion of claim 1 further teaches “ wherein the insulating pattern ” (Min Fig. 6, upper buried insulating layer 316S) “ is disposed between the first gate electrode and the device isolation layer ” ( Yeom Fig. 5E, device isolation layer ST, portion of the gate electrode GE1 to the right of the gate cutting pattern CT ; Min Fig. 6, upper buried insulating layer 316S) “ and between the second gate electrode and the device isolation layer ” ( Yeom Fig. 5E, device isolation layer ST , portion of the gate electrode GE1 to the left of the gate cutting portion CT ; Min Fig. 6, upper buried insulating layer 316S). Regarding claim 3 , the combination of Yeom and Min described in the discussion of claim 1 further teaches “ wherein a top surface of the insulating pattern ” (Min Fig. 6, upper buried insulating layer 316S) “ includes a portion in contact with the gate cutting pattern ” ( Yeom Fig. 5E, device isolation layer ST, gate cutting pattern CT). Regarding claim 4 , the combination of Yeom and Min described in the discussion of claim 1 further teaches “ further comprising an insulating layer ” (Min [0055]; Fig. 6, gate dielectric layer 152) “ disposed on a top surface of the insulating pattern ” (Min Fig. 6, upper buried insulating layer 316S) . Regarding claim 7 , the combination of Yeom and Min described in the discussion of claim 1 further teaches “ wherein a top surface of the insulating pattern is a curved surface ” (Min [0093]; Fig. 6, upper buried insulating layer 316S). Regarding claim 8 , the combination of Yeom and Min described in the discussion of claim 1 further teaches “ wherein a bottom surface of the insulating pattern ” (Min Fig. 6, upper buried insulating layer 316S) “ is disposed on the concave top surface of the device isolation layer ” (Min Fig. 6, lower buried insulating layer 112C) . Regarding claim 1 6 , Yeom teaches “ A semiconductor device ” ( Yeom Fig. 4), “ comprising: a substrate including a logic cell ” ( Yeom [0035]; Fig. 4, substrate 100) , “ the logic cell including a PMOSFET region ” ( Yeom [0036]; Fig. 4, first PMOSFET region PR1) “ and an NMOSFET region ” ( Yeom [0036]; Fig. 4, first NMOSFET region NR1) “ which are spaced apart from each other in a first direction ” ( Yeom Fig. 4, first direction D1) , “ the logic cell having a first boundary ” ( Yeom Fig. 4, first border BD1 ) , “ a second boundary ” ( Yeom Fig. 4, second border BD2 ) , “ a third boundary ” ( Yeom Fig. 4, third border BD3 ) , “ and a fourth boundary ” ( Yeom Fig. 4, fourth border BD4 ) , “ the first boundary and the second boundary disposed opposite to each other in a second direction intersecting the first direction ” ( Yeom Fig. 4, second direction D2) , “ and the third boundary and the fourth boundary disposed opposite to each other in the first direction ” ( Yeom Fig. 4, first direction D1) ; “ a device isolation layer provided on the substrate ” ( Yeom Figs. 5D and 5E, device isolation layer ST) “ defining a first active pattern on the PMOSFET region ” ( Yeom [0038]; Fig s . 5 A, 5D, and 5E , first active pattern AP1) “ and defining a second active pattern on the NMOSFET region ” ( Yeom [0038]; Fig. 5B, 5D , and 5E , second active pattern AP2) , “ the first active pattern and the second active pattern extending in the second direction ” ( Yeom Fig. 4, second direction D2) , “ and the first active pattern and the second active pattern having upper portions protruding above the device isolation layer ” ( Yeom Fig. 5D, first active pattern AP1 and second active pattern AP2) ; “ a gate electrode extending in the first direction and intersecting the first active pattern and intersecting the second active pattern ” ( Yeom Figs. 4 and 5E, gate electrode GE1 , first and second active patterns AP1 and AP2 ) ; “ a first source/drain pattern disposed in the upper portions of the first active pattern at a first side of the gate electrode ” ( Yeom Fig s . 5A and 5D, first source/drain patterns SD1) ; “ a second source/drain pattern disposed in the upper portion of the second active pattern at a second side of the gate electrode ” ( Yeom Fig s . 5B and 5D, second source/drain patterns SD2) ; “ a pair of gate spacers on sidewalls of the gate electrode, the pair of gate spacers extending in the first direction ” ( Yeom [006 4 ]; Fig s . 4 and 5C, gate spacer GS2) ; “ a gate capping pattern on the gate electrode ” ( Yeom [0069]; Fig. 5E, gate capping pattern GP) ; “ an isolation structure provided on at least one of the first boundary or the second boundary ” ( Yeom [0033]; Fig. 4, division structure DB) ; “ a gate cutting pattern provided on at least one of the third boundary or the fourth boundary ” ( Yeom [0061]; Fig. 4, gate cutting pattern CT) , “ the gate cutting pattern having a lower portion provided between the pair of gate spacers ” ( Yeom [0064]; Fig. 4, first direction D1, gate electrode GE, and gate cutting pattern CT, Figs. 5C and 6C, gate spacer portions GSP1-3, hereafter collectively referred to as the gate spacer ) , “ and the gate cutting pattern aligned with the gate electrode in the first direction ” ( Yeom Fig. 4 , first direction D1, gate electrode GE, gate cutting pattern CT ) ; “ an interlayer insulating layer on the gate capping pattern and the gate cutting pattern ” ( Yeom [0064], [0069]; Fig. 5D, first interlayer insulating layer 110, second interlayer insulating layer 120 , gate capping pattern GP, gate cutting pattern CT ) ; “ an active contact penetrating the interlayer insulating layer ” ( Yeom [0091]; Fig. 5D, active contacts AC, first and second interlayer insulating layers 110 and 120) “ and electrically connected to at least one of the first source/drain pattern or the second source/drain pattern ” ( Yeom [0091]; Fig s . 5A, 5B, and 5D, active contacts AC, first and second source/drains SD1 and SD2) ; “ a gate contact penetrating the interlayer insulating layer and the gate capping pattern ” ( Yeom [0097]; Fig. 5E, gate contact GC, second interlayer insulating layer 120, and gate capping pattern GC) “ and electrically connected to the gate electrode ” ( Yeom [0097]; Fig. 5E, gate electrode GE1) ; “ a first metal layer on the interlayer insulating layer ” ( Yeom [0103]; Fig. 5E, first metal layer M1) , “ the first metal layer comprising a power interconnection line vertically overlapping with the gate cutting pattern ” ( Yeom Fig. 4, first, second, and third power lines M1_R1, M1_R2, and M1_R3) , “ and a first interconnection line electrically connected to the active contact ” ( Yeom [0104]: “ The active contacts AC and the first interconnection lines M1_I of the first metal layer M1 may be electrically connected to each other through the first via VI1. ”; Fig. 5D, first vias VI1 , active contact AC ) “ and the gate contact, respectively ” ( Yeom [0104]: “ The gate contact GC and the first interconnection lines M1_I of the first metal layer M1 may be electrically connected to each other through the first via VI1. ”; Fig. 5E, first vias VI1, gate contact GC) ; “ a second metal layer on the first metal layer ” ( Yeom [0106]; Fig. 5E, second metal layer M2) , and “ the second metal layer comprising a second interconnection line electrically connected to the first metal layer ” ( Yeom [0107]: “ The interconnection lines of the first and second metal layers M1 and M2 may be electrically connected to each other through the second via VI2. ”; Fig. 5E, second vias VI2) , but does not teach “ an insulating pattern disposed between the gate cutting pattern and the device isolation layer and between the gate electrode and the device isolation layer. ” Min, on the other hand, does teach an insulating pattern (Min Fig. 6, upper buried insulating layer 316S) disposed between the gate electrode (Min Fig. 6, gate line 160) and the device isolation layer (Min Fig. 6, lower buried insulating layer 112C). Furthermore, Min teaches that the purpose of the upper insulating layer is to reduce parasitic capacitance between two transistors, thus improving performance (Min [0004], [0077]). The insulating pattern of Min can be incorporated into the apparatus of Yeom through the splitting of the device isolation layer of Yeom into two portions, a lower portion and an upper portion. The upper portion would be directly underneath the gate cutting pattern of Yeom , and thus the combined device teaches “ an insulating pattern between the gate cutting pattern and the concave top surface of the device isolation layer . ” It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to split the device isolation layer of Yeom into an upper portion and a lower portion as taught by Min because it would improve the performance of the device of Yeom by reducing parasitic capacitance, as taught by Min, and is a simple combination of elements of the two disclosures. Regarding claim 17 , the combination of Yeom and Min described in the discussion of claim 16 further teaches “ further comprising an insulating layer ” (Min [0055]; Fig. 6, gate dielectric layer 152) “ disposed on a top surface of the insulating pattern ” (Min [0055]; Fig. 6, upper buried insulating layer 316S) . Regarding claim 20 , the combination of Yeom and Min described in the discussion of claim 16 further teaches “ wherein a top surface and a bottom surface of the insulating pattern are concave curved surfaces ” (Min [0093]; Fig. 6, upper buried insulating layer 316S) , “ and the bottom surface of the insulating pattern ” (Min Fig. 6, upper buried insulating layer 316S) “ is disposed on a concave top surface of the device isolation layer ” (Min Fig. 6, lower buried insulating layer 112C) . This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference s was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02. Fig. 1I of Lin, reproduced above with annotations added by the examiner. Fig. 1S of Lin, reproduced above with annotations added by the examiner. Claim FILLIN "Pluralize claim, if necessary, and then insert the claim number(s) which is/are under rejection." \d "[ 1 ]" 5 is rejected under 35 U.S.C. 103 as being unpatentable over FILLIN "Insert the prior art reference(s) relied upon for the obviousness rejection." \d "[ 2 ]" Yeom and Min as applied to claim s FILLIN "Pluralize claim, if necessary, and then insert the claim number(s) which is/are under rejection." \d "[ 3 ]" 1-4, 7-8, 16-17, and 20 above, and further in view of FILLIN "Insert the additional prior art reference(s) relied upon for the obviousness rejection." \d "[ 4 ]" Lin et. al. , Pub. No. US 2024/0063065, hereafter referred to as Lin . Regarding claim 5 , the combination of Yeom and Min described in the discussion of claim 1 teaches “ The semiconductor device of claim 1 ” and “ wherein the insulating pattern has an uppermost portion and a lowermost portion ” (Min Fig. 6, upper buried insulating layer 316S) , but does not teach “ wherein a distance between the uppermost portion and the lowermost portion ranges from about 5nm to 50nm . ” Lin, on the other hand, anticipate s “ wherein a distance between the uppermost portion and the lowermost portion ranges from about 5nm to 50nm ” (Lin [0062]: “In some embodiments, the thickness T5… may be less than 50 nm.”; Figs. 1I and 1S, reproduced above with annotations added by the examiner, upper isolation layer 130B , thickness T5 ). Lin also states that a goal of their disclosure is to reduce the size of semiconductor devices, which would improve performance (Lin [0001]). The upper isolation layer 130B and the lower isolation layer 126B of Lin (Lin Fig. 13C) may be incorporated into the combination of Yeom and Min described in the discussion of claim 1 as replacements for the upper buried insulating layer (Min Fig. 6, 316S ) and lower buried insulating layer (Min Fig. 6 , 112C ) . It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to replace the upper and lower buried insulating layers of the combination of Yeom and Min described in the discussion of claim 1 with the upper and lower isolation layers of Lin because it would help to reduce the size of the device and thus improve performance , and current case law holds that the fact that Lin teaches a range of thicknesses that overlaps the claimed range establishes a prima facie case of obviousness (see MPEP 2144.05 I: “ In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990) ”). Fig. 1A of Yemenicioglu , reproduced above with annotations added by the examiner. Fig. 2 of Yemenicioglu , reproduced with annotations added by the examiner. Claims FILLIN "Pluralize claim, if necessary, and then insert the claim number(s) which is/are under rejection." \d "[ 1 ]" 6, 9, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over FILLIN "Insert the prior art reference(s) relied upon for the obviousness rejection." \d "[ 2 ]" Yeom and Min as applied to claim s FILLIN "Pluralize claim, if necessary, and then insert the claim number(s) which is/are under rejection." \d "[ 3 ]" 1-4, 7-8, 16-17, and 20 above, and further in view of FILLIN "Insert the additional prior art reference(s) relied upon for the obviousness rejection." \d "[ 4 ]" Yemenicioglu et. al. , Pub. No. US 2024/0113106, hereafter referred to as Yemenicioglu . R egarding claim 6 , the combination of Yeom and Min described in the discussion of claim 1 teaches “ The semiconductor device of claim 1 ”, but does not teach “ wherein the insulating pattern includes at least one of silicon nitride ( SiN ), silicon carbon nitride ( SiCN ), silicon oxycarbide ( SiOC ), or silicon oxycarbonitride ”. Yemenicioglu , on the other hand, anticipate s “ wherein the insulating pattern includes at least one of silicon nitride ( SiN ), silicon carbon nitride ( SiCN ), silicon oxycarbide ( SiOC ), or silicon oxycarbonitride ” by disclosing silicon nitride, silicon oxycarbide , and silicon oxycarbonitride as possible materials for the insulating pattern disclosed therein ( Yemenicioglu [0053]: “ Examples of the dielectric material 107 include silicon nitride ( SiN ), silicon oxynitride ( SiON ), silicon carbide ( SiC ), silicon oxycarbide ( SiOC ), silicon oxycarbonitride ( SiOCN ), or silicon oxide ( SiO ), for example. ”; Figs. 1A and 2 , reproduced above with annotations added by the examiner , second dielectric material 107). The material composition of the second dielectric material of Yemenicioglu can be incorporated into the combination of Yeom and Min described in the discussion of claim 1 as the material composition of the upper buried insulating layer (Min Fig. 6, upper buried insulating layer 316S). It would have been obvious to one of ordinary skill in the art to use one of the dielectric materials disclosed by Yemenicioglu as the material of the insulating pattern in the combination of Yeom and Min described in the discussion of claim 1 because said materials can also serve the purpose of insulators and it would be a simple substitution of one material for another. Regarding claim 9 , the combination of Yeom and Min described in the discussion of claim 1 teaches “ The semiconductor device of claim 1 ”, but does not teach “ wherein the insulating pattern includes a first insulating portion and a second insulating portion, and wherein the first insulating portion is spaced apart from the second insulating portion by an insulating layer ”. Yemenicioglu , on the other hand, does teach “ wherein the insulating pattern includes a first insulating portion and a second insulating portion ” ( Yemenicioglu [0055]: “ In other such example cases, the trenches pass-through the etch stop dielectric material 107 …”; Fig. 2, second dielectric material with first and second portions 107) , “ and wherein the first insulating portion is spaced apart from the second insulating portion by an insulating layer ” ( Yemenicioglu [0049], [0055]; Fig. 2, second dielectric material with first and second portions 107 , dielectric material structure 124). The second dielectric material with first and second portions of Yemenicioglu can be implemented as a splitting of the upper buried insulating layer (Min Fig. 6, upper buried insulating layer 316S) of the combination of Yeom and Min described in the discussion of claim 1 into two portions via an extension of the gate cut pattern as shown in Yemenicioglu (Fig. 2, dielectric material structure 124) , with said extension serving as the insulating layer separating the two portions . It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have extended the gate cut pattern in the combination of Yeom and Min described in the discussion of claim 1 such that the insulating pattern is split into two portions, as disclosed by Yemenicioglu , because doing so would have provided better isolation of the two transistors separated by the gate cut and it would have been a simple combination of elements of the two disclosures. Regarding claim 18 , the combination of Yeom and Min described in the discussion of claim 16 teaches “ The semiconductor device of claim 1 6 ”, but does not teach “ wherein the insulating pattern includes at least one of silicon nitride ( SiN ), silicon carbon nitride ( SiCN ), silicon oxycarbide ( SiOC ), or silicon oxycarbonitride ”. Yemenicioglu , on the other hand, anticipate s “ wherein the insulating pattern includes at least one of silicon nitride ( SiN ), silicon carbon nitride ( SiCN ), silicon oxycarbide ( SiOC ), or silicon oxycarbonitride ” by disclosing silicon nitride, silicon oxycarbide , and silicon oxycarbonitride as possible materials for the insulating pattern disclosed therein ( Yemenicioglu [0053]; Figs. 1A and 2, second dielectric material 107). The material composition of the second dielectric material of Yemenicioglu can be incorporated into the combination of Yeom and Min described in the discussion of claim 16 as the material composition of the upper buried insulating layer (Min Fig. 6, 316S). It would have been obvious to one of ordinary skill in the art to use one of the dielectric materials disclosed by Yemenicioglu as the material of the insulating pattern in the combination of Yeom and Min described in the discussion of claim 16 because said materials can also serve the purpose of insulators and it would be a simple substitution of one material for another. Fig. 13C of Chang, reproduced with annotations added by the examiner. Claims FILLIN "Pluralize claim, if necessary, and then insert the claim number(s) which is/are under rejection." \d "[ 1 ]" 10 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over FILLIN "Insert the prior art reference(s) relied upon for the obviousness rejection." \d "[ 2 ]" Yeom and Min as applied to claim s FILLIN "Pluralize claim, if necessary, and then insert the claim number(s) which is/are under rejection." \d "[ 3 ]" 1-4, 7-8, 16-17, and 20 above, and further in view of FILLIN "Insert the additional prior art reference(s) relied upon for the obviousness rejection." \d "[ 4 ]" Chang et. al. , Pub. No. US 2024/0055476, hereafter referred to as Chang . Regarding claim 10 , the combination of Yeom and Min described in the discussion of claim 1 teaches “ The semiconductor device of claim 1 , wherein the first active pattern comprises a pair of first source/drain patterns ” ( Yeom Fig. 5A, reproduced above with annotations added by the examiner, a first copy of the first source/drain patterns SD1) “ and a first channel pattern between the pair of first source/drain patterns ” ( Yeom Fig. 5A, a first copy of the first channel pattern CH1) , “ the second active pattern comprises a pair of second source/drain patterns ” ( Yeom Fig. 5 A , a second copy of the first source/drain patterns SD 1 ) “ and a second channel pattern between the pair of second source/drain patterns ” ( Yeom Fig. 5 A , a second copy of the first channel pattern CH 1 ) , but does not teach “ the insulating pattern extends to cover the first source/drain patterns and the second source/drain patterns. ” Chang, on the other hand, does teach a device isolation layer (Chang [0029]; Fig. 13C, STI feature 317) that extends to cover the first source/drain patterns and the second source/drain patterns (Chang [0036]; Fig. 13 C, source/drain features 321) . The shape of the STI features of Chang may be incorporated as a corresponding shape of the device isolation layers of the combination of Yeom and Min described in the discussion of claim 1. The device isolation layer is then split into two portions as described in the discussion of claim 1; the device so modified then teaches “ the insulating pattern extends to cover the first source/drain patterns and the second source/drain patterns. ” It would have been obvious to one of ordinary skill in the art before the effective filing date to use the shape of the STI features of Chang in the combination of Yeom and Min described in the discussion of claim 1 because such a shape would provide better separation of the transistor structures and it would be a simple combination of elements of the two disclosures. Regarding claim 19 , the combination of Yeom and Min described in the discussion of claim 1 teaches “ The semiconductor device of claim 1 6 ” , but does not teach “ wherein the insulating pattern extends to cover the first source/drain patterns and the second source/drain patterns. ” Chang, on the other hand, does teach a device isolation layer (Chang [0029]; Fig. 13C, STI feature 317) that extends to cover the first source/drain patterns and the second source/drain patterns (Chang [0036]; Fig. 13C, source/drain features 321). The shape of the STI features of Chang may be incorporated as a corresponding shape of the device isolation layers of the combination of Yeom and Min described in the discussion of claim 1. The device isolation layer is then split into two portions as described in the discussion of claim 1; the device so modified then teaches “ the insulating pattern extends to cover the first source/drain patterns and the second source/drain patterns. ” It would have been obvious to one of ordinary skill in the art before the effective filing date to use the shape of the STI features of Chang in the combination of Yeom and Min described in the discussion of claim 16 because such a shape would provide better separation of the transistor structures and it would be a simple combination of elements of the two disclosures. Allowable Subject Matter Claim s 12 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to disclose or suggest the claim limitations of: Claim 12 , which teaches the limitation, “ wherein the second portion of the first insulating pattern is in contact with the second portion of the second insulating pattern. ” Claim 1 4 , which teaches the limitation, “ wherein the gate cutting pattern is on and in contact with the second portion of the insulating pattern . ” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT ROBERT EMIL THROCKMORTON whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571) 272-7014 . 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To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /R.E.T./ Examiner, Art Unit 2818 /STEVEN H LOKE/ Supervisory Patent Examiner, Art Unit 2818