Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on July 2, 2026, under 37 CFR 1.312 has been entered. All objections raised by the examiner to the applicant’s drawings in the previous office action have been addressed. Therefore, all objections to the drawings are withdrawn.
Response to Arguments
Applicant’s arguments, see pp. 9-10, filed July 2, 2026, with respect to the rejections of claims 1-20 under 35 U.S.C. 102(a)(2) and 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, new grounds of rejection are made in view of:
You et. al., Pub. No. US 2025/0311407, hereafter referred to as You, and Lin et. al., Pub. No. US 2024/0063065, hereafter referred to as Lin, with regards to claims 1-10,
Chang et. al., Pub. No. US 2024/0055476, hereafter referred to as Chang, with regards to claims 11-15, and
Liaw et. al., Pub. No. US 2021/0305389, hereafter referred to as Liaw, and Kim et. al., Pub. No. US 2021/0126014, hereafter referred to as Kim, with regards to claims 16-20.
Regarding rejections under 35 U.S.C. 102(a)(2) and 103, applicant has provided a statement that, as of the effective filing date of the application, the reference, Yeom et. al., Pub. No. US 2023/0019278, hereafter referred to as Yeom, which shares a common applicant with the instant application, was subject to common ownership, and is therefore disqualified as prior art under 35 U.S.C. 102(b)(2)(C). Therefore, the original rejections of claims 1-20, all of which relied on Yeom, are withdrawn and this action is made non-final.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites the limitation, “wherein the second portion of the first insulating pattern is in contact with the second portion of the second insulating pattern.” There is no antecedent basis for the second portions of the first and second insulating patterns.
This rejection may be overcome by reciting first and second portions of the first and second insulating patterns, e.g., “wherein each of the first and second insulating patterns comprises a first portion disposed between a respective gate spacer and the interlayer insulating layer and a second portion disposed between a respective device isolation layer and the interlayer insulating layer”.
PNG
media_image1.png
570
734
media_image1.png
Greyscale
Fig. 1 of Chang, reproduced with annotations added by the examiner.
PNG
media_image2.png
775
700
media_image2.png
Greyscale
Fig. 13A of Chang, reproduced with annotation added by the examiner.
PNG
media_image3.png
549
697
media_image3.png
Greyscale
Fig. 13B of Chang, reproduced with annotations added by the examiner.
PNG
media_image4.png
648
786
media_image4.png
Greyscale
Fig. 13C of Chang, reproduced with annotations added by the examiner.
PNG
media_image5.png
822
944
media_image5.png
Greyscale
Fig. 13D of Chang, reproduced with annotations added by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 11-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chang.
Regarding claim 11, Chang teaches all of the limitations of the claim in Figs. 13A-D, reproduced above with annotations added by the examiner: “A semiconductor device” ([0022]; Fig. 13A, semiconductor device 300) “comprising: a substrate” ([0026]; Fig. 13D, substrate 302); “a device isolation layer on the substrate” ([0041]; Fig. 13D, STI features 317); “a gate cutting pattern on the device isolation layer” ([0041]; Fig. 13D, portion of liner layer 402a marked “(part of gate cutting pattern)” and dielectric layer 402b, hereafter referred to as the gate cutting pattern; also see [0043] and Fig. 13B and note that the dielectric layer 402b splits the gate structure 316 into multiple sections); “a gate spacer on a sidewall of the gate cutting pattern” ([0041]; Fig. 13D, portion of liner layer 402a marked “gate spacer”, hereafter referred to as the gate spacer); “an interlayer insulating layer on the device isolation layer and the gate spacer” ([0041]; Fig. 13D, dielectric layer 802b); “and an insulating pattern between the device isolation layer and the interlayer insulating layer” ([0045]; Fig. 13D, note that the portion of the liner layer 802a marked “first insulating pattern”, hereafter referred to as the first insulating pattern, has portions between the dielectric layer 802b and the STI features 317) “and between the gate spacer and the interlayer insulating layer” ([0045]; Fig. 13D, note that the first insulating pattern has portions between the gate spacer and the dielectric layer 802b), “wherein the insulating pattern includes: a first portion disposed between the interlayer insulating layer and the gate spacer” ([0045]; Fig. 13D, first portion of the first insulating pattern; note that the first portion of the insulating pattern is disposed between the gate spacer and the dielectric layer 802b); “and a second portion disposed between the interlayer insulating layer and the device isolation layer” ([0045]; Fig. 13D, second portion of the first insulating pattern; note that the second portion of the insulating pattern is disposed between the STI features 317 and the dielectric layer 802b).
Regarding claim 12, Chang further teaches “The semiconductor device of claim 11, wherein the insulating pattern includes a first insulating pattern and a second insulating pattern adjacent to each other” (Fig. 13D, note that the first and second insulating patterns are adjacent to each other), “wherein the second portion of the first insulating pattern is in contact with the second portion of the second insulating pattern” (Fig. 13D, note that the second portions of the first and second insulating patterns contact each other).
Regarding claim 13, Chang further teaches “The semiconductor device of claim 11, wherein the second portion has a round profile in a cross-sectional view” (Figs. 1, 13A, and 13D; note that the second portion of the second insulating pattern has a round shape in the cross section shown in Fig. 13A).
Regarding claim 14, Chang further teaches “The semiconductor device of claim 11, wherein the gate cutting pattern is on and in contact with the second portion of the insulating pattern” ([0041]; Fig. 13D, note that the gate cutting pattern contacts the second portion of the first insulating pattern).
Regarding claim 15, Chang further anticipates “The semiconductor device of claim 11, wherein the insulating pattern includes at least one of silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), or silicon oxycarbonitride” by teaching that the insulating pattern may be made of SiN ([0045]: “The liner layer 802a may be a nitride layer, for example including SiN.”; Fig. 13D, liner layer 802a).
PNG
media_image6.png
724
681
media_image6.png
Greyscale
Fig. 30 of You, reproduced with annotations added by the examiner.
PNG
media_image7.png
719
857
media_image7.png
Greyscale
Fig. 1I of Lin, reproduced with annotations added by the examiner.
PNG
media_image8.png
685
1047
media_image8.png
Greyscale
Fig. 1S of Lin, reproduced with annotations added by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over You in view of Lin.
Regarding claim 1, You teaches “A semiconductor device” (You Fig. 30) “comprising: a substrate including a first active region and a second active region” (You [0015]; Fig. 30, substrate 202 and first and second active regions); “a first active pattern on the first active region” (You [0031]; Fig. 30, channel members 2080 within the first active region); “a second active pattern on the second active region” (You [0031]; Fig. 30, channel members 2080 within the second active region); “a device isolation layer filling a trench between the first active pattern and the second active pattern” (You [0020]; Fig. 30, isolation feature 216), “the device isolation layer having a concave top surface” (You [0020] and [0045]; Fig. 30, note that the top surface of the isolation feature 216 has a concave top surface to accommodate the round-bottom isolation structure 294); “a first gate electrode in the first active region” (You [0032]; Fig. 30, left-hand of the gate electrode layers 266); “a second gate electrode in the second active region” (You [0032]; Fig. 30, right-hand of the gate electrode layers 266); “a gate cutting pattern between the first gate electrode and the second gate electrode” (You [0032] and [0045]; Fig. 30, note that the round-bottom isolation structure 294 is disposed between the left-hand and right-hand gate electrode layers 266) “and separating the first gate electrode and the second gate electrode” (You [0032] and [0045]; Fig. 30, note that the round-bottom isolation structure 294 separates the left-hand gate electrode layer 266 from the right-hand gate electrode layer 266).
You, however, does not teach “an insulating pattern between the gate cutting pattern and the concave top surface of the device isolation layer.”
Lin, on the other hand, teaches a device isolation layer (Lin [0060]; Fig. 1S, isolation structure 132B) consisting of an upper layer (Lin [0060]; Fig. 1S, upper isolation layer 130B) with a rounded bottom and a lower layer (Lin [0060]; Fig. 1S, lower isolation layer 126B) with a concave top surface to accommodate the upper layer.
The insulating pattern of Lin can be incorporated into the device of You by splitting the device isolation layer of You into two portions, a lower portion and an upper portion, such that the lower portion has a concave top surface. The upper portion would be directly underneath the gate cutting pattern of You. The combined device teaches “an insulating pattern between the gate cutting pattern and the concave top surface of the device isolation layer” (You [0045]; Fig. 30, round-bottom isolation structure 294; Lin [0060]; Fig. 1S, upper isolation layer 130B; note that the round-bottom isolation structure 294 of You contacts the upper isolation layer 130B of Lin in the combined device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have split the device isolation layer of You into an upper portion and a lower portion as taught by Lin because it would improve the performance of the device of You by reducing parasitic capacitance and it would be a simple combination of elements of the two disclosures.
Regarding claim 2, the combination of You and Lin described in the discussion of claim 1 further teaches “The semiconductor device of claim 1, wherein the insulating pattern is disposed between the first gate electrode and the device isolation layer” (You [0032] and [0045]; Fig. 30, left-hand of the gate electrode layers 266 and round-bottom isolation structure 294; Lin [0060]; Fig. 1S, lower isolation layer 126B and upper isolation layer 130B; note that the upper isolation layer 130B of Lin would contact both the left-hand of the gate electrode layers 266 and the lower isolation layer 126B in the combined device) “and between the second gate electrode and the device isolation layer” (You [0032] and [0045]; Fig. 30, right-hand of the gate electrode layers 266 and round-bottom isolation structure 294; Lin [0060]; Fig. 1S, lower isolation layer 126B and upper isolation layer 130B; note that the upper isolation layer 130B of Lin would contact both the right-hand of the gate electrode layers 266 and the lower isolation layer 126B in the combined device).
Regarding claim 3, the combination of You and Lin described in the discussion of claim 1 further teaches “The semiconductor device of claim 1, wherein a top surface of the insulating pattern includes a portion in contact with the gate cutting pattern” (You [0045]; Fig. 30, round-bottom isolation structure 294; Lin [0060]; Fig. 1S, upper isolation layer 130B; note that the round-bottom isolation structure 294 of You contacts the upper isolation layer 130B of Lin in the combined device).
Regarding claim 4, the combination of You and Lin described in the discussion of claim 1 teaches “The semiconductor device of claim 1” but does not teach “further comprising an insulating layer disposed on a top surface of the insulating pattern.”
Lin, on the other hand, does teach “further comprising an insulating layer disposed on a top surface of the insulating pattern” (Lin [0108]; Fig. 1S, gate insulating layer 176; note that the gate insulating layer 176 contacts the top surface upper isolation layer 130B).
The gate insulating layer of Lin can be incorporated into combined device of You and Lin described in the discussion of claim 1 as a similar insulating layer disposed around the gates and directly over the isolation feature.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have incorporated the gate insulating layer of Lin into the device of You because doing so would provide further insulation of the gate electrodes from other electronic components and it would be a simple combination of elements of the two disclosures.
Regarding claim 5, the combination of You and Lin described in the discussion of claim 1 teaches “The semiconductor device of claim 1, wherein the insulating pattern has an uppermost portion and a lowermost portion” (Lin [0060]; Fig. 1S, note that the upper isolation layer 130B has an upper surface and a lower surface) but does not teach “and wherein a distance between the uppermost portion and the lowermost portion ranges from about 5nm to 50nm.”
Lin, on the other hand, teaches that the distance between the uppermost and lowermost portions of the upper isolation layer is less than 50 nm (Lin [0062]: “In some embodiments, the upper isolation layers 130B have a thickness T5 (in the Z direction), measured from the lowermost point of the bottom surface to the top surface of the upper isolation layers 130B. In some embodiments, the thickness T5 is less than the thickness T4 and may be less than 50 nm.”; Fig. 1I, thickness T5), which overlaps the claimed range.
The thickness of the upper isolation layer of Lin may be incorporated into the combined device of You and Lin described in the discussion of claim 1 by making the thickness of the upper isolation layer less than 50 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have made the upper isolation layer of the combined device of You and Lin described in the discussion of claim 1 with a thickness less than 50 nm because doing so would help to reduce the size of the device and thus improve its performance, and current case law hold that the fact that Lin teaches a range of thicknesses that overlaps the claimed range establishes a prima facie case of obviousness (see MPEP 2144.05 I: “In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)”).
Regarding claim 6, the combination of You and Lin described in the discussion of claim 1 further anticipates “The semiconductor device of claim 1, wherein the insulating pattern includes at least one of silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), or silicon oxycarbonitride” by teaching that the isolation feature may be made of silicon nitride (SiN) (You [0020]: “In an example process, a dielectric material for the isolation feature 216 is first deposited over the semiconductor liner 214 over the workpiece 200, filling the trenches between fin-shaped structures 212 with the dielectric material. In some embodiments, the dielectric material may include… silicon nitride…”).
Regarding claim 7, the combination of You and Lin described in the discussion of claim 1 further teaches “The semiconductor device of claim 1, wherein a top surface of the insulating pattern is a curved surface” (You [0045]; Fig. 30, note the concave portion of the top surface of the isolation feature 216; Lin [0060]; Fig. 1S, upper isolation layer 130B; note that the upper isolation layer 130B has a curved upper surface in the combined device).
Regarding claim 8, the combination of You and Lin described in the discussion of claim 1 further teaches “The semiconductor device of claim 1, wherein a bottom surface of the insulating pattern is disposed on the concave top surface of the device isolation layer” (Lin [0060]; Fig. 1S, note that the lower isolation layer 126B has a concave upper surface within which the upper isolation layer 130B is disposed).
PNG
media_image9.png
661
981
media_image9.png
Greyscale
Fig. 2 of Yemenicioglu, reproduced with annotations added by the examiner.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over You and Lin in view of Yemenicioglu et. al., Pub. No. US 2024/0113106, hereafter referred to as Yemenicioglu.
Regarding claim 9, the combination of You and Lin described in the discussion of claim 1 teaches “The semiconductor device of claim 1” but does not teach “wherein the insulating pattern includes a first insulating portion and a second insulating portion, and wherein the first insulating portion is spaced apart from the second insulating portion by an insulating layer.”
Yemenicioglu, on the other hand, does teach “wherein the insulating pattern includes a first insulating portion and a second insulating portion” (Yemenicioglu [0055]: “In other such example cases, the trenches pass-through the etch stop dielectric material 107…”; Fig. 2, second dielectric material with first and second portions 107), “and wherein the first insulating portion is spaced apart from the second insulating portion by an insulating layer” (Yemenicioglu [0049] and [0055]; Fig. 2, second dielectric material with first and second portions 107, dielectric material structure 124).
The second dielectric material with first and second portions of Yemenicioglu can be implemented as a splitting of the upper buried insulating layer (Lin Fig. 1S, upper isolation layer 130B) of the combination of You and Lin described in the discussion of claim 1 into two portions via an extension of the gate cut pattern as shown in Yemenicioglu (Fig. 2, dielectric material structure 124), with said extension serving as the insulating layer separating the two portions.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have extended the gate cut pattern in the combination of You and Lin described in the discussion of claim 1 such that the insulating pattern is split into two portions, as disclosed by Yemenicioglu, because doing so would have provided better isolation of the two transistors separated by the gate cut and it would have been a simple combination of elements of the two disclosures.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over You and Lin in view of Chang.
Regarding claim 10, the combination of You and Lin described in the discussion of claim 1 teaches “The semiconductor device of claim 1” but does not teach “wherein the first active pattern comprises a pair of first source/drain patterns and a first channel pattern between the pair of first source/drain patterns, the second active pattern comprises a pair of second source/drain patterns and a second channel pattern between the pair of second source/drain patterns, and the insulating pattern extends to cover the first source/drain patterns and the second source/drain patterns.”
Chang, on the other hand, does teach “wherein the first active pattern comprises a pair of first source/drain patterns” (Chang [0035]; Fig. 13A, note that there are several source/drain features 321) “and a first channel pattern between the pair of first source/drain patterns” (Chang [0035]; Fig. 13A, note that there is a set of nanosheet channel layers 306 between two adjacent source/drain features 321), “the second active pattern comprises a pair of second source/drain patterns” (Chang [0035]; Fig. 13A, note that there are several source/drain features 321; also see [0021]: “Channel regions of the multi-gate device 100, which may include a plurality of semiconductor channel layers (e.g., when the multi-gate device 100 includes GAA transistors), are disposed within the fins 104, underlying the gate structures 108, along a plane substantially parallel to a plane defined by the first cutline (A-A) of FIG. 1.” and Fig. 1, noting that Fig. 13A is representative of similar cross sections through the fins 104) “and a second channel pattern between the pair of second source/drain patterns” (Chang [0035]; Fig. 13A, note that there is a set of nanosheet channel layers 306 between two adjacent source/drain features 321; also see [0021] and Fig. 1, noting that Fig. 13A is representative of similar cross sections through the fins 104). Furthermore, Chang teaches a device isolation layer (Chang [0029]; Fig. 13C, STI feature 317) that extends to cover the first source/drain patterns and the second source/drain patterns (Chang [0036]; Fig. 13C, note that the STI feature 317 extends to cover the source/drain features 321).
The plurality of source/drain patterns in the first and second active patterns and the channel patterns interposed between adjacent source/drain patterns can be incorporated into the combined device of You and Lin described in the discussion of claim 1 by forming multiple source/drain patterns within each active area with channels interposed between adjacent source/drains. Furthermore, the shape of the STI features of Chang may be incorporated as a corresponding shape of the device isolation layers of the combination of You and Lin described in the discussion of claim 1. The device isolation layer is then split into two portions as described in the discussion of claim 1. The combined device teaches “and the insulating pattern extends to cover the first source/drain patterns and the second source/drain patterns” (Chang [0036]; Fig. 13C, note that the STI feature 317 extends to cover the source/drain features 321).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have formed multiple source/drain patterns within each active area with channel layers interposed between two adjacent source/drains in the combined device of You and Lin described in the discussion of claim 1 as taught by Chang because doing so allows the device to function as a two-dimensional array of transistors and it would be a simple combination of elements of the two disclosures. Furthermore, it would have been obvious to one of ordinary skill in the art before the effective filing date to use the shape of the STI features of Chang in the combination of You and Lin described in the discussion of claim 1 because such a shape would provide better separation of the transistor structures and it would be a simple combination of elements of the two disclosures.
PNG
media_image10.png
657
928
media_image10.png
Greyscale
Fig. 1 of Liaw, reproduced with annotations added by the examiner.
PNG
media_image11.png
572
930
media_image11.png
Greyscale
Fig. 2 of Liaw, reproduced with annotations added by the examiner.
PNG
media_image12.png
575
903
media_image12.png
Greyscale
Fig. 3 of Liaw, reproduced with annotations added by the examiner.
PNG
media_image13.png
643
1026
media_image13.png
Greyscale
Fig. 4 of Liaw, reproduced with annotations added by the examiner.
PNG
media_image14.png
574
926
media_image14.png
Greyscale
Fig. 5 of Liaw, reproduced with annotations added by the examiner.
PNG
media_image15.png
587
862
media_image15.png
Greyscale
Fig. 7 of Liaw, reproduced with annotations added by the examiner.
PNG
media_image16.png
556
776
media_image16.png
Greyscale
Fig. 9 of Kim, reproduced with annotations added by the examiner.
PNG
media_image17.png
754
718
media_image17.png
Greyscale
Fig. 10A of Kim, reproduced with annotations added by the examiner.
PNG
media_image18.png
684
775
media_image18.png
Greyscale
Fig. 10D of Kim, reproduced with annotations added by the examiner.
Claims 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw in view of Kim and Lin.
Regarding claim 16, Liaw teaches “A semiconductor device” (Liaw [0023]; Fig. 1, GAA device 200) “comprising: a substrate including a logic cell” (Liaw [0025]: “Turning to FIG. 1, the device 200 includes multiple standard (STD) cells where each standard cell includes multiple transistors. The standard cells are separated and isolated from each other by dielectric gates 402 and gate-end dielectric features 404.” and [0026]; Fig. 1, note that the device is divided into cells, and Fig. 2, substrate 202), “the logic cell including a PMOSFET region and an NMOSFET region which are spaced apart from each other in a first direction” (Liaw Fig. 1; note that each cell contains a PMOSFET and an NMOSFET spaced apart along the X direction), “the logic cell having a first boundary, a second boundary, a third boundary, and a fourth boundary” (Liaw [0025]; Fig. 1, note that the cells each have four boundaries defined by the dielectric gates 402 and the gate-end dielectric features 404), “the first boundary and the second boundary disposed opposite to each other in a second direction intersecting the first direction” (Liaw [0025]; Fig. 1, boundaries defined by the dielectric gates 402, which are spaced apart along the Y direction), “and the third boundary and the fourth boundary disposed opposite to each other in the first direction” (Liaw [0025]; Fig. 1, boundaries defined by the gate-end dielectric features 404, which are spaced apart along the X direction); “a device isolation layer provided on the substrate defining a first active pattern on the PMOSFET region and defining a second active pattern on the NMOSFET region” (Liaw [0028-0029]; Figs. 1-3 and 5, doped regions 204A and B and fins 205A and B, and Fig. 3, note that two of the isolation features 230 separate PMOSFET regions from NMOSFET regions; note that the labeling of the doped region in Fig. 5 as 204B is likely an error in the source, as Fig. 1 shows cross-section cut-4 as passing through a doped region 204A), “the first active pattern and the second active pattern extending in the second direction” (Liaw [0028]; Figs. 1-2 and 5, doped regions 204A and B and fins 205A and B; note that the labeling of the doped region in Fig. 5 as 204B is likely an error in the source, as Fig. 1 shows cross-section cut-4 as passing through a doped region 204A), “and each of the first active pattern and the second active pattern having an upper portion protruding above the device isolation layer” (Liaw [0029]; Fig. 3, note that the fins 205A and B extend slightly above the isolation features 230); “a gate electrode extending in the first direction and intersecting the first active pattern and intersecting the second active pattern” (Liaw [0025] and [0033]: “As shown in FIGS. 1, 2, and 3, the gate stacks 240 includes a gate dielectric layer 282 and a gate electrode layer 350.”; Fig. 1, note that the gate stacks 240 are oriented along the X direction and intersect the doped regions 204A and B, and Fig. 3, gate electrode layer 350); “a first source/drain pattern disposed in the upper portion of the first active pattern at a first side of the gate electrode” (Liaw [0033]: “…the gate stack 240 for an NMOSFET GAA is disposed between a pair of n-type source/drain features 260A.”; Fig. 4, n-type source/drain features 260A); “a second source/drain pattern disposed in the upper portion of the second active pattern at a second side of the gate electrode” (Liaw [0033]: “The gate stack 240 for a PMOSFET GAA is disposed between a pair of p-type source/drain features 260B…”; Fig. 4, p-type source/drain features 260B); “a pair of gate spacers on sidewalls of the gate electrode, the pair of gate spacers extending in the first direction” (Liaw [0025]; Fig. 1, note that the gate sidewall spacers 247 extend along the X direction); “a gate capping pattern on the gate electrode” (Liaw [0037]; Fig. 2, gate-top dielectric layer 408); “an isolation structure provided on at least one of the first boundary or the second boundary” (Liaw [0025]; Fig. 1, note that the first and second boundaries of the cells are defined by dielectric gates 402); “a gate cutting pattern provided on at least one of the third boundary or the fourth boundary” (Liaw [0025]; Fig. 1, note that the third and fourth boundaries of the cells are defined by gate-end dielectric features 404), “the gate cutting pattern having a lower portion provided between the pair of gate spacers” (Liaw [0025]; Fig. 7, note that a lower portion of the gate-end dielectric features 404 is disposed between the gate sidewall spacers 247), “and the gate cutting pattern aligned with the gate electrode in the first direction” (Liaw [0025]; Fig. 1, note that the gate-end dielectric features 404 are aligned with the gate stacks 240 along the X direction in the sense that the walls of the gate-end dielectric features 404 are lined up with those of the gate stacks 240); “an interlayer insulating layer on the gate capping pattern and the gate cutting pattern” (Liaw [0040]; Figs. 5 and 7, note that the inter-layer dielectric (ILD) layer 270 is disposed over the gate-top dielectric layer 408 and the gate-end dielectric features 404); “an active contact penetrating the interlayer insulating layer and electrically connected to at least one of the first source/drain pattern or the second source/drain pattern” (Liaw [0035] and [0042]; Fig. 4, note that the source/drain contacts 406 and S/D contact vias 412 penetrate through the ILD layer 270 and are connected to the source/drains 260A and B); and “a gate contact penetrating the interlayer insulating layer and the gate capping pattern and electrically connected to the gate electrode” (Liaw [0042]; Figs. 1-3, gate vias 410; note that Fig. 3 omits the ILD layer 270, but it should be present with the gate vias 410 penetrating through it and the gate-top dielectric layer 408 according to [0041]: “The various features including the S/D features 260A/B, the silicide features 261, the source/drain contacts 406, the gate stacks 240, the dielectric gates 402, the top spacers 247, the inner spacers 255, the gate-end dielectric features 404, and the gate-top dielectric layer 408 are embedded in the ILD layer 270.”, and Fig. 2, which shows a cross section intersecting that of Fig. 3).
However, Liaw does not teach “a first metal layer on the interlayer insulating layer, the first metal layer comprising a power interconnection line vertically overlapping with the gate cutting pattern, and a first interconnection line electrically connected to the active contact and the gate contact, respectively; a second metal layer on the first metal layer, the second metal layer comprising a second interconnection line electrically connected to the first metal layer; and an insulating pattern disposed between the gate cutting pattern and the device isolation layer and between the gate electrode and the device isolation layer.”
Kim, on the other hand, does teach “a first metal layer on the interlayer insulating layer” (Kim [0077]; Fig. 10C, note that the first connection lines M1 is disposed on the interlayer dielectric layer 110), “and a first interconnection line electrically connected to the active contact and the gate contact, respectively” (Kim [0095]; Figs. 10A and D, note that the first lower vias V1_a are connected to the active contacts AC and the second lower vias V1_b are connected to the date electrodes GE); and “a second metal layer on the first metal layer” (Kim [0098]; Figs. 10A and D, note that the second connection lines M2 are disposed above the first connection lines M1), “the second metal layer comprising a second interconnection line electrically connected to the first metal layer” (Kim [0102]; Figs. 10A and D, note that the second connection lines M2 are connected to the first connection lines M1 through the second via V2). Furthermore, Kim teaches two power lines belonging to the first metal layer (Kim [0092-0093]; Fig. 9, first and second lower power lines M1_R1 and M1_R2) that run along boundaries of the device along a second direction (Kim [0055]; Fig. 9, second direction D2) perpendicular to the direction that the gate electrodes are disposed along (Kim [0074]; Fig. 9, note that the gate electrodes GE are disposed along the first direction D1).
The metal layers of Kim can be incorporated into the device of Liaw as a first set of wirings disposed on the device of Liaw electrically connected to the active contact and the gate contact and including two power lines disposed along the first and second edges of a cell and a second set of wirings electrically connected to the first. The combined device teaches “the first metal layer comprising a power interconnection line vertically overlapping with the gate cutting pattern” (Liaw [0025]; Fig. 1, note that the gate-end dielectric features 404 are disposed along boundaries of the cell that are perpendicular to the lengths of the gate stacks 240; Kim [0092-0093]; Fig. 9, first and second lower power lines M1_R1 and M1_R2; note that the first and second power lines M1_R1 and M1_R2 of Kim would vertically overlap the gate-end dielectric features 240 of Liaw in the combined device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have included the wiring layers suggested by Kim in the device of Liaw because these wiring layers provide power to the device, and it would be a simple combination of elements of the two disclosures.
The combination of Liaw and Kim just described, however, does not teach “an insulating pattern disposed between the gate cutting pattern and the device isolation layer and between the gate electrode and the device isolation layer.”
Lin, on the other hand, teaches a device isolation layer (Lin [0060]; Fig. 1S, isolation structure 132B) consisting of an upper layer (Lin [0060]; Fig. 1S, upper isolation layer 130B) with a rounded bottom and a lower layer (Lin [0060]; Fig. 1S, lower isolation layer 126B) with a concave top surface to accommodate the upper layer.
The insulating pattern of Lin can be incorporated into the combined device of Liaw and Kim by splitting the device isolation layer of said device into two portions, a lower portion and an upper portion, such that the lower portion has a concave top surface. The upper portion would be directly underneath the gate cutting pattern of the combined device of Liaw and Kim. The combined device teaches “an insulating pattern disposed between the gate cutting pattern and the device isolation layer and between the gate electrode and the device isolation layer.” (Liaw [0025] and [0033]; Fig. 3, gate-end dielectric feature 404 and gate electrode layer 350; Lin [0060]; Fig. 1S, upper isolation layer 130B; note that the upper isolation layer 130B would contact both the gate-end dielectric feature 404 and the gate electrodes 350 in the combined device).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have split the device isolation layer of You into an upper portion and a lower portion as taught by Lin because it would improve the performance of the device of You by reducing parasitic capacitance and it would be a simple combination of elements of the two disclosures.
Regarding claim 17, the combination of Liaw, Kim, and Lin described in the discussion of claim 16 teaches “The semiconductor device of claim 16” but does not teach “further comprising an insulating layer disposed on a top surface of the insulating pattern.”
Lin, on the other hand, does teach “further comprising an insulating layer disposed on a top surface of the insulating pattern” (Lin [0108]; Fig. 1S, gate insulating layer 176; note that the gate insulating layer 176 contacts the top surface upper isolation layer 130B).
The gate insulating layer of Lin can be incorporated into the combined device of Liaw, Kim, and Lin described in the discussion of claim 16 as a similar insulating layer disposed around the gates and directly over the isolation feature.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have incorporated the gate insulating layer of Lin into the combined device of Liaw, Kim, and Lin described in the discussion of claim 16 because doing so would provide further insulation of the gate electrodes from other electronic components and it would be a simple combination of elements of the two disclosures.
Regarding claim 18, the combination of Liaw, Kim, and Lin described in the discussion of claim 16 teaches “The semiconductor device of claim 16” but does not teach “wherein the insulating pattern includes at least one of silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), or silicon oxycarbonitride.”
Lin, on the other hand, anticipates “wherein the insulating pattern includes at least one of silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), or silicon oxycarbonitride” by teaching that the upper isolation layer can be made from silicon nitride (SiN) (Lin [0056]: “In some embodiments, the insulating material 130 includes… silicon nitride (SiN)…” and [0060]: “The remainder of the insulating material 130 is referred to as an upper isolation layers 130B…”).
The teaching of silicon nitride as a possible material for the upper isolation layer of Lin can be incorporated into the combined device of Liaw, Kim, and Lin described in the discussion of claim 16 by making the upper isolation layer of said combined device out of silicon nitride.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to have used silicon nitride as the material for the upper isolation layer in the combined device of Liaw, Kim, and Lin described in the discussion of claim 16 as taught by Lin because silicon nitride can serve the purpose of an insulator and it would be a simple substitution of one material for another.
Claims 19-20 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw, Kim, and Lin in view of Chang.
Regarding claim 19, the combination of Liaw, Kim, and Lin described in the discussion of claim 16 teaches “The semiconductor device of claim 16” but does not teach “wherein the insulating pattern extends to cover the first source/drain pattern and the second source/drain pattern.”
Chang, on the other hand, teaches a device isolation layer (Chang [0029]; Fig. 13C, STI feature 317) that extends to cover the first source/drain patterns and the second source/drain patterns (Chang [0036]; Fig. 13C, note that the STI feature 317 extends to cover the source/drain features 321).
The shape of the STI features of Chang may be incorporated as a corresponding shape of the device isolation layers of the combination of Liaw, Kim, and Lin described in the discussion of claim 16. The device isolation layer is then split into two portions as described in the discussion of claim 16. The combined device teaches “and the insulating pattern extends to cover the first source/drain patterns and the second source/drain patterns” (Chang [0036]; Fig. 13C, note that the STI feature 317 extends to cover the source/drain features 321).
It would have been obvious to one of ordinary skill in the art before the effective filing date to use the shape of the STI features of Chang in the combination of You and Lin described in the discussion of claim 1 because such a shape would provide better separation of the transistor structures and it would be a simple combination of elements of the two disclosures.
Regarding claim 20, the combination of Liaw, Kim, and Lin described in the discussion of claim 16 teaches “The semiconductor device of claim 16, wherein… the bottom surface of the insulating pattern is disposed on a concave top surface of the device isolation layer” (Lin [0060]; Fig. 1S, lower isolation layer 126B and upper isolation layer 130B; note that the top surface of the lower isolation layer 126B is concave and that the upper isolation layer 130B is disposed on this top surface) but does not teach “wherein a top surface and a bottom surface of the insulating pattern are concave curved surfaces”. Only the bottom surface of the upper isolation layer is curved.
Chang, on the other hand, teaches a device isolation layer (Chang [0029]; Fig. 13C, STI feature 317) that has a curved upper surface with a gate cutting pattern disposed on said upper surface (Chang [0029] and [0041]; Fig. 13B, note that the STI feature 317 has a curved surface and the dielectric layer 402 extends to contact said curved surface).
The shape of the STI features of Chang may be incorporated as a corresponding shape of the device isolation layers of the combination of Liaw, Kim, and Lin described in the discussion of claim 16. The device isolation layer is then split into two portions as described in the discussion of claim 16. The combined device teaches “wherein a top surface and a bottom surface of the insulating pattern are concave curved surfaces” (Lin [0060]; Fig. 1S, note that the bottom surface of the upper isolation layer 130B is curved; Chang [0029]; Fig. 13B, note that a portion of the upper surface of the STI feature 317 is curved).
It would have been obvious to one of ordinary skill in the art before the effective filing date to use the shape of the STI features of Chang in the combined device of Liaw, Kim, and Lin described in the discussion of claim 16 because such a shape would provide better separation of the transistor structures and it would be a simple combination of elements of the two disclosures.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Robert E Throckmorton whose telephone number is (571) 272-7014. The examiner can normally be reached 7:30 AM - 11:30 AM and 12:30 PM - 4:30 PM ET Monday to Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven H Loke can be reached at (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/R.E.T./Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights