DETAILED ACTION
This communication is in response to the Request for Continued Examination (RCE) and Amendment filed on November 26, 2025 in which claims 1-20 are pending in the application. Claims 1, 15, and 19 are in independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Final Office Action is in response to the applicant’s remarks, amendments and arguments filed on November 26, 2025.
Claims 1-20 were previously pending. Claims 1, 15 and 19 are amended. No claims have been added or canceled.
Claims 1-20 remain pending in the application. Claims 1-20 are being considered on the merits.
The objection to the specification related to the title not being descriptive previously set forth in the Final Office Action mailed on August 26, 2025, has been withdrawn due to the amendment filed November 26, 2025.
Response to Arguments
The applicant’s remarks, amendments and/or arguments, filed on November 26, 2025 have been fully considered with the following result(s).
The examiner is entitled to give claim limitations their broadest reasonable interpretation in light of the specification. See MPEP 2111 [R-1] Interpretation of Claims-Broadest Reasonable Interpretation. The applicant always has the opportunity to amend the claims during prosecution, and broad interpretation by the examiner reduces the possibility that the claim, once issued, will be interpreted more broadly than is justified. In re Prater, 162 USPQ 541,550-51 (CCPA 1969).
Applicant’s arguments, filed November 26, 2025, with respect to the rejection(s) of claim(s) 1-20 under 35 USC 103 have been fully considered but they are not persuasive.
Applicant argues that “The Examiner asserts that the newly cited reference Anderson discloses "DMA or emulation accesses trigger state change before formal idle mode exit", thus the previously amended claim 1 is obvious from the disclosures of the cited references Kim '272 and Anderson.
However, the cited reference Anderson discloses that the state change is triggered
"during the formal idle mode", and it is different from the present invention according to claim 1 that the controller of the storage device transmits the device information to the external device (e.g., host device) "before entering the idle mode" and also "before receiving the idle mode control signal indicating to enter the idle mode".
The device information is used to determine a method or a type of the idle mode, and the idle mode control signal is generated based on the device information which is transmitted by the controller of the storage device "before that the storage device enters the idle mode".
Furthermore, the cited reference Kim '272 discloses that the internal information is
selected and transmitted "during the idle period", thus Kim '272 does not disclose that the device information is set and transmitted before entering the idle mode of the storage device.
Consequently, none of the cited references, either individually or in combination, disclose that the device information which is used for determining the idle mode is set and transmitted by the storage device before the storage device enters the idle mode. Additionally, none of the cited references, either individually or in combination, disclose that the idle mode control signal is generated based on the device information received before the storage device enters the idle mode.”
Examiner respectfully disagrees with applicant’s arguments for the following reasons.
Kim ‘272 discloses the limitation “set device information based on a state of the memory, the state being associated with the operation according to the internal command before entering an idle mode” as taught in Para [0064], [0068], [0083] where “Mode register stores info selection signal for selecting internal info (e.g., refresh, power-down, temp, etc.)”. It is to be noted that “Device information” = internal status; “internal command” = self-refresh, power-down, etc. occurs before entering the idle mode.
Kim ‘272 further discloses the limitation “transmit the device information to an external device through a response unit corresponding to a command unit according to the external command before receiving an idle mode control signal” as taught in Para [0049], [0077], [0084] where “Selected internal info transmitted to memory controller during idle period.” It is noted that the info is sent during idle, after receiving command, before any new control signal.
As such, the combination of references discloses the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 9-10, 14-16 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘272 (US 2016/0224272 A1) and Anderson et al. (US 2008/0068239 A1).
As per claim 1, Kim ‘272 discloses a storage device comprising:
a memory [Para [0020], [0047], [0101], memory device]; and a controller [Para [0020], [0047], [0101], Fig. 1, memory controller 110] configured to:
control an operation of the memory according to an external command or an internal command [Para 0020-0022, performing an operation in response to a command; Para [0048], [0067], [0107], Command decoder receives command, controls memory operation, e.g., read/write/self-refresh. “External command” = host/MCU command; “internal command” = self-refresh, power-down, etc.];
set device information based on a state of the memory, the state being associated with the operation according to the internal command before entering an idle mode [Para 0049, Para 0072, selects internal information based on state (functions, modes, self-refresh, power-down, temperature); Para [0064], [0068], [0083], Mode register stores info selection signal for selecting internal info (e.g., refresh, power-down, temp, etc.). “Device information” = internal status; “internal command” = self-refresh, power-down, etc.];
transmit the device information to an external device through a response unit corresponding to a command unit according to the external command before receiving an idle mode control signal, [Para [0015], [0049], [0077], [0084], transmits selected internal (device) information to an external controller during idle period; “Info is sent during idle, after receiving command, before any new control signal.”],
wherein the idle mode control signal controls the idle mode of the storage device [Para [0055], [0082], Power-down/self-refresh command triggers idle mode; status info sent to controller. “The controller can use this info to control power state”]; and
receive the idle mode control signal configured based on the device information, and enter the idle mode according to the idle mode control signal [Para [0055], [0082], [0094], memory device 200 may detect that the state of the memory device 200 has transited to the idle period, and generate an idle signal IDLE in response to the self-refresh command and the power-down command; Para [0011], [0055], [0094], the memory controller sending commands (e.g., power-down) based on the device’s status.]. “Memory device enters power-down/self-refresh mode upon command; info sent to controller. Same functional result.”
Kim ‘272 discloses the invention as detailed above for claim 1. However, Kim ‘272 does not explicitly teach transmitting the information before receiving an idle mode control signal as required by claim 1.
Anderson discloses transmitting the information before receiving an idle mode control signal [Para 0007, 0094-0099, DMA or emulation accesses trigger state change before formal idle mode exit].
Both Kim ‘272 and Anderson are in the same field of endeavor and they are both in the data processor and memory power control technology and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Kim with the teachings of Anderson in order to transmit the information before receiving an idle mode control signal.
Modification would improve the overall power efficiency of the system by increasing processing power and data transfer rates and maintaining the functionality of the system without hangs while minimizing the power contribution of the DSP core as taught by Anderson (Para 00080).
As per claim 9, Kim ‘272 discloses the storage device of claim 1, wherein the idle mode control signal indicates an idle period of the storage device [Para 0082, 0083, detecting a transition to an idle period…], and wherein the controller is further configured to receive a sleep mode setting signal when the idle period ends [Para 0011, 0055, 0094 The memory controller may control the memory device to enter a power-down mode…Power-down/self-refresh commands control sleep/idle state; status info sent to controller]. It is noted that power-down followed by sleep signals as is well known in the art.
As per claim 10, Kim ‘272 discloses the storage device of claim 9, wherein the controller is further configured to stop, when receiving the idle mode control signal subsequently provided after the sleep mode setting signal, a supply of at least one operating voltage to the memory during the idle period corresponding to the subsequent idle mode control signal [Para 0095- 0099, The PMIC 710 may block the supply of the operating power to the memory controller 110 and the memory device 200, when the operating status information indicating that the memory device 200 is in the power-down mode is transferred…]. “PMIC can block power based on power-down info.”
As per claim 14, Anderson discloses the storage device of claim 1, wherein the controller is further configured to transmit an idle mode control response signal to the external device during the receiving of the idle mode control signal [Para 0095-0096, each component is responsible to update its signal back indicating power-down status].
As per claim 15, Kim ‘272 discloses a computing system comprising:
a storage device configured to: control, according to an external command or an internal command, an operation of a memory included therein [Para 0005, 0044, The memory controller controls the memory device while based on an internal status of the memory device],
set device information based on a state of the memory, the state being associated with the operation according to the internal command before entering an idle mode [Abstract, 0010, 0072, The memory device selects at least one from among information about functions, characteristics and modes…, Para [0043], [0094], [0133], System with memory device, controller; device sends internal info to controller, controller may control power state. Functionally similar.], and
transmit the device information to a host device through a response unit corresponding to a command unit according to the external command before receiving an idle mode control signal, when the idle mode control signal controls the idle mode of the storage device [Abstract, 0015, 0084, outputting the selected internal information during the idle period…The memory device transfers the selected internal information to a memory controller; Para [0043], [0094], [0133], System with memory device, controller; device sends internal info to controller, controller may control power state. Functionally similar.];
wherein the host device configured to: set an idle period corresponding to the device information [Para 0011, 0055, 0094, The memory controller may control the memory device to enter a power-down mode in response to a power-down command…], and
transmit, to the storage device, the idle mode control signal indicating the idle period, and wherein the storage device is configured to enter the idle mode according to the idle mode control signal [Para 0011, 0055, 0094, The memory controller may control the memory device to enter a power-down mode in response to a power-down command…].
Kim ‘272 discloses the invention as detailed above for claim 15. However, Kim does not explicitly teach transmitting the information before receiving an idle mode control signal as required by claim 15.
Anderson discloses transmitting the information before receiving an idle mode control signal [Para 0007, 0094-0099, DMA or emulation accesses trigger state change before formal idle mode exit].
Both Kim ‘272 and Anderson are in the same field of endeavor and they are both in the data processor and memory power control technology and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Kim ‘272 with the teachings of Anderson in order to transmit the information before receiving an idle mode control signal.
Modification would improve the overall power efficiency of the system by increasing processing power and data transfer rates and maintaining the functionality of the system without hangs while minimizing the power contribution of the DSP core as taught by Anderson [Para 0008].
As per claim 16, Kim ‘272 discloses the computing system of claim 15, wherein the host device is further configured to provide, when the idle period ends, the storage device with a sleep mode setting signal and then with a subsequent idle mode control signal [Para 0011, 0055, 0094, The memory controller may control the memory device to enter a power-down mode…].
As per claim 19, Kim ‘272 discloses a controller comprising:
a device information configuration module configured to set device information based on a state of a memory before entering an idle mode, the state being associated with an operation of the memory and the operation being performed according to an internal command [Para 0010, 0067-0068, 0072, mode register configured to store an information selection signal for selecting internal information of the memory device and outputting the selected internal information during the idle period];
a data signal transmission module configured to transmit the device information to an external device through a response unit corresponding to a command unit received from the external device, wherein the device information is transmitted before receiving an idle mode control signal, wherein the idle mode control signal controls the controller and the memory [Para 0015, 0083-0084, a data pad configured to transmit the selected internal information to an external device during the idle period]; and
a control signal reception module configured to receive an idle mode control signal corresponding to the device information, wherein the controller and the memory enter the idle mode according to the idle mode control signal [Para 0011, 0055, 0094, The memory controller may control the memory device to enter a power-down mode in response to a power-down command…].
Kim ‘272 discloses the invention as detailed above for claim 19. However, Kim does not explicitly teach transmitting the information before receiving an idle mode control signal as required by claim 19.
Anderson discloses transmitting the information before receiving an idle mode control signal [Para 0007, 0094-0099, DMA or emulation accesses trigger state change before formal idle mode exit].
Both Kim ‘272 and Anderson are in the same field of endeavor and they are both in the data processor and memory power control technology and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Kim ‘272 with the teachings of Anderson in order to transmit the information before receiving an idle mode control signal.
Modification would improve the overall power efficiency of the system by increasing processing power and data transfer rates and maintaining the functionality of the system without hangs while minimizing the power contribution of the DSP core as taught by Anderson [Para 0008].
As per claim 20, Anderson discloses the controller of claim 19, further comprising a control response signal transmission module configured to transmit, in response to the idle mode control signal, an idle mode control response signal to the external device [Para 0095-0096, each component is responsible to update its signal back indicating power-down status].
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘272 (US 2016/0224272 A1) and Anderson et al. (US 2008/0068239 A1) and further in view of He et al. (US 2022/0300061 A1).
As per claim 2, Kim ‘272 discloses the storage device of claim 1, wherein the device information is one of first state information and second state information [Para 0010, 0018, 0072, The selected internal information may include at least one of a function, a characteristic, and a mode…], wherein the idle mode control signal indicates an idle period of the storage device [Para 0082, 0064, 0083, detecting a transition to an idle period, which is a data idle period, based on the received command. Mode register selects which internal info to transmit (e.g., function, refresh, temp, power-down); controller can act accordingly]. “State info” = selected internal info; controller may set different idle periods.
Kim’272 further discloses different state information [Para 0010, 0088, 0090, the memory device may select at least one from among the mode register information…]. Mode register selects which internal info to transmit (e.g., function, refresh, temp, power-down); controller can act accordingly. “State info” = selected internal info; controller may set different idle periods.
The combination of Kim ‘272 and Anderson does not specifically teach the idle period corresponding to the first state information is different from the idle period corresponding to the second state information.
He discloses the idle period corresponding to the first state information is different from the idle period corresponding to the second state information [Para 0011, he memory system may consume excess power by remaining in the second power state throughout the duration of the host system's idle mode—e.g., if the duration of the idle mode is relatively long].
Kim ‘272 and Anderson and He are in the same field of endeavor and they are both in the data processor and memory power control technology and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Kim ‘272 and Anderson with the teachings of He in order to for the memory devices to maintain their programmed states for extended periods of time.
Modification would improve the overall power efficiency of the system by allowing the memory system to conserve power by transitioning to another power state in response to the host system being in the idle mode for a relatively long time as taught by He (Para 0013).
Claim(s) 3-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘272 (US 2016/0224272 A1) and Anderson et al. (US 2008/0068239 A1) and further in view of Kim ‘747 (US 2019/0179747 A1.
As per claim 3, the combination of Kim ‘272 and Anderson discloses the claimed invention as detailed above for claim 1. Kim ‘272 discloses a buck-boost converter 714 and boost Regulator 718 in Fig. 7. The combination of Kim ‘272 and Anderson does not specifically teach the state of the memory is a remaining capacity of a write booster buffer included in the memory as recited in the claim.
Kim ‘747 discloses the storage device of claim 1, wherein the state of the memory is a remaining capacity of a write booster buffer included in the memory [Para 0003, a memory system that uses or embeds at least one memory device, i.e., a data storage device; Para 0034-0035, Valid data and invalid data can be counted for measuring the usage level. The usage level is determined based on a classified range regarding a ratio of an amount of both valid data and invalid data to the storage capacity.]. It is noted that Kim ‘747 the use of a memory system embedding a memory device. A booster buffer combines the functions of a buffer and a boost and is designed to amplify the current of a signal without significantly altering its voltage or tone to provide the benefits of both signal integrity and volume boost as is well known in the art.
Kim ‘272 and Anderson and Kim ‘747 are in the same field of endeavor and they are both in the data processor and memory power control technology and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Kim ‘272 and Anderson with the teachings of Kim ‘747 in order to use the host’s idle status to secure storage capacity of a memory system (Para 0029).
Modification would improve the overall power efficiency of the system by reducing power consumption of the memory system as taught by Kim ‘747 (Para 0036).
As per claim 4, Kim ‘272 discloses the storage device of claim 1 wherein the idle mode control signal indicates an idle period of the storage device [Para 0082, 0083, detecting a transition to an idle period…]. Kim ‘272 does not specifically teach wherein the idle period is inversely proportional to a remaining capacity of the write booster buffer.
Kim ‘747 teaches wherein the idle period is inversely proportional to a remaining capacity of the write booster buffer [Para 0032, Embodiments of the disclosure can avoid deteriorating performance of the memory system during the host's idle state; Para 0034-0035, Valid data and invalid data can be counted for measuring the usage level. The usage level is determined based on a classified range regarding a ratio of an amount of both valid data and invalid data to the storage capacity; The classified range can be determined based on the storage capacity].
Kim ‘272 and Anderson and Kim ‘747 are in the same field of endeavor and they are both in the data processor and memory power control technology and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Kim ‘272 and Anderson with the teachings of Kim ‘747 in order to use the host’s idle status to secure storage capacity of a memory system (Para 0029).
Modification would improve the overall power efficiency of the system by reducing power consumption of the memory system as taught by Kim ‘747 (Para 0036).
As per claim 5, Kim ‘747 discloses the storage device of claim 1, wherein the controller is further configured to receive a sleep mode setting signal before the idle mode control signal when a remaining capacity of a write booster buffer included in the memory is equal to or greater than a preset value [Para 0035, the memory device has a larger storage capacity, the range may be densely classified (e.g., 10% to 5%, 5% to 3% for each class) or close to full storage capacity (e.g., 80% to 90%, 90% to 95% for a trigger reference); Para 0048, the first command can include a hibernate command or a sleep command used for reducing power consumption].
As per claim 6, the combination of Kim ‘272 and Anderson discloses the claimed invention as detailed above for claim 6. The combination of Kim ‘272 and Anderson does not specifically teach the state of the memory is a level at which garbage collection is required for the memory.
Kim ‘747 discloses the storage device of claim 1, wherein the state of the memory is a level at which garbage collection is required for the memory [Para 0030-0034, determining an operation state of the memory device and carrying out garbage collection to the memory device in response to the operation state; controller may determine the operation state based on a usage level against a storage capacity of the memory device].
Kim ‘272 and Anderson and Kim ‘747 are in the same field of endeavor and they are both in the data processor and memory power control technology and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Kim ‘272 and Anderson with the teachings of Kim ‘747 in order to use the host’s idle status to secure storage capacity of a memory system, or make the memory system be in a clean state (Para 0029).
Modification would improve the overall power efficiency of the system by reducing power consumption of the memory system as taught by Kim ‘747 (Para 0036).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘272 (US 2016/0224272 A1) and Anderson et al. (US 2008/0068239 A1) and further in view of Fu et al. CN 114968839 A).
As per claim 7, the combination of Kim ‘272 and Anderson discloses the invention as detailed above for claim 1. Kim ‘272 teaches the storage device of claim 1 wherein the idle mode control signal indicates an idle period of the storage device [Para 0082, 0083, detecting a transition to an idle period…].
The combination of Kim ‘272 and Anderson does not specifically teach wherein the idle period is proportional to a level at which garbage collection is required for the memory.
Fu discloses the idle period is proportional to a level at which garbage collection is required for the memory [Page 5, Para 4, The garbage recycling trigger condition can be specifically as follows: the number of idle data block is less than the garbage recycling starting threshold value, and/or detecting the error of the data block.].
Kim ‘272 and Anderson and Fu are in the same field of endeavor and they are both in the data storage technology and garbage collection filed, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Kim ‘272 and Anderson with the teachings of Fu in order to detect and set the storage system garbage collection conditions.
Motivation would improve the execution efficiency of the garbage recycling task as taught by Fu (abstract).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘272 (US 2016/0224272 A1) and Anderson et al. (US 2008/0068239 A1) and Kim ‘747 (US 2019/0179747 A1) and further in view of Fu et al. CN 114968839 A).
As per claim 8, the combination of Kim ‘272 and Anderson and Kim ‘747 discloses the claimed invention as detailed above for claim 1. Kim ‘747 discloses the storage device of claim 1, wherein the controller is further configured to receive a sleep mode setting signal before the idle mode control signal [Para 0048, the first command can include a hibernate command or a sleep command used for reducing power consumption].
The combination of Kim ‘272 and Anderson and Kim ‘747 does not specifically teach the
mode setting signal when a level at which garbage collection is required for the memory is less than or equal to a preset level.
Fu discloses idle data blocks when a level at which garbage collection is required for the memory is less than or equal to a preset level [Page 5, Para 4, The garbage recycling trigger condition can be specifically as follows: the number of idle data block is less than the garbage recycling starting threshold value, and/or detecting the error of the data block.].
Kim ‘272 and Anderson and Kim ‘747 and Fu are in the same field of endeavor and they are both in the data storage technology and garbage collection filed, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Kim ‘272 and Anderson and Kim ‘747 with the teachings of Fu in order to detect and set the storage system garbage collection conditions.
Motivation would improve the execution efficiency of the garbage recycling task as taught by Fu (abstract).
Claim(s) 11 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘272 (US 2016/0224272 A1) and Anderson et al. (US 2008/0068239 A1) and further in view of Cariello (US 2022/0237079 A1).
As per claim 11, the combination of Kim ‘272 and Anderson discloses the invention as detailed above for claim 1. Kim ‘272 further discloses the storage device of claim 1, wherein the controller transmits the device information in a response unit transmitted to the external device [Abstract, Para 0015, 0084, The memory device transfers the selected internal information to a memory controller; Para [0064], [0077], [0084], Mode register stores info selection signal; info sent as INFO_DATA via DQ bus].
Kim ‘272 does not explicitly teach transmits the device information through one or more bits included in an exception event status field included in a response unit as recited in the claim.
Cariello discloses transmits the device information through one or more bits included in an exception event status field included in a response unit [Para 0075-0078, bits 7-15 may be reserved and those bits can be used to communicate the additional fault conditions described herein. In some cases, at least some of bits 7-15 may be mapped to fault conditions].
Kim ‘272 and Anderson and Cariello are in the same field of endeavor and they are both in the data processor and memory power control technology and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Kim ‘272 and Anderson with the teachings of Cariello to include transmitting the exception event through one or more bits included in an exception event status field in order to accelerate the failure analysis to identify the causes of the fault condition.
Motivation would allow the memory system to quickly address the fault condition, improve latency in error handling, and prevent future fault conditions from occurring As taught by Cariello (Para 0063).
As per claim 12, Cariello discloses the storage device of claim 11, wherein the one or more bits are at least a part of 8th to 16th bits among 16 bits included in the exception event status field [Para 0075-0078, bits 7-15 may be reserved and those bits can be used to communicate the additional fault conditions described herein. In some cases, at least some of bits 7-15 may be mapped to fault conditions].
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘272 (US 2016/0224272 A1) and Anderson et al. (US 2008/0068239 A1) and Satoru (JP 5582345 B2) and further in view of Kim ‘747 (US 2019/0179747 A1.
As per claim 17, the combination of Kim ‘272 and Anderson teaches the claimed invention as detailed above in claim 15. Kim ‘272 discloses the computing system of claim 15, wherein the device information includes one or more bits indicating the state [Para 0069, 0084, The information selection signal INFO_SEL is provided as at least one piece of bit information…].
The combination of Kim ‘272 and Anderson does not specifically teach wherein the host device is further configured to provide, when the one or more bits are not set or all the one or more bits are set to the same value, the storage device with a sleep mode setting signal before the transmission of the idle mode control signal.
Satoru discloses providing, when the one or more bits are not set or all the one or more bits are set to the same value, the storage device with a sleep mode setting signal [Page 4, Para 3, The sleep control unit 102E communicating with the request processing monitoring unit 102A checks the internal variable and determines whether there is a set bit. If all bits are set to zero, sleep is permitted, and if even one bit is set, the process waits without performing sleep processing.].
Kim ‘272 and Anderson and Satoru are in the same field of endeavor and they are both in the data processor and memory power control technology and, therefore, are combinable/modifiable.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the teachings of Kim ‘272 and Anderson with the teachings of Satoru to include a sleep processing unit that stops a CPU during idle times of a plurality of request processes.
Motivation would provide a simplified complicated sleep process and can accurately execute the sleep process with easy judgment control as taught by Satoru (Page 3, Para 1).
Allowable Subject Matter
Claims 13 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20230229218 A1 to Choi et al teaches a storage device configured to: transmit, to an exterior, prediction information, for each power mode, that indicates a predicted time for performing a background operation for managing a memory device; and perform the background operation in an idle state of the storage device by switching to a corresponding power mode in response to a power mode control signal that is received in the idle state; and a control device configured to: determine a power mode of the storage device and an idle time for the idle state during which the background operation is performed based on the prediction information; transmit the power mode control signal to the storage device; and suspend, during the idle time, execution of a command processing request transmitted to the storage device (Para 0007).
Examiner has cited particular columns/paragraphs/sections and line numbers in the references applied and not relied upon to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
When responding to the Office action, applicant is advised to clearly point out the patentable novelty the claims present in view of the state of the art disclosed by the reference(s) cited or the objections made. A showing of how the amendments avoid such references or objections must also be present. See 37 C.F.R. 1.111(c).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Pierre M. Vital whose telephone number is (571)272-4215. The examiner can normally be reached Mon-Fri, 8:00a-4:00p.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dede Zecher can be reached at (571) 272-7771. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
August 22, 2025
/PIERRE VITAL/Supervisory Patent Examiner, Art Unit 2162
Prosecution Insights