Prosecution Insights
Last updated: April 19, 2026
Application No. 18/465,195

CONTROLLED TRANSITION TO REGULATION

Non-Final OA §102
Filed
Sep 12, 2023
Examiner
NGUYEN, KHANH V
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
2y 3m
To Grant
96%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allow Rate
1105 granted / 1181 resolved
+25.6% vs TC avg
Minimal +2% lift
Without
With
+1.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
27 currently pending
Career history
1208
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
28.8%
-11.2% vs TC avg
§102
39.6%
-0.4% vs TC avg
§112
27.2%
-12.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1181 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 6, 8 and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Amemiya et al. (9,553,461), hereafter called AMEMIYA. Regarding claim 1, AMEMIYA (Fig. 2) discloses a switch control circuit comprising: receiving, by a regulating circuit (35), a battery feedback parameter via terminal (Va); producing, by an operational transconductance amplifier (62/Gm), a first output current at an output terminal based on the battery feedback parameter (Va) and a battery current regulation voltage (61); and producing, by a current source (73), a second current at the output terminal based on the battery feedback parameter and a reference voltage (70). Regarding claim 6, wherein producing the second current comprises closing a switch (72) coupling the current source (73) to the output terminal of transconductance amplifier (62/Gm). Regarding claim 8, AMEMIYA (Fig. 2) discloses a switch control circuit comprising: an operational transconductance amplifier (62/Gm) having a first operational transconductance amplifier input (Va/inverting terminal), a second operational transconductance amplifier input (V1/non-inverting terminal), and an operational transconductance amplifier output; a switch (72) having a first switch terminal, a second switch terminal, and a switch control terminal, the second switch terminal coupled to the operational transconductance amplifier output; and a comparator (71) having a first comparator input (-), a second comparator input (+), and a comparator output, the comparator output coupled to the switch control terminal of switch (72). Regarding claim 9, wherein the first comparator input (-) is coupled to the first operational transconductance amplifier input (-/Va) and the second comparator input (+) is coupled to a voltage source (70/V2). Claim(s) 1-6, 8 and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li (10,348,101). Regarding claim 1, Li (Fig. 2B) discloses a battery management module (200’) comprising: receiving at non-inverting terminal (+) of OTA (214B), by a regulating circuit (200’), a battery feedback parameter (202); producing, by an operational transconductance amplifier (214B), a first output current at an output terminal based on the battery feedback parameter (202) and a battery current regulation voltage (228); and producing, by a current source (206), a second current at the output terminal based on the battery feedback parameter and a reference voltage, see comparator (214A) having non-inverting terminal (+) coupled to the battery feedback parameter and inverting terminal coupled to reference voltage (226), wherein output of comparator is fed into logic control, which controls ON/OFF of switch (SW2). Regarding claim 2, wherein the battery feedback parameter is a sensed battery current, see RSEN, which coupled to non-inverting terminal (+) of transconductance amplifier (214B). Regarding claim 3, wherein producing the second current at the output terminal is further performed based on comparing (214A) the sensed battery current (non-inverting terminal (+) of comparator (214A) coupled to RSEN and a voltage reference (226). Regarding claim 4, wherein the battery feedback parameter (202) is a sensed battery voltage (VSEN). Regarding claim 5, wherein producing the second current at the output terminal o transconductance amplifier (214B) is further performed based on comparing the sensed battery voltage (voltage to non-inverting terminal of OTA (214B)) to a voltage of a voltage source (226). Regarding claim 6, wherein producing the second current comprises closing a switch (SW2) coupling the current source (206) to the output terminal of transconductance amplifier (214B). Regarding claim 8, Li (Fig. 2B) a battery management module (200’) comprising: an operational transconductance amplifier (214B) having a first operational transconductance amplifier input (+), a second operational transconductance amplifier input (-), and an operational transconductance amplifier output; a switch (SW2) having a first switch terminal, a second switch terminal, and a switch control terminal, the second switch terminal coupled to the operational transconductance amplifier output; and a comparator (214A) having a first comparator input (+), a second comparator input (-), and a comparator output, the comparator output (Scoc) coupled to the switch control terminal of switch (SW2) via control logic (212). Regarding claim 9, wherein the first comparator input (+) is coupled to the first operational transconductance amplifier input (+) and the second comparator input (-) is coupled to a voltage source (226). Allowable Subject Matter Claims 7 and 10-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 15-20 are allowed. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 7, prior art(s) does not disclose producing the second current at the output terminal is further performed based on a voltage at the output terminal. Regarding claims 10 and 11, prior art(s) does not disclose the circuit further comprising: a logic gate having a first logic input, a second logic input, and a logic output, the logic output coupled to the switch control terminal and the first logic input coupled to the first comparator output; and a second comparator having a third comparator input, a fourth comparator input, and a second comparator output, the second comparator output coupled to the second logic input. Regarding claim 12, prior art(s) does not disclose the first comparator input is coupled to the operational transconductance amplifier output and the second comparator input is coupled to a transistor stack. Regarding claim 13, prior art(s) does not disclose the circuit further comprising: a resistor coupled between the operational transconductance amplifier output and the second switch terminal; and a capacitor coupled between the second switch terminal and a ground terminal. Regarding claim 14, prior art(s) does not disclose the circuit further comprising a second operational transconductance amplifier having a third operational transconductance amplifier input, a fourth operational transconductance amplifier input, and a second operational transconductance amplifier output, the third operational transconductance amplifier input coupled to a sensed battery voltage, the fourth operational transconductance amplifier input coupled to a voltage source, and the second operational transconductance amplifier output coupled to the first operational transconductance amplifier output. The following is an examiner’s statement of reasons for allowance: Regarding claims 15-20, among other subject matters claimed, prior art(s) does not disclose a control circuit (330 having a control input and a control output, the control input coupled to the operational transconductance amplifier output and to the second switch terminal; and a power transistor coupled to the control output, the power transistor adapted to be coupled to the battery. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional reference(s) cited in PTO-892 show further analogous prior art circuitry. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Khanh V. Nguyen whose telephone number is (571) 272-1767. The examiner can normally be reached from 8:30 AM – 5:00 PM EST. Examiner interviews are available via telephone and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LINDGREN BALTZELL ANDREA can be reached on (571) 272-5918. The fax phone numbers for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application lnformation Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KHANH V NGUYEN/ Primary Examiner, Art Unit 2843
Read full office action

Prosecution Timeline

Sep 12, 2023
Application Filed
Feb 19, 2026
Non-Final Rejection — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
96%
With Interview (+1.9%)
2y 3m
Median Time to Grant
Low
PTA Risk
Based on 1181 resolved cases by this examiner. Grant probability derived from career allow rate.

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