Office Action Predictor
Last updated: April 15, 2026
Application No. 18/465,207

DIAGNOSIS AND PROGNOSIS OF IGBT MODULES

Non-Final OA §101
Filed
Sep 12, 2023
Examiner
DO, AN H
Art Unit
2853
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Abb Schweiz AG
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
2y 1m
To Grant
97%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allow Rate
1293 granted / 1427 resolved
+22.6% vs TC avg
Moderate +7% lift
Without
With
+6.7%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
25 currently pending
Career history
1452
Total Applications
across all art units

Statute-Specific Performance

§101
11.3%
-28.7% vs TC avg
§103
24.2%
-15.8% vs TC avg
§102
42.7%
+2.7% vs TC avg
§112
4.4%
-35.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1427 resolved cases

Office Action

§101
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on 12 September 2023 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-15 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. Claim 14 recites “A method for diagnosing an IGBT module, the method comprising: maintaining, in a memory, information on a computational model for modelling thermal behavior of layers of the IGBT module, wherein the computational model includes a plurality of inputs having at least dissipated power at semiconductors of the IGBT module and ambient temperature of the IGBT module; obtaining measurements of values of the dissipated power at the semiconductors of the IGBT module and the ambient temperature; determining one or more current values of one or more temperatures of the IGBT module, wherein the determining includes at least obtaining a measurement of a current value of a switching delay of the IGBT module and determining a current value of a junction temperature of the IGBT module based on the current value of the switching delay; and calculating a current estimate of a joint state-parameter space defined for the computational model using a Bayesian filter in combination with the computational model taking as inputs at least the values of the dissipated power and the ambient temperature, wherein the joint state-parameter space includes at least the one or more temperatures of the IGBT module, one or more thermal loss parameters quantifying thermal loss in one or more layers of the IGBT module and one or more wear parameters quantifying a change in the one or more thermal loss parameters over time due to unknown wear, the one or more wear parameters being defined via one or more random processes, the one or more current values of the one or more temperatures being used as observations in the Bayesian filter.” Claim 14, in view of the claim limitations, recites the abstract idea of “maintaining, in a memory, information on a computational model for modelling thermal behavior of layers of the IGBT module, wherein the computational model includes a plurality of inputs having at least dissipated power at semiconductors of the IGBT module and ambient temperature of the IGBT module; obtaining measurements of values of the dissipated power at the semiconductors of the IGBT module and the ambient temperature; determining one or more current values of one or more temperatures of the IGBT module, wherein the determining includes at least obtaining a measurement of a current value of a switching delay of the IGBT module and determining a current value of a junction temperature of the IGBT module based on the current value of the switching delay; and calculating a current estimate of a joint state-parameter space defined for the computational model using a Bayesian filter in combination with the computational model taking as inputs at least the values of the dissipated power and the ambient temperature, wherein the joint state-parameter space includes at least the one or more temperatures of the IGBT module, one or more thermal loss parameters quantifying thermal loss in one or more layers of the IGBT module and one or more wear parameters quantifying a change in the one or more thermal loss parameters over time due to unknown wear, the one or more wear parameters being defined via one or more random processes, the one or more current values of the one or more temperatures being used as observations in the Bayesian filter.” As a whole, in view of the claim limitations, but for the computer components and systems performing the claimed functions, the broadest reasonable interpretation of the recited “maintaining, in a memory, information on a computational model for modelling thermal behavior of layers of the IGBT module, wherein the computational model includes a plurality of inputs having at least dissipated power at semiconductors of the IGBT module and ambient temperature of the IGBT module; obtaining measurements of values of the dissipated power at the semiconductors of the IGBT module and the ambient temperature; determining one or more current values of one or more temperatures of the IGBT module, wherein the determining includes at least obtaining a measurement of a current value of a switching delay of the IGBT module and determining a current value of a junction temperature of the IGBT module based on the current value of the switching delay; and calculating a current estimate of a joint state-parameter space defined for the computational model using a Bayesian filter in combination with the computational model taking as inputs at least the values of the dissipated power and the ambient temperature, wherein the joint state-parameter space includes at least the one or more temperatures of the IGBT module, one or more thermal loss parameters quantifying thermal loss in one or more layers of the IGBT module and one or more wear parameters quantifying a change in the one or more thermal loss parameters over time due to unknown wear, the one or more wear parameters being defined via one or more random processes, the one or more current values of the one or more temperatures being used as observations in the Bayesian filter.”; therefore, the claim recites mental processes. Accordingly, the claim recites a mental process, and thus, the claim recites an abstract idea under the first prong of Step 2A. This judicial exception is not integrated into a practical application under the second prong of Step 2A. In particular, the claim recites the additional elements beyond the recited abstract idea of“[a] computer- implemented method” and “the method is carried out by one or more physical processors configured by machine-readable instructions” as recited in claims 1, 13 and 15, individually and when viewed as an ordered combination, and pursuant to the broadest reasonable interpretation, each of the additional elements are computing elements recited at high level of generality implementing the abstract idea on a computer (i.e. apply it), and thus, are no more than applying the abstract idea with generic computer components. Moreover, aside from the aforementioned additional elements, the remaining elements of dependent claims 2-12 do not integrate the abstract idea into a practical application because these claims merely recite further limitations that provide no more than simply narrowing the recited abstract idea. The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception under Step 2B. As noted above, the aforementioned additional elements beyond the recited abstract idea, as an order combination, are no more than mere instructions to implement the idea using generic computer components (i.e. apply it), and further, generally link the abstract idea to a field of use, which is not sufficient to amount to significantly more than an abstract idea; therefore, the additional elements are not sufficient to amount to significantly more than an abstract idea. Additionally, these recitations as an ordered combination, simply append the abstract idea to recitations of generic computer structure performing generic computer functions that are well-understood, routine, and conventional in the field as evinced by Applicant’s Specification at [0135] (describing that the disclosure is not limited to the disclosed implementations, but, on the contrary, is intended to cover modifications and equivalent arrangements that are within the spirit and scope of the appended claims). Furthermore, as an ordered combination, these elements amount to generic computer components performing repetitive calculations, receiving or transmitting data over a network, which, as held by the courts, are well-understood, routine, and conventional. See MPEP 2106.05(d); July 2015 Update, p. 7. Moreover, aside from the aforementioned additional elements, the remaining elements of dependent claims 2-12 do not transform the recited abstract idea into a patent eligible invention because these claims merely recite further limitations that provide no more than simply narrowing the recited abstract idea. Looking at these limitations as an ordered combination adds nothing additional that is sufficient to amount to significantly more than the recited abstract idea because they simply provide instructions to use a generic arrangement of generic computer components and recitations of generic computer structure that perform well-understood, routine, and conventional computer functions that are used to “apply” the recited abstract idea. Thus, the elements of the claims, considered both individually and as an ordered combination, are not sufficient to ensure that the claim as a whole amounts to significantly more than the abstract idea itself. Since there are no limitations in these claims that transform the exception into a patent eligible application such that these claims amount to significantly more than the exception itself, claims 1-15 are rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Aeloiza et al (US 10,393,795) disclose a power converter that includes a semiconductor switch and a converter control system. The converter control system is configured to turn on the semiconductor switch, measure a first voltage and a current during reverse conduction, estimate junction temperature of the semiconductor device, turn off the semiconductor device, measure a second voltage after turning off the semiconductor device, determine a resistance value using the second voltage measurement, determine an expected resistance value, predict a failure of the semiconductor device using the resistance value and the expected resistance value, and transmit a semiconductor device failure warning. Wagoner et al (US 9,748,947) disclose a method for operating an insulated gate bipolar transistor (IGBT), including: detecting a desaturation condition in the IGBT; and initiating a turn off procedure when desaturation is detected, the turn off procedure including: holding a gate of the IGBT at at least one voltage level intermediate between raa positive rail voltage and a negative rail voltage of an operational range of the IGBT; and controlling a gate resistance of the IGBT during the turn off procedure; and wherein when the at least one voltage level includes a first voltage and a second voltage less than the first voltage, the gate resistance at the first voltage is lower than the gate resistance at the second voltage. Sundaramoorthy et al (US 9,039,279) disclose a system that includes a differential unit configured to receive a gate-emitter voltage characteristic of the IGBT device to be measured and to differentiate the gate-emitter voltage characteristic to obtain pulses correlating with edges formed by a Miller plateau phase during a switch-off phase of the IGBT device; a timer unit configured to measure the time delay between the obtained pulses indicating the start and end of the Miller plateau phase during the switch-off phase of the IGBT device, and a junction temperature calculation unit configured to determine at least one of the junction temperature of the IGBT device and/or the remaining lifetime of the IGBT device based on the measured time delay. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to AN H DO whose telephone number is (571)272-2143. The examiner can normally be reached on M-F 7:5:30pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Stephen Meier can be reached on 571-272-2149. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AN H DO/Primary Examiner, Art Unit 2853
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Prosecution Timeline

Sep 12, 2023
Application Filed
Dec 27, 2025
Non-Final Rejection — §101
Mar 26, 2026
Response Filed

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
97%
With Interview (+6.7%)
2y 1m
Median Time to Grant
Low
PTA Risk
Based on 1427 resolved cases by this examiner. Grant probability derived from career allow rate.

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