Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on July 27, 2026, has been entered.
Response to Amendment
The amendment filed on July 23, 2026, under 37 CFR 1.312 has been entered. However, the applicant’s amendments to claims 1, 8, and 15 introduce new matter, thus necessitating the rejections under 35 U.S.C. 112(a) detailed below.
Response to Arguments
Applicant's arguments filed July 9, 2026, have been fully considered but they are not persuasive.
Regarding rejections under 35 U.S.C. 102, the applicant makes the argument that Mannebach et. al., Pub. No. US 2020/0219970, hereafter referred to as Mannebach, fails to teach the limitations, “wherein a first portion of a backside surface of the gate contact that is vertically aligned with a lateral extent of one or more of the plurality of nanosheets is smaller than a second portion of the backside surface of the gate contact that is laterally positioned between adjacent nanosheets of the plurality of nanosheets the first portion extending continuously from an inner sidewall to an interior portion of the one or more of the plurality of nanosheets, the second portion extending continuously across and vertically overlapping spaces separating the adjacent nanosheets”, recited in the amended claims 1, 8, and 15. More specifically, the applicant argues that the “spaces separating the adjacent nanosheets” is a structurally-defined region and not simply any region that fails to overlap the nanosheets. The applicant further argues that the examiner’s argument is invalid because it is based on an artificial partitioning of the gate contact surface.
In response to the applicant’s arguments in general, none of the features that the applicant argues are not present in Mannebach were claimed in the previous set of claims but are imported from the specification. While the interpretation of claims may be guided by the specification, claim limitations cannot be imported from the specification (see MPEP 2111.01 II: ““Though understanding the claim language may be aided by explanations contained in the written description, it is important not to import into a claim limitations that are not part of the claim. For example, a particular embodiment appearing in the written description may not be read into a claim when the claim language is broader than the embodiment.” Superguide Corp. v. DirecTV Enterprises, Inc., 358 F.3d 870, 875, 69 USPQ2d 1865, 1868 (Fed. Cir. 2004).”). The applicant’s argument amounts to importation of limitations from the specification that are not recited in the previous claims. In addition, the limitation, “a first portion of a backside surface of the gate contact that is vertically aligned with a lateral extent of one or more of the plurality of nanosheets”, is unsupported in the original disclosure, thus necessitating a rejection under 35 U.S.C. 112(a), as detailed below.
Regarding the applicant’s specific arguments against applying Mannebach to the new claim limitations, all limitations are given their broadest reasonable interpretation (see MPEP 2111). The broadest reasonable interpretation of “spaces separating the adjacent nanosheets” is “any region of the device that lies between the nanosheets”. Furthermore, the claims give no further definition of the first and second portions of the gate contacts other than that the first portion must continuously extend from an inner sidewall of a nanosheet to an interior portion of the nanosheet and that the second portion must extend continuously across and overlap spaces separating adjacent nanosheets. Therefore, any portions of the gate electrode that match these descriptions can be considered to read on the claim language. Given these interpretations, the examiner respectfully argues that Mannebach in fact does teach the new limitations recited in the amended claims.
In light of the above arguments, the examiner maintains that the rejections of the previous claims 1-3 under 35 U.S.C. 102(a)(1) as being anticipated by Mannebach were proper. However, in light of the applicant’s amendments to claims 1, 8, and 15, the previous rejections are rendered moot, necessitating the new grounds of rejection detailed below.
Regarding rejections under 35 U.S.C. 103, the applicant argues that the secondary references, Song et. al., Pub. No. US 2023/0343782, hereafter referred to as Song, and Guler et. al., Pub. No. US 2024/0321872, hereafter referred to as Guler, fail to correct the alleged deficiencies in Mannebach in teaching the limitations of claims 1, 8, and 15 described in the discussion of rejections under 35 U.S.C. 102.
In response to this argument, the examiner must respectfully disagree that there are any deficiencies in Mannebach in teaching the limitations of claim 1 for the reasons detailed above in the discussion of rejections under 35 U.S.C. 102.
In light of the above arguments, the examiner maintains that the rejections of the previous claims 4-5, 8-13 and 15-18 under 35 U.S.C. 103 as being unpatentable under Mannebach in view of Song and of claims 6-7 as being unpatentable under Mannebach in view of Song and Guler were proper. However, in light of the applicant’s amendments to claims 1, 8, and 15, the previous rejections are rendered moot, necessitating the new grounds of rejection detailed below.
Drawings
The drawings are objected to because the figures showing the top view of the device and gate contacts (Figs. 5, 30, and 37) do not show the gate contact 180D overlapping any of the nanodevices ND1-4, but the corresponding cross sectional views (X, Y1, and Y2) do show the gate contact 180D vertically overlapping the nanosheets. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventors, at the time the application was filed, had possession of the claimed invention.
Claim 1 recites the limitation, “the first portion extending continuously from an inner sidewall to an interior portion of the one or more of the plurality of nanosheets”. There is no clear support for this limitation in the original disclosure; it is not disclosed in the written specification and none of the “top view” figures showing the gate contacts (Figs. 5, 30, and 37) show the gate contact (180D) overlapping any of the nanosheets. Therefore, the quoted limitation constitutes new matter.
Claims 2-7 are dependent on claim 1 and thus contain the same new matter.
Claim 8 recites the limitation, “the first portion extending continuously from an inner sidewall to an interior portion of the one or more of the plurality of nanosheets”. There is no clear support for this limitation in the original disclosure; it is not disclosed in the written specification and none of the “top view” figures showing the gate contacts (Figs. 5, 30, and 37) show the gate contact (180D) overlapping any of the nanosheets. Therefore, the quoted limitation constitutes new matter.
Claims 9-14 are dependent on claim 1 and thus contain the same new matter.
Claim 15 recites the limitation, “the first portion extending continuously from an inner sidewall to an interior portion of the one or more of the plurality of nanosheets”. There is no clear support for this limitation in the original disclosure; it is not disclosed in the written specification and none of the “top view” figures showing the gate contacts (Figs. 5, 30, and 37) show the gate contact (180D) overlapping any of the nanosheets. Therefore, the quoted limitation constitutes new matter.
Claims 16-20 are dependent on claim 1 and thus contain the same new matter.
These rejections may be overcome by canceling the limitations in question from the claims.
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Fig. 3A of Mannebach, inverted and with annotations and axes added by the examiner.
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Fig. 3D of Mannebach, inverted and with axes added by the examiner. Dashed lines are also added as a guide to the eye to illustrate the boundaries of the first and second portions of the gate contact.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mannebach.
Regarding claim 1, Mannebach teaches all of the limitations of the claim in Figs. 3A and 3D, reproduced above inverted to align with applicant’s Figs. 50-52 and with annotations and axes added by the examiner: “A semiconductor device” ([0055]; Figs. 3A and 3D, vertical arrangement of active nanoribbons 300, gate dielectric 370, gate electrodes 372 and 374), “comprising: a plurality of nanodevices” ([0055]; device locations 330A-C) “including a plurality of transistors” ([0061]; Figs. 3A and 3D, device locations 308B-C, nanoribbons 350A-C and 360A-C, gate dielectric 370, gate electrodes 372 and 374) “and a plurality of nanosheets” (Figs. 3A and 3D, nanoribbons 350A-C and 360A-C), “wherein the plurality of nanodevices are located adjacent to and parallel to each other along an x-axis” ([0055]; Figs. 3A and 3D, device locations 330A-C, x-axis direction not labeled in the source, but corresponds to the direction out of the page); “a gate contact located at an edge of a cell boundary between two nanodevices of the plurality of nanodevices” ([0070]; Fig. 3D, gate contact 380C, device locations 330B and 330C), “wherein a first portion of a backside surface of the gate contact that is vertically aligned with a lateral extent of one or more of the plurality of nanosheets” (Fig. 3D, note that the first portion of gate contact 380C is vertically aligned with the nanoribbons 350A-C and 360A-C) “is smaller than a second portion of the backside surface of the gate contact that is laterally positioned between adjacent nanosheets of the plurality of nanosheets” (Fig. 3D, note that the second portion of gate contact 380C is larger than the first portion and is laterally positioned between adjacent nanoribbons 350A-C and 360A-C), “the first portion extending continuously from an inner sidewall to an interior portion of the one or more of the plurality of nanosheets” (Fig. 3D; note that the first portion of gate contact 380C extends continuously from sidewalls of the nanoribbons 350A-C and 360A-C to interior portions of said nanoribbons from a top view), “the second portion extending continuously across and vertically overlapping spaces separating the adjacent nanosheets” (Fig. 3D; note that the second portion of gate contact 380C extends across and vertically overlaps a region between adjacent nanoribbons), “wherein the gate contact includes a recessed portion” (Fig. 3D, gate contact 380C), “and a backside gate cut dielectric pillar” ([0055]; Figs. 3A and 3D, fill dielectric layer 320C, dielectric cap 320D, hereafter collectively referred to as pillar 320C-D) “extending downwards through the recessed portion to be in direct contact with the gate contact” (Figs. 3A and 3D, pillar 320C-D, gate contact 380C), “wherein the spaces separating the adjacent nanosheets vertically overlap the backside gate cut dielectric pillar” (Fig. 3D; note that the space between adjacent nanoribbons 350A-C and 360A-C that is overlapped by the second portion of gate contact 380C contains the pillar 320C-D). Mannebach does not designate any specific directions as the x-, y-, or z-axes; for the purposes of examination, the axes added by the examiner are used, which correspond to those used in the instant application.
Regarding claim 2, Mannebach further teaches “The semiconductor device of claim 1, wherein the gate contact has substantially an L-shaped profile through a cross section of a gate region” (Fig. 3D, gate contact 380C).
Regarding claim 3, Mannebach further teaches “The semiconductor device of claim 2, wherein the backside gate cut dielectric pillar is in direct contact with a horizontal section of the L-shaped profile of the gate contact” (Figs. 3A and 3D, pillar 320C-D, gate contact 380C).
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Fig. 1B of Song, reproduced inverted and with annotations added by the examiner.
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Fig. 1D of Song, reproduced above with annotations added by the examiner.
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Fig. 4J of Mannebach, reproduced with annotation added by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 4-5, 8-13, and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Mannebach in view of Song.
Regarding claim 4, Mannebach teaches “The semiconductor device of claim 3”, but does not teach “wherein a frontside surface of the backside gate cut dielectric pillar that is in direct contact with the gate contact has a first width along a y-axis, wherein a backside surface of the backside gate cut dielectric pillar extends a second width along the y-axis, and wherein the second width is greater than the first width”.
Song, on the other hand, does teach “wherein a frontside surface of the backside gate cut dielectric pillar… has a first width along a y-axis, wherein a backside surface of the backside gate cut dielectric pillar extends a second width along the y-axis, and wherein the second width is greater than the first width” (Song Fig. 1D, reproduced above inverted with annotations added by the examiner, gate cut structure CT; also see [0054]: “The horizontal width of the gate cut structure CT may decrease away from the substrate insulating layer 660” (i.e., the backside), “and the horizontal width of the gate cut structure CT may increase away from the interlayer insulating layer 170” (i.e., the frontside).).
The wedge shape of the gate cut structure in Song can be incorporated as the shape of the pillar structure of Mannebach. The combined device of Mannebach and Song just described teaches a backside gate cut dielectric pillar (of Song) “that is in direct contact with the gate contact” (of Mannebach).
It would have been obvious to one of ordinary skill in the art to substitute the wedge-shaped pillar of Song for the pillar of Mannebach because both can serve the purpose of electrically isolating the two adjacent nanodevices and it is a simple substitution of one pillar shape for another with a foreseeable result.
Regarding claim 5, the combination of Mannebach and Song described in the discussion of claim 4 further teaches “The semiconductor device of claim 4, wherein the gate contact is in direct contact with a sidewall of the backside gate cut dielectric pillar” (Mannebach Figs. 3A and 3D, pillar 320C-D, gate contact 380C).
Regarding claim 8, Mannebach teaches “A semiconductor device” (Mannebach [0055]; Figs. 3A and 3D, vertical arrangement of active nanoribbons 300, gate dielectric 370, gate electrodes 372 and 374), “comprising: a plurality of nanodevices” (Mannebach [0055]; Figs. 3A and 3D, device locations 330A-C) “including a plurality of transistors” (Mannebach [0061]; Figs. 3A and 3D, device locations 308B-C, nanoribbons 350A-C and 360A-C, gate dielectric 370, gate electrodes 372 and 374) “and a plurality of nanosheets” (Figs. 3A and 3D, nanoribbons 350A-C and 360A-C), “wherein the plurality of nanodevices are located adjacent to and parallel to each other along an x-axis” (Mannebach [0055]; Figs. 3A and 3D, device locations 330A-C, x-axis direction not labeled in the source, but corresponds to the direction out of the page); “a gate contact located at an edge of a cell boundary between two nanodevices of the plurality of nanodevices” (Mannebach [0070]; Figs. 3A and 3D, gate contact 380C, device locations 330B and 330C), “wherein a first portion of a backside surface of the gate contact that is vertically aligned with a lateral extent of one or more of the plurality of nanosheets” (Fig. 3D, note that the first portion of gate contact 380C is vertically aligned with the nanoribbons 350A-C and 360A-C) “is smaller than a second portion of the backside surface of the gate contact that is laterally positioned between adjacent nanosheets of the plurality of nanosheets” (Fig. 3D, note that the second portion of gate contact 380C is larger than the first portion and is laterally positioned between adjacent nanoribbons 350A-C and 360A-C), “the first portion extending continuously from an inner sidewall to an interior portion of the one or more of the plurality of nanosheets” (Fig. 3D; note that the first portion of gate contact 380C extends continuously from sidewalls of the nanoribbons 350A-C and 360A-C to interior portions of said nanoribbons from a top view), “the second portion extending continuously across and vertically overlapping spaces separating the adjacent nanosheets” (Fig. 3D; note that the second portion of gate contact 380C extends across and vertically overlaps a region between adjacent nanoribbons), “wherein the gate contact includes a recessed portion” (Mannebach Fig. 3D, gate contact 380C), “and a backside gate cut dielectric pillar” (Mannebach [0055]; Figs. 3A and 3D, fill dielectric layer 320C, dielectric cap 320D, hereafter collectively referred to as pillar 320C-D) “extending downwards through the recessed portion to be in direct contact with the gate contact” (Mannebach Figs. 3A and 3D, pillar 320C-D, gate contact 380C), “wherein the spaces separating the adjacent nanosheets vertically overlap the backside gate cut dielectric pillar” (Fig. 3D; note that the space between adjacent nanoribbons 350A-C and 360A-C that is overlapped by the second portion of gate contact 380C contains the pillar 320C-D), but does not teach “a frontside signal line located at the cell boundary between the two nanodevices”. Mannebach does not designate any specific directions as the x-, y-, or z-axes; for the purposes of examination, the axes added by the examiner are used, which correspond to those used in the instant application.
Song, on the other hand, does teach “a frontside signal line located at the cell boundary between the two nanodevices” (Song [0047]; Figs. 1B, reproduced above inverted and with annotations added by the examiner, and 1D, upper wiring structure FS-PDN).
The frontside signal lines of Song can be incorporated into the device of Mannebach as a similar frontside signal line structure.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to incorporate the wiring structure of Song in Mannebach, as it provides a means for providing the voltages on the gate contacts.
Regarding claim 9, the combination of Mannebach and Song described in the discussion of claim 8 further teaches “The semiconductor device of claim 8, wherein the frontside signal line includes a via connected to a frontside of the gate contact” (Song [0045] and [0051]; Fig. 1B, contact plug 220, gate electrode 150).
Regarding claim 10, the combination of Mannebach and Song described in the discussion of claim 8 teaches “The semiconductor device of claim 9”, but does not teach “wherein a frontside surface of the backside gate cut dielectric pillar that is in direct contact with the gate contact has a first width along a y-axis, wherein a backside surface of the backside gate cut dielectric pillar extends a second width along the y-axis, and wherein the second width is greater than the first width”.
Song, on the other hand, does teach “wherein a frontside surface of the backside gate cut dielectric pillar… has a first width along a y-axis, wherein a backside surface of the backside gate cut dielectric pillar extends a second width along the y-axis, and wherein the second width is greater than the first width” (Song Fig. 1D, gate cut structure CT; also see [0054]: “The horizontal width of the gate cut structure CT may decrease away from the substrate insulating layer 660” (i.e., the backside), “and the horizontal width of the gate cut structure CT may increase away from the interlayer insulating layer 170” (i.e., the frontside).).
The wedge shape of the gate cut structure in Song can be incorporated as the shape of the pillar structure of the combination of Mannebach and Song described in the discussion of claim 8. The combined device of Mannebach and Song just described teaches a backside gate cut dielectric pillar (of Song) “that is in direct contact with the gate contact” (of Mannebach).
It would have been obvious to one of ordinary skill in the art to substitute the wedge-shaped pillar of Song for the pillar of the combination of Mannebach and Song described in the discussion of claim 8 because both can serve the purpose of electrically isolating the two adjacent nanodevices and it is a simple substitution of one pillar shape for another with a foreseeable result.
Regarding claim 11, the combination of Mannebach and Song described in the discussion of claim 10 further teaches “The semiconductor device of claim 10, wherein the backside gate cut dielectric pillar progressively narrows from the backside surface to the frontside surface” (Song [0054]; Fig. 1D, gate cut structure CT).
Regarding claim 12, the combination of Mannebach and Song described in the discussion of claim 10 further teaches “The semiconductor device of claim 11” but does not teach “further comprising: a backside power distribution network (BSPDN) in direct contact with the backside surface of the backside gate cut dielectric pillar”. However, it does teach a conductive via (Mannebach [0070]; Fig. 3D, conductive via 396) in direct contact with a backside of the dielectric pillar (Mannebach, Figs. 3A and 3D, pillar 320C-D).
Song, on the other hand, does teach “further comprising: a backside power distribution network (BSPDN)” (Song [0018]; Figs. 1B and 1D, lower wiring structure BS-PDN), but not “in direct contact with the backside surface of the backside gate cut dielectric pillar”.
The wiring structure BS-PDN of Song can be incorporated into the device of Mannebach with one of the vias of Song (Song [0048]; Fig. 1B, vias 654) taking the role of the conductive via of Mannebach (Mannebach [0070]; Fig. 3D, conductive via 396) in contact with the dielectric pillar (Mannebach Figs. 3A and 3D, pillar 320C-D). The combined device of Mannebach and Song just described teaches the limitation, “a backside power distribution network (BSPDN) in direct contact with the backside surface of the backside gate cut dielectric pillar”.
It would have been obvious to one of ordinary skill in the art to introduce the lower wiring structure of Song into the combination of Mannebach and Song described in the discussion of claim 10 because such a wiring structure provides a means for providing voltages to the gate electrodes and the source/drains.
Regarding claim 13, the combination of Mannebach and Song described in the discussion of claim 12 further teaches “The semiconductor device of claim 12, further comprising: a plurality of dielectric spacers in direct contact with a frontside of the BSPDN” (Mannebach Figs. 3A and 3D, liner dielectric layer 320B and etch stop layer 398), “wherein two dielectric spacers of the plurality of dielectric spacers are in direct contact with sidewalls of the backside gate cut dielectric pillar” (Mannebach Figs. 3A and 3D, liner dielectric layer 320B, etch stop layer 398, and pillar 320C-D).
Regarding claim 15, Mannebach teaches “A semiconductor device” (Mannebach [0055]; Fig. 3A, vertical arrangement of active nanoribbons 300, gate dielectric 370, gate electrodes 372 and 374), “comprising: a plurality of nanodevices” (Mannebach [0055]; device locations 330A-C) “including a plurality of transistors” (Mannebach [0061]; Fig. 3A, device locations 308B-C, nanoribbons 350A-C and 360A-C, gate dielectric 370, gate electrodes 372 and 374) “and a plurality of nanosheets” (Figs. 3A and 3D, nanoribbons 350A-C and 360A-C), “wherein the plurality of nanodevices include a plurality of source/drains” (Mannebach [0081]; Fig. 4J, reproduced above with annotation added by the examiner, source/drains 422), “wherein the plurality of nanodevices are located adjacent to and parallel to each other along an x-axis” (Mannebach [0055]; device locations 330A-C, x-axis direction not labeled in the source, but corresponds to the direction out of the page); “a gate contact located at an edge of a cell boundary between two nanodevices of the plurality of nanodevices” (Mannebach [0070]; Fig. 3D, gate contact 380C, device locations 330B and 330C), “wherein a first portion of a backside surface of the gate contact that is vertically aligned with a lateral extent of one or more of the plurality of nanosheets” (Fig. 3D, note that the first portion of gate contact 380C is vertically aligned with the nanoribbons 350A-C and 360A-C) “is smaller than a second portion of the backside surface of the gate contact that is laterally positioned between adjacent nanosheets of the plurality of nanosheets” (Fig. 3D, note that the second portion of gate contact 380C is larger than the first portion and is laterally positioned between adjacent nanoribbons 350A-C and 360A-C), “the first portion extending continuously from an inner sidewall to an interior portion of the one or more of the plurality of nanosheets” (Fig. 3D; note that the first portion of gate contact 380C extends continuously from sidewalls of the nanoribbons 350A-C and 360A-C to interior portions of said nanoribbons from a top view), “the second portion extending continuously across and vertically overlapping spaces separating the adjacent nanosheets” (Fig. 3D; note that the second portion of gate contact 380C extends across and vertically overlaps a region between adjacent nanoribbons), “wherein the gate contact includes a recessed portion” (Mannebach Fig. 3D, gate contact 380C); “a backside gate cut dielectric pillar” (Mannebach [0055]; Figs. 3A and 3D, fill dielectric layer 320C, dielectric cap 320D, hereafter collectively referred to as pillar 320C-D) “extending downwards through the recessed portion to be in direct contact with the gate contact” (Mannebach Figs. 3A and 3D, pillar 320C-D, gate contact 380C), “wherein the spaces separating the adjacent nanosheets vertically overlap the backside gate cut dielectric pillar” (Fig. 3D; note that the space between adjacent nanoribbons 350A-C and 360A-C that is overlapped by the second portion of gate contact 380C contains the pillar 320C-D), but does not teach “a frontside signal line located at the cell boundary between the two nanodevices”. Mannebach does not designate any specific directions as the x-, y-, or z-axes; for the purposes of examination, the axes added by the examiner are used, which correspond to those used in the instant application.
Song, on the other hand, does teach “a frontside signal line located at the cell boundary between the two nanodevices” (Song [0047]; Figs. 1B and 1D, upper wiring structure FS-PDN).
The frontside signal lines of Song can be incorporated into the device of Mannebach as a similar frontside signal line structure.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to incorporate the wiring structure of Song in Mannebach, as it provides a means for providing the voltages on the gate contacts.
Regarding claim 16, the combination of Mannebach and Song described in the discussion of claim 15 teaches “The semiconductor device of claim 15”, but does not teach “wherein a frontside surface of the backside gate cut dielectric pillar that is in direct contact with the gate contact has a first width along a y-axis, wherein a backside surface of the backside gate cut dielectric pillar extends a second width along the y-axis, and wherein the second width is greater than the first width”. However, it does teach a gate contact (Mannebach Fig. 3D, gate contact 380C) in direct contact with a frontside surface of the gate cut dielectric pillar (Mannebach, Figs. 3A and 3D, pillar 320C-D).
Song, on the other hand, does teach “wherein a frontside surface of the backside gate cut dielectric pillar… has a first width along a y-axis, wherein a backside surface of the backside gate cut dielectric pillar extends a second width along the y-axis, and wherein the second width is greater than the first width” (Song Fig. 1D, gate cut structure CT; also see [0054]: “The horizontal width of the gate cut structure CT may decrease away from the substrate insulating layer 660” (i.e., the backside), “and the horizontal width of the gate cut structure CT may increase away from the interlayer insulating layer 170” (i.e., the frontside).).
The wedge shape of the gate cut structure in Song can be incorporated as the shape of the pillar structure of the combination of Mannebach and Song described in the discussion of claim 15. The combined device of Mannebach and Song just described teaches a backside gate cut dielectric pillar (of Song) “that is in direct contact with the gate contact” (of Mannebach).
It would have been obvious to one of ordinary skill in the art to substitute the wedge-shaped pillar of Song for the pillar of the combination of Mannebach and Song described in the discussion of claim 15 because both can serve the purpose of electrically isolating the two adjacent nanodevices and it is a simple substitution of one pillar shape for another with a foreseeable result.
Regarding claim 17, the combination of Mannebach and Song described in the discussion of claim 16 further teaches “The semiconductor device of claim 16, wherein the backside gate cut dielectric pillar extends downwards between the plurality of source/drains” (Mannebach, Figs. 3D, pillar 320C-D, and 4J, source/drains 422).
Regarding claim 18, the combination of Mannebach and Song described in the discussion of claim 16 teaches “The semiconductor device of claim 17”, but does not teach “further comprising: a backside power distribution network (BSPDN) in direct contact with the backside surface of the backside gate cut dielectric pillar; and a plurality of dielectric spacers in direct contact with a frontside of the BSPDN, wherein two dielectric spacers of the plurality of dielectric spacers are in direct contact with sidewalls of the backside gate cut dielectric pillar”. However, it does teach a conductive via (Mannebach [0070]; Fig. 3D, conductive via 396) in direct contact with a backside of the dielectric pillar (Mannebach, Figs. 3A and 3D, pillar 320C-D).
Song, on the other hand, does teach “further comprising: a backside power distribution network (BSPDN)” (Song [0018]; Figs. 1B and 1D, lower wiring structure BS-PDN), but not “in direct contact with the backside surface of the backside gate cut dielectric pillar; and a plurality of dielectric spacers in direct contact with a frontside of the BSPDN, wherein two dielectric spacers of the plurality of dielectric spacers are in direct contact with sidewalls of the backside gate cut dielectric pillar”.
The wiring structure BS-PDN of Song can be incorporated into the device of Mannebach with one of the vias of Song (Song [0048]; Fig. 1B, vias 654) taking the role of the conductive via of Mannebach (Mannebach [0070]; Fig. 3D, conductive via 396) in contact with the dielectric pillar (Mannebach Figs. 3A and 3D, pillar 320C-D). The combined device of Mannebach and Song just described teaches “(a BSPDN) in direct contact with the backside surface of the backside gate cut dielectric pillar”, “a plurality of dielectric spacers in direct contact with a frontside of the BSPDN” (Mannebach Figs. 3A and 3D, liner dielectric layer 320B and etch stop layer 398), and “wherein two dielectric spacers of the plurality of dielectric spacers are in direct contact with sidewalls of the backside gate cut dielectric pillar” (Mannebach Figs. 3A and 3D, liner dielectric layer 320B, etch stop layer 398, and pillar 320C-D).
It would have been obvious to one of ordinary skill in the art to introduce the lower wiring structure of Song into the combination of Mannebach and Song described in the discussion of claim 16 because such a wiring structure provides a means for providing voltages to the gate electrodes and the source/drains.
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470
805
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Fig. 1A of Guler, reproduced with annotation added by the examiner.
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Mockup of the combination of Mannebach, Song, and Guler described in the discussion of claim 6, prepared by the examiner and based on Fig. 3D of Mannebach.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Mannebach and Song, in further view of Guler.
Regarding claim 6, the combination of Mannebach and Song described in the discussion of claim 4 teaches “The semiconductor device of claim 5” but does not teach that “the plurality of nanodevices include at least a first nanodevice, a second nanodevice, a third nanodevice, and a fourth nanodevice, and wherein the gate contact is located between the second nanodevice and the third nanodevice”.
Guler, on the other hand, teaches “the plurality of nanodevices include at least a first nanodevice, a second nanodevice, a third nanodevice, and a fourth nanodevice” (Guler [0032-0038]; Fig. 1A, reproduced above with annotation added by the examiner, semiconductor devices 102a-d, nanoribbons 106, gate structures 112a-d).
The four nanodevices of Guler may be incorporated as a fourth nanodevice in the combination of Mannebach and Song described in the discussion of claim 4 positioned to the right of device location 330C in Fig. 3D of Mannebach (left in the inverted reproduction above) with the thinner barrier shown between device locations 330A and 330B in Fig. 3D of Mannebach (see mockup of this arrangement prepared by the examiner, based on Fig. 3D of Mannebach, above). The combined device of Mannebach, Song, and Guler just described teaches “the gate contact is located between the second nanodevice and the third nanodevice” (Mannebach Fig. 3D, device locations 330B and 330C, gate contact 380C).
It would be obvious to one of ordinary skill in the art before the effective filing date of the application to add a fourth nanodevice to the combination of Mannebach and Song described in the discussion of claim 4 because it would provide additional transistors in a complex electronic device employing the apparatus formed from said combination of Mannebach and Song and is a simple combination of elements of the apparatus of said combination of Mannebach and Song and the apparatus of Guler.
Regarding claim 7, the combination of Mannebach, Song, and Guler further teaches “The semiconductor device of claim 6, wherein the gate contact partially overlaps the third nanodevice” (Mannebach Fig. 3D, device location 330C, gate contact 380C).
Conclusion
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/R.E.T./ Examiner, Art Unit 2818
/CUONG B NGUYEN/ Primary Examiner, Art Unit 2818
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