Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
In paragraph [0040], “silicon germanium (SiGe:C), III-V, II-V compound semiconductor” should be “silicon germanium (SiGe:C), a III-V or II-V compound semiconductor”.
In paragraph [0040], the next-to-last sentence reads, “A portion or the entire semiconductor substrate 105 may also be comprised of an amorphous, polycrystalline, or monocrystalline.”, which is missing a word at the end, presumably “semiconductor”.
In paragraph [0041], “…, together the nanosheet stack, the nanosheet stack” should read “…together, the nanosheet stack”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
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Fig. 3A of Mannebach, inverted and with annotations and axes added by the examiner.
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Fig. 3D of Mannebach, inverted and with annotations and axes added by the examiner.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mannebach et. al., Pub. No. US 2020/0219970 A1, hereafter referred to as Mannebach.
Regarding claim 1, Mannebach teaches all of the limitations of the claim in Figs. 3A and 3D, reproduced above inverted to align with applicant’s Figs. 50-52 and with annotations and axes added by the examiner: “A semiconductor device” ([0055]; Figs. 3A and 3D, vertical arrangement of active nanoribbons 300, gate dielectric 370, gate electrodes 372 and 374), “comprising: a plurality of nanodevices” ([0055]; device locations 330A-C) “including a plurality of transistors” ([0061]; Figs. 3A and 3D, device locations 308B-C, nanoribbons 350A-C and 360A-C, gate dielectric 370, gate electrodes 372 and 374), “wherein the plurality of nanodevices are located adjacent to and parallel to each other along an x-axis” ([0055]; Figs. 3A and 3D, device locations 330A-C, x-axis direction not labeled in the source, but corresponds to the direction out of the page); “a gate contact located at an edge of a cell boundary between two nanodevices of the plurality of nanodevices” ([0070]; Fig. 3D, gate contact 380C, device locations 330B and 330C), “wherein the gate contact includes a recessed portion” (Fig. 3D, gate contact 380C), “and a backside gate cut dielectric pillar” ([0055]; Figs. 3A and 3D, fill dielectric layer 320C, dielectric cap 320D, hereafter collectively referred to as pillar 320C-D) “extending downwards through the recessed portion to be in direct contact with the gate contact” (Figs. 3A and 3D, pillar 320C-D, gate contact 380C). Mannebach does not designate any specific directions as the x-, y-, or z-axes; for the purposes of examination, the axes added by the examiner are used, which correspond to those used in the instant application.
Regarding claim 2, Mannebach further teaches “The semiconductor device of claim 1, wherein the gate contact has substantially an L-shaped profile through a cross section of a gate region” (Fig. 3D, gate contact 380C).
Regarding claim 3, Mannebach further teaches “The semiconductor device of claim 2, wherein the backside gate cut dielectric pillar is in direct contact with a horizontal section of the L-shaped profile of the gate contact” (Figs. 3A and 3D, pillar 320C-D, gate contact 380C).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
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Fig. 1B of Song, reproduced inverted and with annotations added by the examiner.
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Fig. 1D of Song, reproduced inverted and with annotations added by the examiner.
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Fig. 4J of Mannebach, reproduced with annotation added by the examiner.
Claims 4-5, 8-13, and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Mannebach in view of Song et. al., Pub. No. US 2023/0343782 A1, hereafter referred to as Song.
Regarding claim 4, Mannebach teaches “The semiconductor device of claim 3”, but does not teach “wherein a frontside surface of the backside gate cut dielectric pillar that is in direct contact with the gate contact has a first width along a y-axis, wherein a backside surface of the backside gate cut dielectric pillar extends a second width along the y-axis, and wherein the second width is greater than the first width”.
Song, on the other hand, does teach “wherein a frontside surface of the backside gate cut dielectric pillar… has a first width along a y-axis, wherein a backside surface of the backside gate cut dielectric pillar extends a second width along the y-axis, and wherein the second width is greater than the first width” (Song Fig. 1D, reproduced above inverted with annotations added by the examiner, gate cut structure CT; also see [0054]: “The horizontal width of the gate cut structure CT may decrease away from the substrate insulating layer 660” (i.e., the backside), “and the horizontal width of the gate cut structure CT may increase away from the interlayer insulating layer 170” (i.e., the frontside).).
The wedge shape of the gate cut structure in Song is incorporated as the shape of the pillar structure of Mannebach.
It would have been obvious to one of ordinary skill in the art to substitute the wedge-shaped pillar of Song for the pillar of Mannebach because both can serve the purpose of electrically isolating the two adjacent nanodevices and it is a simple substitution of one pillar shape for another with a foreseeable result. The combined device teaches a backside gate cut dielectric pillar (of Song) “that is in direct contact with the gate contact” (of Mannebach).
Regarding claim 5, the combination of Mannebach and Song described in the discussion of claim 4 further teaches “The semiconductor device of claim 4, wherein the gate contact is in direct contact with a sidewall of the backside gate cut dielectric pillar” (Mannebach Figs. 3A and 3D, pillar 320C-D, gate contact 380C).
Regarding claim 8, Mannebach teaches “A semiconductor device” (Mannebach [0055]; Figs. 3A and 3D, vertical arrangement of active nanoribbons 300, gate dielectric 370, gate electrodes 372 and 374), “comprising: a plurality of nanodevices” (Mannebach [0055]; Figs. 3A and 3D, device locations 330A-C) “including a plurality of transistors” (Mannebach [0061]; Figs. 3A and 3D, device locations 308B-C, nanoribbons 350A-C and 360A-C, gate dielectric 370, gate electrodes 372 and 374), “wherein the plurality of nanodevices are located adjacent to and parallel to each other along an x-axis” (Mannebach [0055]; Figs. 3A and 3D, device locations 330A-C, x-axis direction not labeled in the source, but corresponds to the direction out of the page); “a gate contact located at an edge of a cell boundary between two nanodevices of the plurality of nanodevices” (Mannebach [0070]; Figs. 3A and 3D, gate contact 380C, device locations 330B and 330C), “wherein the gate contact includes a recessed portion” (Mannebach Fig. 3D, gate contact 380C), “and a backside gate cut dielectric pillar” (Mannebach [0055]; Figs. 3A and 3D, fill dielectric layer 320C, dielectric cap 320D, hereafter collectively referred to as pillar 320C-D) “extending downwards through the recessed portion to be in direct contact with the gate contact” (Mannebach Figs. 3A and 3D, pillar 320C-D, gate contact 380C), but does not teach “a frontside signal line located at the cell boundary between the two nanodevices”. Mannebach does not designate any specific directions as the x-, y-, or z-axes; for the purposes of examination, the axes added by the examiner are used, which correspond to those used in the instant application.
Song, on the other hand, does teach “a frontside signal line located at the cell boundary between the two nanodevices” (Song [0047]; Figs. 1B, reproduced above inverted and with annotations added by the examiner, and 1D, upper wiring structure FS-PDN).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to incorporate the wiring structure of Song in Mannebach, as it provides a means for providing the voltages on the gate contacts.
Regarding claim 9, the combination of Mannebach and Song described in the discussion of claim 8 further teaches “The semiconductor device of claim 8, wherein the frontside signal line includes a via connected to a frontside of the gate contact” (Song [0045] and [0051]; Fig. 1B, contact plug 220, gate electrode 150).
Regarding claim 10, the combination of Mannebach and Song described in the discussion of claim 8 teaches “The semiconductor device of claim 9”, but does not teach “wherein a frontside surface of the backside gate cut dielectric pillar that is in direct contact with the gate contact has a first width along a y-axis, wherein a backside surface of the backside gate cut dielectric pillar extends a second width along the y-axis, and wherein the second width is greater than the first width”.
Song, on the other hand, does teach “wherein a frontside surface of the backside gate cut dielectric pillar… has a first width along a y-axis, wherein a backside surface of the backside gate cut dielectric pillar extends a second width along the y-axis, and wherein the second width is greater than the first width” (Song Fig. 1D, gate cut structure CT; also see [0054]: “The horizontal width of the gate cut structure CT may decrease away from the substrate insulating layer 660” (i.e., the backside), “and the horizontal width of the gate cut structure CT may increase away from the interlayer insulating layer 170” (i.e., the frontside).).
The wedge shape of the gate cut structure in Song is incorporated as the shape of the pillar structure of the combination of Mannebach and Song described in the discussion of claim 8.
It would have been obvious to one of ordinary skill in the art to substitute the wedge-shaped pillar of Song for the pillar of the combination of Mannebach and Song described in the discussion of claim 8 because both can serve the purpose of electrically isolating the two adjacent nanodevices and it is a simple substitution of one pillar shape for another with a foreseeable result. The combined device teaches a backside gate cut dielectric pillar (of Song) “that is in direct contact with the gate contact” (of Mannebach).
Regarding claim 11, the combination of Mannebach and Song described in the discussion of claim 10 further teaches “wherein the backside gate cut dielectric pillar progressively narrows from the backside surface to the frontside surface” (Song [0054]; Fig. 1D, gate cut structure CT).
Regarding claim 12, the combination of Mannebach and Song described in the discussion of claim 10 further teaches “The semiconductor device of claim 11”, but does not teach “further comprising: a backside power distribution network (BSPDN) in direct contact with the backside surface of the backside gate cut dielectric pillar”. However, it does teach a conductive via (Mannebach [0070]; Fig. 3D, conductive via 396) in direct contact with a backside of the dielectric pillar (Mannebach, Figs. 3A and 3D, pillar 320C-D).
Song, on the other hand, does teach “further comprising: a backside power distribution network (BSPDN)” (Song [0018]; Figs. 1B and 1D, lower wiring structure BS-PDN), but not “in direct contact with the backside surface of the backside gate cut dielectric pillar”.
The wiring structure BS-PDN of Song can be incorporated into the device of Mannebach with one of the vias of Song (Song [0048]; Fig. 1B, vias 654) taking the role of the conductive via of Mannebach (Mannebach [0070]; Fig. 3D, conductive via 396) in contact with the dielectric pillar (Mannebach Figs. 3A and 3D, pillar 320C-D).
It would have been obvious to one of ordinary skill in the art to introduce the lower wiring structure of Song into the combination of Mannebach and Song described in the discussion of claim 10 because such a wiring structure provides a means for providing voltages to the gate electrodes and the source/drains. The combined device teaches the limitation, “a backside power distribution network (BSPDN) in direct contact with the backside surface of the backside gate cut dielectric pillar”.
Regarding claim 13, the combination of Mannebach and Song described in the discussion of claim 12 further teaches “The semiconductor device of claim 12, further comprising: a plurality of dielectric spacers in direct contact with a frontside of the BSPDN” (Mannebach Figs. 3A and 3D, liner dielectric layer 320B and etch stop layer 398), “wherein two dielectric spacers of the plurality of dielectric spacers are in direct contact with sidewalls of the backside gate cut dielectric pillar” (Mannebach Figs. 3A and 3D, liner dielectric layer 320B, etch stop layer 398, and pillar 320C-D).
Regarding claim 15, Mannebach teaches “A semiconductor device” (Mannebach [0055]; Fig. 3A, vertical arrangement of active nanoribbons 300, gate dielectric 370, gate electrodes 372 and 374), “comprising: a plurality of nanodevices” (Mannebach [0055]; device locations 330A-C) “including a plurality of transistors” (Mannebach [0061]; Fig. 3A, device locations 308B-C, nanoribbons 350A-C and 360A-C, gate dielectric 370, gate electrodes 372 and 374), “wherein the plurality of nanodevices include a plurality of source/drains” (Mannebach [0081]; Fig. 4J, reproduced above with annotation added by the examiner, source/drains 422), “wherein the plurality of nanodevices are located adjacent to and parallel to each other along an x-axis” (Mannebach [0055]; device locations 330A-C, x-axis direction not labeled in the source, but corresponds to the direction out of the page); “a gate contact located at an edge of a cell boundary between two nanodevices of the plurality of nanodevices” (Mannebach [0070]; Fig. 3D, gate contact 380C, device locations 330B and 330C), “wherein the gate contact includes a recessed portion” (Mannebach Fig. 3D, gate contact 380C), “and a backside gate cut dielectric pillar” (Mannebach [0055]; Figs. 3A and 3D, fill dielectric layer 320C, dielectric cap 320D, hereafter collectively referred to as pillar 320C-D) “extending downwards through the recessed portion to be in direct contact with the gate contact” (Mannebach Figs. 3A and 3D, pillar 320C-D, gate contact 380C), but does not teach “a frontside signal line located at the cell boundary between the two nanodevices”. Mannebach does not designate any specific directions as the x-, y-, or z-axes; for the purposes of examination, the axes added by the examiner are used, which correspond to those used in the instant application.
Song, on the other hand, does teach “a frontside signal line located at the cell boundary between the two nanodevices” (Song [0047]; Figs. 1B and 1D, upper wiring structure FS-PDN).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the application to incorporate the wiring structure of Song in Mannebach, as it provides a means for providing the voltages on the gate contacts.
Regarding claim 16, the combination of Mannebach and Song described in the discussion of claim 15 teaches “The semiconductor device of claim 15”, but does not teach “wherein a frontside surface of the backside gate cut dielectric pillar that is in direct contact with the gate contact has a first width along a y-axis, wherein a backside surface of the backside gate cut dielectric pillar extends a second width along the y-axis, and wherein the second width is greater than the first width”. However, it does teach a gate contact (Mannebach Fig. 3D, gate contact 380C) in direct contact with a frontside surface of the gate cut dielectric pillar (Mannebach, Figs. 3A and 3D, pillar 320C-D).
Song, on the other hand, does teach “wherein a frontside surface of the backside gate cut dielectric pillar… has a first width along a y-axis, wherein a backside surface of the backside gate cut dielectric pillar extends a second width along the y-axis, and wherein the second width is greater than the first width” (Song Fig. 1D, gate cut structure CT; also see [0054]: “The horizontal width of the gate cut structure CT may decrease away from the substrate insulating layer 660” (i.e., the backside), “and the horizontal width of the gate cut structure CT may increase away from the interlayer insulating layer 170” (i.e., the frontside).).
The wedge shape of the gate cut structure in Song is incorporated as the shape of the pillar structure of the combination of Mannebach and Song described in the discussion of claim 15.
It would have been obvious to one of ordinary skill in the art to substitute the wedge-shaped pillar of Song for the pillar of the combination of Mannebach and Song described in the discussion of claim 15 because both can serve the purpose of electrically isolating the two adjacent nanodevices and it is a simple substitution of one pillar shape for another with a foreseeable result. The combined device teaches a backside gate cut dielectric pillar (of Song) “that is in direct contact with the gate contact” (of Mannebach).
Regarding claim 17, the combination of Mannebach and Song described in the discussion of claim 16 further teaches “The semiconductor device of claim 16, wherein the backside gate cut dielectric pillar extends downwards between the plurality of source/drains” (Mannebach, Figs. 3D, pillar 320C-D, and 4J, source/drains 422).
Regarding claim 18, the combination of Mannebach and Song described in the discussion of claim 16 teaches “The semiconductor device of claim 17”, but does not teach “further comprising: a backside power distribution network (BSPDN) in direct contact with the backside surface of the backside gate cut dielectric pillar; and a plurality of dielectric spacers in direct contact with a frontside of the BSPDN, wherein two dielectric spacers of the plurality of dielectric spacers are in direct contact with sidewalls of the backside gate cut dielectric pillar”. However, it does teach a conductive via (Mannebach [0070]; Fig. 3D, conductive via 396) in direct contact with a backside of the dielectric pillar (Mannebach, Figs. 3A and 3D, pillar 320C-D).
Song, on the other hand, does teach “further comprising: a backside power distribution network (BSPDN)” (Song [0018]; Figs. 1B and 1D, lower wiring structure BS-PDN), but not “in direct contact with the backside surface of the backside gate cut dielectric pillar; and a plurality of dielectric spacers in direct contact with a frontside of the BSPDN, wherein two dielectric spacers of the plurality of dielectric spacers are in direct contact with sidewalls of the backside gate cut dielectric pillar”.
The wiring structure BS-PDN of Song can be incorporated into the device of Mannebach with one of the vias of Song (Song [0048]; Fig. 1B, vias 654) taking the role of the conductive via of Mannebach (Mannebach [0070]; Fig. 3D, conductive via 396) in contact with the dielectric pillar (Mannebach Figs. 3A and 3D, pillar 320C-D).
It would have been obvious to one of ordinary skill in the art to introduce the lower wiring structure of Song into the combination of Mannebach and Song described in the discussion of claim 16 because such a wiring structure provides a means for providing voltages to the gate electrodes and the source/drains. The combined device teaches the limitations, “in direct contact with the backside surface of the backside gate cut dielectric pillar”, “a plurality of dielectric spacers in direct contact with a frontside of the BSPDN” (Mannebach Figs. 3A and 3D, liner dielectric layer 320B and etch stop layer 398), and “wherein two dielectric spacers of the plurality of dielectric spacers are in direct contact with sidewalls of the backside gate cut dielectric pillar” (Mannebach Figs. 3A and 3D, liner dielectric layer 320B, etch stop layer 398, and pillar 320C-D).
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Fig. 1A of Guler, with an annotation added by the examiner.
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Mockup of the combination of Mannebach, Song, and Guler described in the discussion of claim 6, prepared by the examiner and based on Fig. 3D of Mannebach.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Mannebach and Song in further view of Guler et. al., Pub. No. US 2024/0321872, hereafter referred to as Guler.
Regarding claim 6, the combination of Mannebach and Song described in the discussion of claim 4 teaches “The semiconductor device of claim 5”, but does not teach that “the plurality of nanodevices include at least a first nanodevice, a second nanodevice, a third nanodevice, and a fourth nanodevice, and wherein the gate contact is located between the second nanodevice and the third nanodevice”.
Guler, on the other hand, teaches “the plurality of nanodevices include at least a first nanodevice, a second nanodevice, a third nanodevice, and a fourth nanodevice” (Guler [0032-0038]; Fig. 1A, reproduced above with annotation added by the examiner, semiconductor devices 102a-d, nanoribbons 106, gate structures 112a-d).
The four nanodevices of Guler may be incorporated as a fourth nanodevice in the combination of Mannebach and Song described in the discussion of claim 4 positioned to the right of device location 330C in Fig. 3D of Mannebach (left in the inverted reproduction above) with the thinner barrier shown between device locations 330A and 330B in Fig. 3D of Mannebach (see mockup of this arrangement prepared by the examiner, based on Fig. 3D of Mannebach, above).
It would be obvious to one of ordinary skill in the art before the effective filing date of the application to add a fourth nanodevice to the combination of Mannebach and Song described in the discussion of claim 4 because it would provide additional transistors in a complex electronic device employing the apparatus formed from said combination of Mannebach and Song and is a simple combination of elements of the apparatus of said combination of Mannebach and Song and the apparatus of Guler. This combination further teaches that “the gate contact is located between the second nanodevice and the third nanodevice” (Mannebach Fig. 3D, device locations 330B and 330C, gate contact 380C).
Regarding claim 7, the combination of Mannebach, Song, and Guler further teaches “The semiconductor device of claim 6, wherein the gate contact partially overlaps the third nanodevice” (Mannebach Fig. 3D, device location 330C, gate contact 380C).
Allowable Subject Matter
Claims 14 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The cited art, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fails to disclose or suggest the claim limitations of:
Claim 14, which teaches the limitation, “wherein the plurality of dielectric spacers are comprised of a different dielectric material than the plurality of dielectric fills and the backside gate cut dielectric pillar.”
Claim 19, which teaches the limitation, “wherein the BILD layer and the plurality of dielectric spacers are comprised of a different dielectric material.”
Claim 20 depends on claim 19, and thus also contains the same allowable limitation.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT EMIL THROCKMORTON whose telephone number is (571) 272-7014. The examiner can normally be reached 7:30 AM - 12 PM and 1 PM - 5:30 PM ET Monday-Thursday, 7:30 AM - 11:30 AM and 12:30 PM - 4:30 PM ET Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEVEN H LOKE can be reached at (571) 272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/R.E.T./ Examiner, Art Unit 2818
/STEVEN H LOKE/ Supervisory Patent Examiner, Art Unit 2818