DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s arguments filed 2/10/26 have been entered and considered. Claim 2 has been cancelled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-5 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki (US 2011/0309456 A1).
Regarding claim 1, Yamazaki discloses a semiconductor device (Figure 1B) comprising: a substrate (Figure 1B, reference 400); a metal oxide layer (Figure 1B, reference 402) arranged above the substrate and having aluminum as a main component of the metal oxide layer (paragraphs 0041-0042; aluminum oxide); an oxide semiconductor layer (Figure 1B, reference 403) arranged above the metal oxide layer (Figure 1B, reference 402); a gate electrode (Figure 1B, reference 410) facing the oxide semiconductor layer (Figure 1B, reference 403); and a gate insulating layer (Figure 1B, reference 407) between the oxide semiconductor layer (Figure 1B, reference 403) and the gate electrode (Figure 1B, reference 410), wherein a thickness of the metal oxide layer (Figure 1B, reference 402) is 1 nm or more (paragraph 0056).
However, Yamazaki does not specifically disclose wherein a thickness of the metal oxide layer 1nm or more and less than 3nm.
Applicant has not disclosed that having the metal oxide thickness within a specific range (1nm or more and less than 3nm), solves any stated problem or is for any particular purpose. Moreover, it appears that the thickness of the metal oxide in Yamazaki or applicant's invention, would perform equally well within the above range. Accordingly, the claim is obvious without showing that the claimed range(s) achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious). It would have been obvious, prior to the effective filing date of the instant application, for one with ordinary skill in the art to provide a metal oxide with a thickness of 1nm or more and less than 3nm in order to achieve desired thickness to control the energy band gap in high reliability semiconductor devices.
Regarding claim 3, Yamazaki discloses wherein the oxide semiconductor layer (Figure 1B, reference 403) is in contact (thru Figure 1B, reference 404) with the metal oxide layer (Figure 1B, reference 402).
Regarding claim 4, Yamazaki discloses wherein the oxide semiconductor layer is formed in an island shape (Figure 1B, reference 403), and part of the metal oxide layer (Figure 1B, reference 402) extends to outside the oxide semiconductor layer (Figure 1B, reference 403) in a plan view.
Regarding claim 5, Yamazaki discloses wherein the metal oxide layer has a barrier property against oxygen and nitrogen (paragraph 0056).
Regarding claim 9, Yamazaki discloses wherein any semiconductor layers (Figure 1B, none) do not exist between the substrate (Figure 1B, reference 400) and the metal oxide layer (Figure 1B, reference 402).
Claim(s) 6-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki (US 2011/0309456 A1) in view of Ito et al (US 2018/0197997 A1).
Yamazaki discloses the above claimed subject matter. However, Yamazaki does not disclose further comprising a first insulating layer arranged between the substrate and the metal oxide layer, the first insulating layer including oxygen (claim 6).
Ito et al discloses a first insulating layer (Figure 1B, reference 110) arranged between the substrate (Figure 1B, reference 100) and the metal oxide layer (Figure 1B, reference 123), the first insulating layer (Figure 1B, reference 110) including oxygen (paragraph 0170).
It would have been obvious, prior to the effective filing date of the instant application, for one having ordinary skill in the art, to modify Yamazaki with the teachings of Ito et al, for the purpose of forming the first insulating layer in between the substrate and metal oxide layer to supply oxygen to the metal oxide layer in order to prevent diffusion of impurities from the substrate in semiconductor devices.
Regarding claim 7, Yamazaki in view of Ito et al discloses wherein the first insulating layer has a function capable of releasing oxygen by a heat treatment of 600°C or less (paragraph 0171, Ito et al; prima facie case of obviousness as stated above).
Regarding claim 8, Yamazaki in view of Ito et al disclose wherein the metal oxide layer (Figure 1B, reference 121) is in contact with each of the first insulating layer (Figure 1B, reference 110) and the oxide semiconductor layer (Figure 1B, reference 122) between the first insulating layer (Figure 1B, reference 110) and the oxide semiconductor layer (Figure 1B, reference 122, Ito et al; prima facie case of obviousness as stated above).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Takeoka (US 2013/0056833 A1) discloses a metal oxide layer having aluminum as a main component with a thickness of .5nm (paragraphs 0063-0064).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MONICA D HARRISON whose telephone number is (571)272-1959. The examiner can normally be reached M-F 7-4:30pm.
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/MONICA D HARRISON/ Primary Examiner, Art Unit 2815
mdh
March 20, 2026