DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a response to the amendment filed 11/13/2025. Claims 1-23 are pending and are under examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 5, 6, 7, 12, 13-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sachdev et al. (USP 8,022,679) in view of Chen et al. (USP 8,896,363).
Regarding claim 1, Sachdev et al.’s figure 1 shows A power transmission gate comprising: a transistor (108) comprising first, second, third, and fourth terminals with a first one of the terminals corresponding to an input terminal (VIN), a second one of the terminals corresponding to an output terminal (VOUT), a third one of the terminals corresponding to a control terminal (gate electrode), and a fourth one of the terminals corresponding to a body terminal (back gate 108), the switch configured to receive an input voltage at the input terminal thereof and, in response to a control signal having a first value being provided to the control terminal, pass the input voltage to the output terminal of the transistor; a first capacitance (107) between the input and control terminals of the transistor and configured to maintain a substantially constant voltage across the input and control terminals of the transistor (column 3, lines 18-30; column 4, lines 28-40); and a charge pump (104; details are described in USP 6,411,531; see column 2, line 62-63) configured to apply a drive voltage to the control terminal of the transistor, wherein a voltage level of the drive voltage is larger than a voltage level of the input voltage (gate control signal is higher than the input voltage because of the charge pump).
Sachdev et al.’s figure 1 does not show a body control circuit that is configured to control a body of the switch via the body terminal as called for in claim 1.
Chen et al.’s figure 2 shows a transmission gate circuit comprising a switch (101) coupled between input terminal (201) and output terminal (202) with a gate terminal coupled to receive a control signal (D1) and a body terminal coupled to receive a control signal B1. The control signal B1 is generated by a body control circuit (21). The control signal B1 is used to improve the flatness of conducting resistance of the switch (see column 1, lines 40-50; column 10, lines 44-63). Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to have Chen et al.’s body control circuit in Sachdev et al.’s circuit arrangement for the purpose of improving the flatness of the conducting resistance of the switch as taught by Chen et al. reference.
Regarding claim 3, Sachdev et al.’s figure 1 shows wherein the first terminal of the transistor is a source terminal, the second terminal of the transistor is a drain terminal, the third terminal of the transistor is a gate terminal, and the fourth terminal of the transistor is a body terminal.
Regarding claim 5, the charge pump comprises a capacitor (8, see details of the charge pump in USP 6,411,531) that is configured to charge a gate of the transistor to about twice the input voltage.
Regarding claim 6, USP 6,411,531’s charge pump shows wherein the charge pump comprises a switch network (30) that is connected to the capacitor (8).
Regarding claim 7, USP6,411,531’s switch network are configured to operate at a variable clock frequency (clock frequency of figure 6B is different from clock frequency of figure 8B).
Regarding claim 12, Sachdev et al.’s figure 1 shows further comprising a shutdown circuit (103) having a terminal coupled to the control terminal of the switch and configured to discharge the voltage at the control terminal of the switch when the transistor is disabled.
Regarding claim 13, Sachdev et al.’s figure 1 shows wherein the switch is an NMOS transistor.
Regarding claim 14, Sachdev et al.’s charge pump is capable of being a Dickson or Pelliconi topology.
Regarding claim 15, Sachdev et al.’s figure 1 shows the power transmission gate satisfies one or more safe operating area conditions of the NMOS transistor.
Regarding claim 16, Sachdev et al.’s figure 1 shows the power transmission gate is a pulse shaping network switch.
Regarding claim 17, Sachdev et al.’s power transmission gate is configured capable of carrying currents in the order of amperes.
Regarding claim 18, Sachdev et al.’s power transmission gate is configured to capable of responding to changes in the input voltage that occur in the order of nanoseconds.
Regarding claims 19-20, the combination of Sachdev et al. and Chen et al. reference shows the body control circuit (21), as noted above, comprising a first NMOS transistor (211) that is configured to drive the body of the switch to a first voltage (Vin at node 201) when the switch is enabled; and a second NMOS transistor that is configured to drive the body of the switch to a second voltage (Ground) different than the first voltage when the switch is disabled (see Chen et al.’s column 5, lines 18-67).
Allowable Subject Matter
Claims 2, 4, 8, 9, 10, 11, 21, 22 and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN THIEU LAM whose telephone number is (571)272-1744. The examiner can normally be reached Monday-Friday, 8:30 am to 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lincoln Donovan can be reached on 571-272-1988. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TUAN T LAM/Primary Examiner, Art Unit 2842 11/15/2025