Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsubara et al. (US Patent No. 20160307854) in view of Milo et al. (US Patent No. 20210202365) and Ozaki et al. (US Patent No. 20160372394).
Regarding claim 1, Matsubara et al. disclose a semiconductor device comprising: a plurality of conductive members (31, 32, Fig. 2) including a first member (111) and a second member (112); a first semiconductor element electrically connected to one of the plurality of conductive members (paragraph 77); a second semiconductor element electrically connected to one of the plurality of conductive members (paragraph 79 )and configured to receive input of a voltage different from a voltage applied to the first semiconductor element (paragraph 36); and a sealing resin covering a part of each of the plurality of conductive members (paragraphs 10 and 11), the first semiconductor element, and the second semiconductor element, wherein a voltage applied to the second member differs from a voltage applied to the first member (paragraph 36).
However, Matsubara et al. do not explicitly disclose a square cross section having a side length equal to 2/3 of a minimum spacing between two adjacent conductive members of the plurality of conductive members is hypothetically defined in the sealing resin.
On the other hand, Milo et al. disclose a minimum distance of gaps (144) spacing leads (143) from pad (141) is no greater than 150 microns (paragraph 43).
Neither Matsubara et al. nor Milo et al. explicitly disclose fillers each having a particle size equal to or greater than 1/8 of the minimum spacing and at least partially contained in the square cross section, or a sealing resin contains fillers that are electrically insulating.
On the other hand, Ozaki et al. disclose the particle size of the inorganic filler is preferably at least 0.01 μm and not greater than 150 μm, from the viewpoint of the filling properties into a mold cavity. Although the maximum particle size of the inorganic filler is not particularly limited, when considering the prevention of malfunction such as wire sweep which is caused by the coarse particles of the inorganic filler getting stuck in the narrow space between the wires, it is preferably 105 μm or less, and more preferably 75 μm or less (paragraph 94).
Ozaki et al. teach the sealing resin contains fillers that are electrically insulating (Ozaki et al. also disclose the inorganic filler is not particularly limited, and examples thereof include fused silica, crystalline silica, alumina, silicon nitride and aluminum nitride. Fused silica is preferably used, and spherical fused silica is more preferably used. One type of these inorganic fillers may be used alone or two or more types thereof may be mixed and used in combination. (paragraph 93)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Matsubara et al. according to the teachings of Milo et al. and Ozaki et al. such that the size of the particle fillers is small enough, such as .05 μm, so that it fits within 2/3 minimum spacing between leads, for example, 150 microns; and choosing a particle filler material that is electrically insulating, such as silica.
With respect to claim 16, Matsubara et al. and Milo et al. fail to teach the semiconductor device according to claim 1, wherein composition of the fillers includes silicon dioxide.
However, Ozaki et al. teach the semiconductor device according to claim 1, wherein composition of the fillers includes silicon dioxide (paragraph 93). This merely provides a different type of filler.
Claim(s) 2-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsubara et al. (US Patent No. 20160307854) in view Milo et al. (US Patent No. 20210202365) and Ozaki et al. (US Patent No. 20160372394) as applied to claim 1 above, and further in view of Jones et al. (US Patent No. 20140239472).
Matsubara, Milo and Ozaki fail to disclose maximum particle sizes of the fillers is ½ of the minimum spacing.
Regarding claim 2, Jones et al. disclose the semiconductor device according to claim 1, wherein a maximum particle size of the fillers is 1/2 of the minimum spacing (paragraph 26). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above according to the teachings of Jones et al. to make the particles less than one half the width of the gap because changing the size would be within the range of the physical particle size. Doing so, would allow the filler to flow better.
Regarding claim 3, Matsubara et al. disclose the semiconductor device according to claim 2, wherein the first member and the second member are spaced apart from each other in a first direction orthogonal to a thickness direction of each of the first semiconductor element and the second semiconductor element (paragraph 37), the first semiconductor element is mounted on the first member (111), the second semiconductor element is mounted on the second member (112).
However, Matsubara does not mention the spacing between the conductive members is equal to or greater than 1.0 times and equal to or less than 3.0 times the minimum spacing.
To provide the spacing between the conductive members requires merely routine skill in the art.
It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify the arts cited above such that a desired spacing is obtained to prevent shorts or avoid leakage and dielectric breakdown.
Regarding claim 4, Matsubara et al. disclose the semiconductor device according to claim 3, wherein the first semiconductor element is electrically connected to the first member (paragraph 43).
Regarding claim 5, Matsubara et al. disclose the semiconductor device according to claim 4, wherein the second semiconductor element is electrically connected to the second member (paragraph 51).
Regarding Claim 6, Matsubara et al. disclose the semiconductor device according to claim 3, wherein the plurality of conductive members include a plurality of first terminals located on one side in the first direction and a plurality of second terminals located on the other side in the first direction, the first semiconductor element is electrically connected to the plurality of first terminals (paragraph 43), and the second semiconductor element is electrically connected to the plurality of second terminals (paragraph 48).
Regarding claim 7, Matsubara et al. disclose the semiconductor device according to claim 6, wherein the plurality of first terminals and the plurality of second terminals are arranged along a second direction orthogonal to the first direction (paragraph 32, 62-63).
Regarding claim 8, Matsubara et al. disclose the semiconductor device according to claim 7, wherein the first member includes a first island portion on which the first semiconductor element is mounted and two first suspension lead portions connected to opposite ends in the second direction of the first island portion, and the two first suspension lead portions are exposed from one side of the sealing resin in the first direction (paragraph 61-62).
Regarding claim 9, Matsubara et al. disclose the semiconductor device according to claim 8, wherein the second member includes a second island portion on which the second semiconductor element is mounted and two second suspension lead portions connected to opposite ends in the second direction of the second island portion, and the two second suspension lead portions are exposed from the other side of the sealing resin in the first direction (paragraph 63-64).
Regarding claim 10, Matsubara et al. does not disclose the semiconductor device according to claim 9, wherein the second island portion overlaps with the first island portion as viewed in the first direction.
However, rearrangement of parts is within the routine skill level of one in the art. The is a design choice. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950).
On the other hand, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the arts cited above to overlap the islands, since this physical placement of the islands is within the routine skill level in the art. Doing so, would improve performance and save space.
Regarding claim 11, Matsubara et al. disclose the semiconductor device according to claim 3, wherein the voltage applied to the second member (112, Fig 2) is higher than the voltage applied to the first member (111, Fig. 2) (paragraph 36).
With respect to claim 12, Matsubara et al. disclose the semiconductor device according to claim 3, further comprising an insulating element (12, Fig. 2) that relays signals between the first semiconductor element and the second semiconductor element and insulates the first semiconductor element and the second semiconductor element from each other, wherein the insulating element is of an inductive type (paragraph 36).
Regarding claim 13, Matsubara et al. disclose the semiconductor device according to claim 12, wherein the insulating element (12, Fig. 2) is mounted on the first member (paragraph 37).
Regarding claim 14, Matsubara et al. disclose the semiconductor device according to claim 12, wherein the insulating element (12, Fig. 2) is mounted on the second member (paragraph 37).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Matsubara et al. (US Patent No. 20160307854) in view Milo et al. (US Patent No. 20210202365), Ozaki et al. (US Patent No. 20160372394), and Jones et al. (US Patent No. 20140239472) as applied to claim(s) 2-14 above, in further view of Abe et al. (US Patent No. 20210305175).
Regarding claim 15, Matsubara et al. disclose the semiconductor device according to claim 12, further comprising a first wire and a second wire (711, Fig. 2), wherein the first wire is bonded to the insulating element and the first semiconductor element, the second wire is bonded to the insulating element and the second semiconductor element (paragraph 76-80).
None of the references disclose the composition of the first wire and the second wire includes gold.
On the other hand, Abe et al. disclose composition of the first wire and the second wire includes gold (paragraph 77). It would have been obvious to one of ordinary skill in the art at the time of the filing date to modify the arts cited above according to the teachings of Abe et al. to make the bonding wires gold, because gold is resistant to corrosion and is highly conductive.
Response to Arguments
Applicant's arguments filed 2/24/2026 have been fully considered but they are not persuasive. With respect to applicant’s arguments against the rejection of claim 1 that Ozaki discloses a particle filler of size .05 micrometers, therefore, cannot be used in combination with Matsubara and Milo to show eight or more fillers each having a particle size equal to or greater than 1/8 of the minimum spacing. Ozaki shows that the particle size of the inorganic filler is preferably at least 0.01 micrometers and not greater than 150 micrometers (paragraph 94). This range is within the applicant’s argument that the particle size would be at least 18.75 micrometers such that “eight or more of the fillers each having a particle size equal to or greater than 1/8 of the minimum spacing are at least partially contained in the cross section”.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE Q PHAN whose telephone number is (571)272-1227. The examiner can normally be reached Monday - Friday 8am - 5pm.
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/STEVE PHAN/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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